Hi Daniel,
Could you please check changes in the documentation,
I've added a new HDMI connector properties section, based on our discussion.
I think now other HDMI specific properties can be transferred there as well.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357
On 04/25/2018 08:49 AM, Daniel Vetter wrote:
On Wed, Apr 25, 2018 at 8:42 AM, Thomas Hellstrom wrote:
Hi,
On 12/07/2017 03:49 PM, Daniel Vetter wrote:
We're spotting this very rarely in CI, but have no idea. Let's add
more debug info about what's going on here.
References:
https://urldefens
== Series Details ==
Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev7)
URL : https://patchwork.freedesktop.org/series/36068/
State : failure
== Summary ==
Applying: drm/i915: Introduce CRTC output format
Applying: drm/i915: Add CRTC output format YCBCR 4:2:0
error: sha1 information is
On Tue, Apr 17, 2018 at 02:31:47PM +0300, Imre Deak wrote:
> Add documentation to gen9_set_dc_state() on what enabling a given DC
> state means and at what point HW/DMC actually enters/exits these states.
>
> Cc: Jani Nikula
> Cc: Daniel Vetter
> Signed-off-by: Imre Deak
lgtm.
Reviewed-by: Da
Ping.
-Daniel
On Tue, Mar 20, 2018 at 9:51 AM, Daniel Vetter wrote:
> At least trackpoint_disconnect wants to remove some sysfs files, and
> we can't remove sysfs files while holding psmouse_mutex:
>
> ==
> WARNING: possible circular locking dep
On 24/04/2018 15:57, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-04-24 15:46:49)
On 24/04/2018 14:14, Chris Wilson wrote:
In the next patch, rings are the central timeline as requests may jump
between engines. Therefore in the future as we retire in order along the
engine timeline, we ma
Quoting Tvrtko Ursulin (2018-04-25 10:30:51)
> Related, there could be potential to unify i915_request_retire_upto and
> ring_retire_requests. Latter could pass in NULL as the upto request,
> just the completed check would need to be different depending on the mode.
Also remember that _upto is t
Cc: Rodrigo, DK, Ville
On Tue, 17 Apr 2018, Imre Deak wrote:
> Add documentation to gen9_set_dc_state() on what enabling a given DC
> state means and at what point HW/DMC actually enters/exits these states.
>
> Cc: Jani Nikula
> Cc: Daniel Vetter
> Signed-off-by: Imre Deak
> ---
> drivers/gp
Argh, now with Ville's correct address.
On Wed, 25 Apr 2018, Jani Nikula wrote:
> Cc: Rodrigo, DK, Ville
>
> On Tue, 17 Apr 2018, Imre Deak wrote:
>> Add documentation to gen9_set_dc_state() on what enabling a given DC
>> state means and at what point HW/DMC actually enters/exits these states.
When WaIdleLiteRestore isn't enough.
---
drivers/gpu/drm/i915/intel_lrc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 029901a8fa38..5c50263e45d3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/driv
We don't need to track every ring for its lifetime as they are managed
by the contexts/engines. What we do want to track are the live rings so
that we can sporadically clean up requests if userspace falls behind. We
can simply restrict the gt->rings list to being only gt->live_rings.
v2: s/live/ac
We need to move to a more flexible timeline that doesn't assume one
fence context per engine, and so allow for a single timeline to be used
across a combination of engines. This means that preallocating a fence
context per engine is now a hindrance, and so we want to introduce the
singular timeline
In the future, we want to move a request between engines. To achieve
this, we first realise that we have two timelines in effect here. The
first runs through the GTT is required for ordering vma access, which is
tracked currently by engine. The second is implied by sequential
execution of commands
In commit 9b6586ae9f6b ("drm/i915: Keep a global seqno per-engine"), we
moved from a global inflight counter to per-engine counters in the
hope that will be easy to run concurrently in future. However, with the
advent of the desire to move requests between engines, we do need a
global counter to pr
In the next patch, rings are the central timeline as requests may jump
between engines. Therefore in the future as we retire in order along the
engine timeline, we may retire out-of-order within a ring (as the ring now
occurs along multiple engines), leading to much hilarity in miscomputing
the pos
When userspace is passing around swapbuffers using DRI, we frequently
have to open and close the same object in the foreign address space.
This shows itself as the same object being rebound at roughly 30fps
(with a second object also being rebound at 30fps), which involves us
having to rewrite the
When WaIdleLiteRestore isn't enough.
Fixes an odd hang on gen8 (both bsw and bdw) during gem_ctx_switch,
where by all intents and purposes if we trigger a lite-restore as it is
processing the pipecontrol flushes, the RING is restored to the oword
following the command and tries to execute the dest
On Wed, Apr 25, 2018 at 12:50:06PM +0300, Jani Nikula wrote:
>
> Argh, now with Ville's correct address.
>
> On Wed, 25 Apr 2018, Jani Nikula wrote:
> > Cc: Rodrigo, DK, Ville
> >
> > On Tue, 17 Apr 2018, Imre Deak wrote:
> >> Add documentation to gen9_set_dc_state() on what enabling a given DC
Chris Wilson writes:
> When WaIdleLiteRestore isn't enough.
>
> Fixes an odd hang on gen8 (both bsw and bdw) during gem_ctx_switch,
Do you have a testcase name? (testcase tag would be nice too)
> where by all intents and purposes if we trigger a lite-restore as it is
> processing the pipecontro
Quoting Mika Kuoppala (2018-04-25 12:19:08)
> Chris Wilson writes:
>
> > When WaIdleLiteRestore isn't enough.
> >
> > Fixes an odd hang on gen8 (both bsw and bdw) during gem_ctx_switch,
>
> Do you have a testcase name? (testcase tag would be nice too)
Just keep running gem_ctx_switch. Switching
Quoting Chris Wilson (2018-04-25 12:23:30)
> Quoting Mika Kuoppala (2018-04-25 12:19:08)
> > Did you try with WA_TAIL_DWORDS 16?
>
> Sure can try, but the error state doesn't indicate TAIL==HEAD as would
> be the issue with WaIdleLiteRestore (restoring to an idle ring wouldn't
> generate the arbit
Hi all,
This is an update a series that was sent out a few months ago. The end
goal here is to optimize some media workloads.
Here is some information provided by Dmitry (cc) on why we want this :
Video decoding/encoding tends to work with macroblocks, dividing up a
frame into smaller elements.
Let's put this in its own function to reuse it later.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_lrc.c | 59 ++--
1 file changed, 34 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
i
From: Chris Wilson
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may
This function will be used later by the per (context,engine) power
programming interface.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h| 3 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 18 +-
2 files changed, 12 insertions(+), 9 deletions(-
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration pe
Rather than accessing it from the engine structure. This will be used
for reprogramming later.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_lrc.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/dr
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes. We need to reprogram them at
context switch.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
dr
We can rely on the i915_vma_pin() to use vma->size instead.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 407a44a341b9..3ca5a1d33f
From: Chris Wilson
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI). If the context is adjusted before
Quoting Lionel Landwerlin (2018-04-25 12:45:14)
> This function will be used later by the per (context,engine) power
> programming interface.
No. This is not the appropriate uABI, please see
intel_engine_lookup_user().
-Chris
___
Intel-gfx mailing list
I
Quoting Lionel Landwerlin (2018-04-25 12:45:16)
> We can rely on the i915_vma_pin() to use vma->size instead.
But that's the alignment parameter. I didn't change it as I have no idea
why it was set to PAGE_SIZE. i915_vma_pin() treats it as 0 anyway.
-Chris
_
== Series Details ==
Series: series starting with [1/7] drm/i915/execlists: Skip lite restore on the
currently executing request
URL : https://patchwork.freedesktop.org/series/42280/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4b4a1828d89c drm/i915/execlists: Skip lite resto
Quoting Lionel Landwerlin (2018-04-25 12:45:19)
> If some of the contexts submitting workloads to the GPU have been
> configured to shutdown slices/subslices, we might loose the NOA
> configurations written in the NOA muxes. We need to reprogram them at
> context switch.
On every single batchbuffe
== Series Details ==
Series: series starting with [1/7] drm/i915/execlists: Skip lite restore on the
currently executing request
URL : https://patchwork.freedesktop.org/series/42280/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/execlists: Skip lite restore on the
== Series Details ==
Series: series starting with [1/7] drm/i915/execlists: Skip lite restore on the
currently executing request
URL : https://patchwork.freedesktop.org/series/42280/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4093 -> Patchwork_8795 =
== Summary - FAILUR
On 24 April 2018 at 20:14, Daniel Vetter wrote:
> On Tue, Apr 24, 2018 at 7:30 PM, Emil Velikov
> wrote:
>> On 13 April 2018 at 11:00, Daniel Vetter wrote:
>>> This tries to align with the X.org communities's long-standing
>>> tradition of trying to be an inclusive community and handing out
>>>
== Series Details ==
Series: drm/i915/execlists: Skip lite restore on the currently executing request
URL : https://patchwork.freedesktop.org/series/42281/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4093 -> Patchwork_8796 =
== Summary - FAILURE ==
Serious unknown chan
== Series Details ==
Series: drm/i915: per context slice/subslice powergating
URL : https://patchwork.freedesktop.org/series/42285/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aad432b4239c drm/i915: expose helper mapping exec flag engine to intel_engine_cs
f01ac5929e4d drm/i9
== Series Details ==
Series: drm/i915: per context slice/subslice powergating
URL : https://patchwork.freedesktop.org/series/42285/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: expose helper mapping exec flag engine to intel_engine_cs
-drivers/gpu/drm/i915/selfte
When filling the ring to align the emit pointer to the next cacheline,
use memset64() rather than open-coding it. As we know that we always
have an even number of dwords, we can replace the dword loop with the
qword equivalent.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffe
Quoting Chris Wilson (2018-04-25 12:31:29)
> Quoting Chris Wilson (2018-04-25 12:23:30)
> > Quoting Mika Kuoppala (2018-04-25 12:19:08)
> > > Did you try with WA_TAIL_DWORDS 16?
> >
> > Sure can try, but the error state doesn't indicate TAIL==HEAD as would
> > be the issue with WaIdleLiteRestore (
== Series Details ==
Series: drm/i915: per context slice/subslice powergating
URL : https://patchwork.freedesktop.org/series/42285/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4093 -> Patchwork_8797 =
== Summary - SUCCESS ==
No regressions found.
External URL:
http
== Series Details ==
Series: drm/i915: Use memset64() to align the ring with MI_NOOP
URL : https://patchwork.freedesktop.org/series/42290/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a2d0462fc7d0 drm/i915: Use memset64() to align the ring with MI_NOOP
-:41: CHECK:SPACING: spa
== Series Details ==
Series: drm/i915: Use memset64() to align the ring with MI_NOOP
URL : https://patchwork.freedesktop.org/series/42290/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4093 -> Patchwork_8798 =
== Summary - SUCCESS ==
No regressions found.
External URL
Quoting Chris Wilson (2018-04-25 13:45:45)
> Quoting Chris Wilson (2018-04-25 12:31:29)
> > Quoting Chris Wilson (2018-04-25 12:23:30)
> > > Quoting Mika Kuoppala (2018-04-25 12:19:08)
> > > > Did you try with WA_TAIL_DWORDS 16?
> > >
> > > Sure can try, but the error state doesn't indicate TAIL==
Quoting Chris Wilson (2018-04-25 12:57:24)
> If they are not context saved, userspace isn't going to be allowed to
> modify them. So why do we need this? If they not context saved, then the
> kernel needs to control them and doesn't need to reset around every
> batch, just the one's that want non-d
On Wed, Apr 25, 2018 at 01:27:20PM +0100, Emil Velikov wrote:
> On 24 April 2018 at 20:14, Daniel Vetter wrote:
> > On Tue, Apr 24, 2018 at 7:30 PM, Emil Velikov
> > wrote:
> >> On 13 April 2018 at 11:00, Daniel Vetter wrote:
> >>> This tries to align with the X.org communities's long-standing
On 25/04/2018 13:37, Chris Wilson wrote:
When filling the ring to align the emit pointer to the next cacheline,
use memset64() rather than open-coding it. As we know that we always
have an even number of dwords, we can replace the dword loop with the
qword equivalent.
Signed-off-by: Chris Wilso
On Tue, Apr 24, 2018 at 09:36:29PM +0200, Daniel Vetter wrote:
> On Tue, Apr 24, 2018 at 05:26:30PM +0300, Ville Syrjälä wrote:
> > On Tue, Apr 24, 2018 at 04:18:37PM +0200, Daniel Vetter wrote:
> > > On Tue, Apr 24, 2018 at 04:02:50PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > >
Quoting Tvrtko Ursulin (2018-04-25 15:00:43)
>
> On 25/04/2018 13:37, Chris Wilson wrote:
> > When filling the ring to align the emit pointer to the next cacheline,
> > use memset64() rather than open-coding it. As we know that we always
> > have an even number of dwords, we can replace the dword
On Wed, Apr 25, 2018 at 07:03:14PM +0800, Antony Chen wrote:
> Hi all,
>
> The patch works: drivers/gpu/drm/drm_edid.c
> I switch 4K@60 and 4K@30 monitors some times, monitors show correct output.
> Thanks for your help.
>
> What are the steps to close the issue in freedesktop? Append the patch b
On 25/04/2018 15:09, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-04-25 15:00:43)
On 25/04/2018 13:37, Chris Wilson wrote:
When filling the ring to align the emit pointer to the next cacheline,
use memset64() rather than open-coding it. As we know that we always
have an even number of dwo
A more complete, and more importantly stable, interface for controlling
the RPS frequency range is available in sysfs, obsoleting the unstable
debugfs.
It's presence seems to trick people into using it, forgetting it is not
ABI.
References: https://bugs.freedesktop.org/show_bug.cgi?id=106237
Sign
On 25/04/18 12:57, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-04-25 12:45:19)
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes. We need to reprogram them at
context s
== Series Details ==
Series: drm/i915: Remove obsolete min/max freq setters from debugfs
URL : https://patchwork.freedesktop.org/series/42293/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4094 -> Patchwork_8799 =
== Summary - FAILURE ==
Serious unknown changes coming wi
Quoting Michel Thierry (2018-04-24 23:27:41)
> On 4/24/2018 2:39 PM, Oscar Mateo wrote:
> > Interrupt handling in Gen11 is quite different from previous platforms.
> >
> > v2: Rebased (Michel)
> > v3: Rebased with wiggle
> > v4: Rebased, remove TODO warning correctly (Daniele)
> > v5: Rebased, mad
== Series Details ==
Series: drm/i915: per context slice/subslice powergating
URL : https://patchwork.freedesktop.org/series/42285/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4093_full -> Patchwork_8797_full =
== Summary - FAILURE ==
Serious unknown changes coming wit
== Series Details ==
Series: drm/i915: Use memset64() to align the ring with MI_NOOP
URL : https://patchwork.freedesktop.org/series/42290/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4093_full -> Patchwork_8798_full =
== Summary - WARNING ==
Minor unknown changes comin
== Series Details ==
Series: drm/i915: Remove obsolete min/max freq setters from debugfs
URL : https://patchwork.freedesktop.org/series/42293/
State : failure
== Summary ==
Applying: drm/i915: Remove obsolete min/max freq setters from debugfs
Using index info to reconstruct a base tree...
M
Hi all,
The patch works: drivers/gpu/drm/drm_edid.c
I switch 4K@60 and 4K@30 monitors some times, monitors show correct output.
Thanks for your help.
What are the steps to close the issue in freedesktop? Append the patch by Ville
Syrjälä, then I close it?
Antony
2018-04-25 3:36 GMT+08:00 Daniel
On Wed, Apr 25, 2018 at 02:09:14PM +0300, Imre Deak wrote:
> On Wed, Apr 25, 2018 at 12:50:06PM +0300, Jani Nikula wrote:
> >
> > Argh, now with Ville's correct address.
> >
> > On Wed, 25 Apr 2018, Jani Nikula wrote:
> > > Cc: Rodrigo, DK, Ville
> > >
> > > On Tue, 17 Apr 2018, Imre Deak wrote
On Wed, Apr 25, 2018 at 03:23:34PM +0100, Chris Wilson wrote:
> A more complete, and more importantly stable, interface for controlling
> the RPS frequency range is available in sysfs, obsoleting the unstable
> debugfs.
>
> It's presence seems to trick people into using it, forgetting it is not
>
On Tue, Apr 24, 2018 at 05:34:14PM -0700, Paulo Zanoni wrote:
> Em Qui, 2018-04-05 às 17:20 -0700, Rodrigo Vivi escreveu:
> > On Thu, Feb 22, 2018 at 12:55:10AM -0300, Paulo Zanoni wrote:
> > > From: Manasi Navare
> > >
> > > This is an important part of the DDI initalization as well as
> > > for
On Wed, 2018-04-25 at 10:45 -0700, Rodrigo Vivi wrote:
> On Wed, Apr 25, 2018 at 02:09:14PM +0300, Imre Deak wrote:
> > On Wed, Apr 25, 2018 at 12:50:06PM +0300, Jani Nikula wrote:
> > >
> > > Argh, now with Ville's correct address.
> > >
> > > On Wed, 25 Apr 2018, Jani Nikula wrote:
> > > > Cc
On Tue, 2018-04-17 at 14:31 +0300, Imre Deak wrote:
> Add documentation to gen9_set_dc_state() on what enabling a given DC
> state means and at what point HW/DMC actually enters/exits these states.
>
> Cc: Jani Nikula
> Cc: Daniel Vetter
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i9
On Thu, Apr 05, 2018 at 05:39:01PM +0300, Jani Nikula wrote:
> Abstract a new intel_dp_compute_link_config() from
> intel_dp_compute_config(), with the parts related to link configuration,
> i.e. bpp, link rate, and lane count selection. No functional changes.
>
This abstraction makes it cleaner a
On Thu, Apr 05, 2018 at 05:39:03PM +0300, Jani Nikula wrote:
> Also use same min/max model for bpp, and adjust debug logging while at
> it.
>
Reviewed-by: Manasi Navare
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dp.c | 57
> -
> 1
Hi Dave,
Here's the latest from -misc-fixes. Of note, no nasty backmerges as per the
thread on dim-tools. We have one regression fix, and two stable fixes, and a
couple of regular fixes for your consideration.
drm-misc-fixes-2018-04-25:
sun41: Fix regression for TBSA711 tablet (Ondrej)
qxl: 2 bug
On Tue, 2018-04-24 at 16:47 -0700, Dhinakaran Pandiyan wrote:
>
>
> On Fri, 2018-04-20 at 15:27 -0700, José Roberto de Souza wrote:
> > This will be helpful to debug what hardware is actually tracking
> > and causing PSR to exit.
> >
> > BSpec: 7721
> >
> > Signed-off-by: José Roberto de Souza
On Tue, 2018-04-24 at 17:18 -0700, Dhinakaran Pandiyan wrote:
>
>
> On Fri, 2018-04-20 at 15:27 -0700, José Roberto de Souza wrote:
> > IGT tests could be improved with sink status, knowing for sure that
> > hardware have activate or exit PSR.
> >
> > Reviewed-by: Dhinakaran Pandiyan
> > Cc: Ro
On Tue, 2018-04-24 at 17:16 -0700, Dhinakaran Pandiyan wrote:
>
>
> On Tue, 2018-04-24 at 14:20 -0700, Rodrigo Vivi wrote:
> > On Mon, Apr 23, 2018 at 05:42:40PM -0700, Souza, Jose wrote:
> > > On Fri, 2018-04-20 at 15:57 -0700, Rodrigo Vivi wrote:
> > > > On Fri, Apr 20, 2018 at 03:27:56PM -0700
On Thu, Apr 05, 2018 at 11:30:18AM +0530, Mahesh Kumar wrote:
> ICL has two slices of DBuf, each slice of size 1024 blocks.
> We should not always enable slice-2. It should be enabled only if
> display total required BW is > 12GBps OR more than 1 pipes are enabled.
>
> Changes since V1:
> - typec
On Fri, 2018-04-20 at 14:16 -0700, Rodrigo Vivi wrote:
> On Wed, Apr 18, 2018 at 03:43:08PM -0700, José Roberto de Souza
> wrote:
> > Sink can be configured to calculate the CRC over the static frame
> > and
> > compare with the CRC calculated and transmited in the VSC SDP by
> > source, if there i
On Thu, Apr 05, 2018 at 11:30:19AM +0530, Mahesh Kumar wrote:
> Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
> 11 bits. This patch make changes to use proper mask for ICL+ during
> hardware ddb value readout.
>
> Changes since V1:
> - Use _MASK & _SHIFT macro (James)
>
This was my bad, spec says that the name of this bit is
'Y-coordinate valid' but the values for it is:
0: Include Y-coordinate valid eDP1.4a
1: Do not include Y-coordinate valid eDP 1.4
So not setting it.
BSpec: 7713
Cc: Rodrigo Vivi
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto
Any write in any display register was causing HW to exit PSR,
masking it to allow more power savings. Writes to pipe related
registers will still cause HW to exit PSR.
This is already masked for PSR2.
It also do not break the Display WA #0884, writes to CURSURFLIVE
are still causing hardware to ex
This will be helpful to debug what hardware is actually tracking
and causing PSR to exit.
BSpec: 7721
v4:
- Using _MMIO_TRANS2() in PSR_EVENT
- Cleaning events before printing
Signed-off-by: José Roberto de Souza
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h |
IGT tests could be improved with sink status, knowing for sure that
hardware have activate or exit PSR.
v3:
Reading i915_edp_psr_status was causing PSR to exit but now with
'drm/i915/psr: Prevent PSR exit when a non-pipe related register is
written' it is fixed.
Reviewed-by: Dhinakaran Pandiyan
On Wed, Apr 25, 2018 at 02:23:32PM -0700, José Roberto de Souza wrote:
> This will be helpful to debug what hardware is actually tracking
> and causing PSR to exit.
>
> BSpec: 7721
>
> v4:
> - Using _MMIO_TRANS2() in PSR_EVENT
> - Cleaning events before printing
>
> Signed-off-by: José Roberto d
== Series Details ==
Series: Optimize use of DBuf slices (rev2)
URL : https://patchwork.freedesktop.org/series/41180/
State : failure
== Summary ==
Applying: drm/i915/icl: track dbuf slice-2 status
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M dr
On Wed, 2018-04-25 at 14:40 -0700, Rodrigo Vivi wrote:
> On Wed, Apr 25, 2018 at 02:23:32PM -0700, José Roberto de Souza
> wrote:
> > This will be helpful to debug what hardware is actually tracking
> > and causing PSR to exit.
> >
> > BSpec: 7721
> >
> > v4:
> > - Using _MMIO_TRANS2() in PSR_EVE
On Wed, Apr 25, 2018 at 02:47:35PM -0700, Souza, Jose wrote:
> On Wed, 2018-04-25 at 14:40 -0700, Rodrigo Vivi wrote:
> > On Wed, Apr 25, 2018 at 02:23:32PM -0700, José Roberto de Souza
> > wrote:
> > > This will be helpful to debug what hardware is actually tracking
> > > and causing PSR to exit.
On Wed, Apr 25, 2018 at 09:46:23PM -, Patchwork wrote:
> == Series Details ==
>
> Series: Optimize use of DBuf slices (rev2)
> URL : https://patchwork.freedesktop.org/series/41180/
> State : failure
>
> == Summary ==
>
> Applying: drm/i915/icl: track dbuf slice-2 status
> error: Failed to
This became dead code with commit 309bd8ed464f ("drm/i915: Reinstate
GMBUS and AUX interrupts on gen4/g4x").
Cc: Ville Syrjälä
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
drivers/gpu/drm/i915/intel_dp.c | 22 +++---
drivers/gpu/drm/i915/intel_d
Sink crc is calculated by the sink for static frames irrespective of
what the driver sets in TEST_SINK_START dpcd. Since PSR is the only use
case for sink crc, we don't really need the sink_crc_{start, stop} code.
The second problem with the current implementation is vblank waits.
Enabling vblank
With sink-crc now being relevant only for PSR static frames, move the
code to intel_psr.c and rename the function.
v2: Rebased.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/intel_dp.c | 36
dri
== Series Details ==
Series: series starting with [1/4] drm/i915/psr: Prevent PSR exit when a
non-pipe related register is written
URL : https://patchwork.freedesktop.org/series/42304/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4099 -> Patchwork_8802 =
== Summary - SUCC
== Series Details ==
Series: drm/i915: remove check for aux irq
URL : https://patchwork.freedesktop.org/series/42305/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: remove check for aux irq
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3659:16: warning: expression
== Series Details ==
Series: drm/i915: remove check for aux irq
URL : https://patchwork.freedesktop.org/series/42305/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4099 -> Patchwork_8803 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.
== Series Details ==
Series: series starting with [1/3] drm/i915/dp: Check if the sink crc we read
is 6 bytes. (rev3)
URL : https://patchwork.freedesktop.org/series/42154/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
89124b64449f drm/i915/dp: Check if the sink crc we read is
== Series Details ==
Series: series starting with [1/3] drm/i915/dp: Check if the sink crc we read
is 6 bytes. (rev3)
URL : https://patchwork.freedesktop.org/series/42154/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4099 -> Patchwork_8804 =
== Summary - FAILURE ==
Ser
Hi Anusha,
Can I ask if this is on anyone's radar as I'm concerned this patch will
stall otherwise?
I see that the significance of testing with the 4.14 kernel enabled the
firmware to be included in the latest Chrome OS kernel (
https://groups.google.com/a/chromium.org/forum/#!topic/chromium-os-r
On Wed, Apr 25, 2018 at 02:57:57PM -0700, Dhinakaran Pandiyan wrote:
> Sink crc is calculated by the sink for static frames irrespective of
> what the driver sets in TEST_SINK_START dpcd. Since PSR is the only use
> case for sink crc, we don't really need the sink_crc_{start, stop} code.
>
> The s
On Wed, Apr 25, 2018 at 02:58:34PM -0700, Dhinakaran Pandiyan wrote:
> With sink-crc now being relevant only for PSR static frames, move the
> code to intel_psr.c and rename the function.
>
> v2: Rebased.
> Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i
On Wed, Apr 25, 2018 at 10:48:10PM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915/dp: Check if the sink crc we read
> is 6 bytes. (rev3)
> URL : https://patchwork.freedesktop.org/series/42154/
> State : failure
>
> == Summary ==
>
> = CI Bug Log
On Wed, Apr 25, 2018 at 02:55:24PM -0700, Lucas De Marchi wrote:
> This became dead code with commit 309bd8ed464f ("drm/i915: Reinstate
> GMBUS and AUX interrupts on gen4/g4x").
>
> Cc: Ville Syrjälä
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915
Em Qua, 2018-04-25 às 11:01 -0700, Rodrigo Vivi escreveu:
> On Tue, Apr 24, 2018 at 05:34:14PM -0700, Paulo Zanoni wrote:
> > Em Qui, 2018-04-05 às 17:20 -0700, Rodrigo Vivi escreveu:
> > > On Thu, Feb 22, 2018 at 12:55:10AM -0300, Paulo Zanoni wrote:
> > > > From: Manasi Navare
> > > >
> > > > T
On Thu, Apr 05, 2018 at 02:47:56PM +0530, Mahesh Kumar wrote:
> Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
> 11 bits. This patch make changes to use proper mask for ICL+ during
> hardware ddb value readout.
>
> Changes since V1:
> - Use _MASK & _SHIFT macro (James)
> C
On Thu, Apr 05, 2018 at 02:47:55PM +0530, Mahesh Kumar wrote:
> ICL has two slices of DBuf, each slice of size 1024 blocks.
> We should not always enable slice-2. It should be enabled only if
> display total required BW is > 12GBps OR more than 1 pipes are enabled.
>
> Changes since V1:
> - typeca
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