== Series Details ==
Series: drm/i915/execlists: Reset ring registers on rebinding contexts
URL : https://patchwork.freedesktop.org/series/40763/
State : failure
== Summary ==
Possible new issues:
Test kms_flip:
Subgroup flip-vs-blocking-wf-vblank:
pass -> F
On Wed, Mar 28, 2018 at 09:47:40AM +0300, Oleksandr Andrushchenko wrote:
> From: Noralf Trønnes
>
> Use srcu to protect drm_device.unplugged in a race free manner.
> Drivers can use drm_dev_enter()/drm_dev_exit() to protect and mark
> sections preventing access to device resources that are not av
From: Noralf Trønnes
Use srcu to protect drm_device.unplugged in a race free manner.
Drivers can use drm_dev_enter()/drm_dev_exit() to protect and mark
sections preventing access to device resources that are not available
after the device is gone.
Suggested-by: Daniel Vetter
Signed-off-by: Nora
== Series Details ==
Series: drm: Use srcu to protect drm_device.unplugged
URL : https://patchwork.freedesktop.org/series/40793/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm: Use srcu to protect drm_device.unplugged
+drivers/gpu/drm/drm_drv.c:336:6: warning: context im
Chris Wilson writes:
> Tvrtko uncovered a fun issue with recovering from a wedge device. In his
> tests, he wedged the driver by injecting an unrecoverable hang whilst a
> batch was spinning. As we reset the gpu in the middle of the spinner,
> when resumed it would continue on from the next instr
Quoting Francisco Jerez (2018-03-28 07:38:45)
> This allows cpufreq governors to realize when the system becomes
> non-CPU-bound due to GPU rendering activity, which will cause the
> intel_pstate LP controller to behave more conservatively: CPU energy
> usage will be reduced when there isn't a good
== Series Details ==
Series: drm: Use srcu to protect drm_device.unplugged
URL : https://patchwork.freedesktop.org/series/40793/
State : success
== Summary ==
Series 40793v1 drm: Use srcu to protect drm_device.unplugged
https://patchwork.freedesktop.org/api/1.0/series/40793/revisions/1/mbox/
== Series Details ==
Series: drm/i915/guc: Support for Guc responses and requests (rev5)
URL : https://patchwork.freedesktop.org/series/28393/
State : failure
== Summary ==
Possible new issues:
Test debugfs_test:
Subgroup read_all_entries_display_off:
pass -
On Thu, 2018-03-22 at 15:10 -0700, Radhakrishna Sripada wrote:
> From: Anusha Srivatsa
>
> Cleanup the testcases by moving the platform checks to a single
> function.
>
> The earlier version of the path is posted here [1]
>
> v2: Make use of the property enums to get the supported rotations
> v
Op 22-03-18 om 23:10 schreef Radhakrishna Sripada:
> From: Anusha Srivatsa
>
> Cleanup the testcases by moving the platform checks to a single function.
>
> The earlier version of the path is posted here [1]
>
> v2: Make use of the property enums to get the supported rotations
> v3: Move hardcodin
Hi Eric,
Thanks for your input.
On Wed, Mar 21, 2018 at 10:10:00AM -0700, Eric Anholt wrote:
> Maxime Ripard writes:
>
> > [ Unknown signature status ]
> > Hi,
> >
> > On Mon, Mar 05, 2018 at 03:21:26PM +0100, Maxime Ripard wrote:
> >> Here is an RFC at starting to test the plane formats using
Quoting Mika Kuoppala (2018-03-28 08:58:38)
> Chris Wilson writes:
>
> > Tvrtko uncovered a fun issue with recovering from a wedge device. In his
> > tests, he wedged the driver by injecting an unrecoverable hang whilst a
> > batch was spinning. As we reset the gpu in the middle of the spinner,
>
On 2018.03.27 17:39:53 +0300, Joonas Lahtinen wrote:
> Quoting Joonas Lahtinen (2018-03-27 16:42:28)
> > Quoting Zhenyu Wang (2018-03-27 11:39:42)
> > >
> > > Hi, Joonas
> > >
> > > Here's this week's gvt-next-fixes queued for 4.17. One notable change
> > > is to revert previous workaround for gv
Quoting Chris Wilson (2018-03-27 10:23:26)
> Quoting Tvrtko Ursulin (2018-03-27 09:51:20)
> >
> > On 26/03/2018 12:50, Chris Wilson wrote:
> > > +static enum hrtimer_restart preempt_timeout(struct hrtimer *hrtimer)
> > > +{
> > > + struct intel_engine_execlists *execlists =
> > > +
== Series Details ==
Series: series starting with [1/2] drm/dp: Move DPCD_REV_XX to drm_dp_helper
URL : https://patchwork.freedesktop.org/series/40768/
State : success
== Summary ==
Known issues:
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
dmesg-warn ->
On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:
We should not leave GuC submission enabled after sanitize,
as we are going to reset all GuC/HuC hardware.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_u
On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:
In commit 9192d4fb811e ("drm/i915/guc: Extract doorbell creation
from client allocation") we introduced asymmetry in doorbell cleanup
to avoid warnings due to failed communication with already reset GuC.
As we improved our reset/unload paths, we can
From: Mahesh Kumar
For YUV 420 Planar formats like NV12,
buffer allocation is done for Y and UV surfaces separately.
For NV12 plane formats, the UV buffer
allocation must be programmed in the Plane Buffer Config register
and the Y buffer allocation must be programmed in the
Plane NV12 Buffer Conf
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.
v2: Change
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
v2: Added reviewed by tag from Shashank Sharma
v3: Added reviewed by from Juha-Pekka Heikkila
v4: Rebas
From: Mahesh Kumar
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable late
From: Mahesh Kumar
This patch passes skl_wm_level structure itself to watermark
computation function skl_compute_plane_wm function (instead
of its internal parameters). It reduces number of arguments
required to be passed.
v2: Addressed review comments by Shashank Sharma
v3: Adding reviewed by
As per WA 1106, to avoid corruption issues
NV12 plane height needs to be multiplier of 4
We avoid trunction in this patch so that
the buffer we send (which is multiplier of 4)
directs goes into the kernel.
Credits-to: Maarten Lankhorst
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/inte
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
v2: Addressed review comments from Shashank Sharma
Alignment issue fixed in i915_reg.h
v3: Adding Reviewed By from Shashank Sharma
v4: Rebased the patch. As part of rebasing, re-using
the color series defines which are a
From: Mahesh Kumar
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
v2: Addressed review comments by Maarten
v3: Rebased and addressed r
This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Previous revision history:
The first version of patches were reviewed when floated b
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offs
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
v2: Addressed review comments from Shashank Sharma.
v3: Addressed review comments from Shashank Sharma
Changed plane_num to plane_id in skl_compute_plane_wm_par
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane
From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max
Display WA 827 applies to GEN9 (excluede GLK) and CNL.
Switching the plane format from NV12 to RGB and leaving system idle
results in display underrun and corruption.
WA: Set the bit 15 & bit 19 to 1b in the CLKGATE_DIS_PSL
register for the pipe in which NV12 plane is enabled.
v2: Addressed review
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: M
Patch adds checks to primary plane related
to scaling, clipping, rotation and fb formats.
These checks currently, were being done only for sprites.
These are required for primary plane as well.
Credits-to: Maarten Lankhorst
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
v2: Added reviewed by tag from Mika Kahola
v3: Added reviewed by from Juha-Pekka Heikkila
v4: Rebased the series
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Mika Kahola
Signed-off-by: Mahesh Ku
On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:
Today uc_fini_hw is subset of uc_sanitize, but remaining
code in sanitize function is also desired for uc_fini_hw.
Instead of duplicating the code, just call uc_sanitize,
but leave as separate function to maintain symmetry with
uc_init_hw.
Signed-o
On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:
Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure")
we believed that we correctly handle all errors encountered during
GuC initialization, including special one that indicates request to
run driver with disabled GPU submission (-E
== Series Details ==
Series: series starting with [v5,1/2] drm/i915/cnl: Implement
WaProgramMgsrForCorrectSliceSpecificMmioReads (rev5)
URL : https://patchwork.freedesktop.org/series/40503/
State : success
== Summary ==
Known issues:
Test kms_cursor_crc:
Subgroup cursor-128x128-
Quoting Patchwork (2018-03-28 06:21:58)
> == Series Details ==
>
> Series: series starting with [v5,1/8] drm/i915: Correctly handle error path
> in i915_gem_init_hw
> URL : https://patchwork.freedesktop.org/series/40759/
> State : failure
>
> == Summary ==
>
> Possible new issues:
>
> T
On 27/03/2018 23:14, Yunwei Zhang wrote:
L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MM
On 28/03/2018 10:39, Tvrtko Ursulin wrote:
On 27/03/2018 23:14, Yunwei Zhang wrote:
L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
pro
== Series Details ==
Series: Add NV12 support (rev5)
URL : https://patchwork.freedesktop.org/series/39670/
State : success
== Summary ==
Series 39670v5 Add NV12 support
https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/5/mbox/
Known issues:
Test gem_exec_suspend:
Adding a i915_fifo_underrun_reset debugfs file will make it possible
for IGT tests to clear FIFO underrun fallout at the start of each
subtest, and make re-enable FBC so tests always have maximum exposure
to features used by IGT. FIFO underruns and FBC bugs will no longer
hide when an earlier subte
== Series Details ==
Series: series starting with [1/3] drm/i915/execlists: Reset ring registers on
rebinding contexts (rev2)
URL : https://patchwork.freedesktop.org/series/40764/
State : failure
== Summary ==
Possible new issues:
Test kms_flip:
Subgroup flip-vs-blocking-wf-vbla
On Wed, 28 Mar 2018, Maarten Lankhorst
wrote:
> Adding a i915_fifo_underrun_reset debugfs file will make it possible
> for IGT tests to clear FIFO underrun fallout at the start of each
> subtest, and make re-enable FBC so tests always have maximum exposure
> to features used by IGT. FIFO underrun
On 27/03/2018 22:01, Chris Wilson wrote:
Tvrtko uncovered a fun issue with recovering from a wedge device. In his
tests, he wedged the driver by injecting an unrecoverable hang whilst a
batch was spinning. As we reset the gpu in the middle of the spinner,
when resumed it would continue on from t
On Tue, Mar 27, 2018 at 06:33:11PM +, Pandiyan, Dhinakaran wrote:
> On Tue, 2018-03-27 at 13:24 +0300, Ville Syrjälä wrote:
> > On Mon, Mar 26, 2018 at 06:16:22PM -0700, Dhinakaran Pandiyan wrote:
> > > Interrupts other than the one for AUX errors are required only for debug,
> > > so unmask th
On Wed, Mar 28, 2018 at 10:29:15AM +0200, Maarten Lankhorst wrote:
> Op 22-03-18 om 23:10 schreef Radhakrishna Sripada:
> > From: Anusha Srivatsa
> >
> > Cleanup the testcases by moving the platform checks to a single function.
> >
> > The earlier version of the path is posted here [1]
> >
> > v2:
== Series Details ==
Series: drm/i915: Add debugfs file to clear FIFO underruns.
URL : https://patchwork.freedesktop.org/series/40800/
State : failure
== Summary ==
Series 40800v1 drm/i915: Add debugfs file to clear FIFO underruns.
https://patchwork.freedesktop.org/api/1.0/series/40800/revisio
Quoting Jackie Li (2018-03-23 01:59:22)
> GuC Address Space and WOPCM Layout diagrams won't be generated correctly by
> sphinx build if not using proper reST syntax.
>
> This patch uses reST literal blocks to make sure GuC Address Space and
> WOPCM Layout diagrams to be generated correctly, and it
Chris Wilson writes:
> Tvrtko uncovered a fun issue with recovering from a wedge device. In his
> tests, he wedged the driver by injecting an unrecoverable hang whilst a
> batch was spinning. As we reset the gpu in the middle of the spinner,
> when resumed it would continue on from the next instr
On 09/01/18 23:28, Paulo Zanoni wrote:
The only thing that differs here is that the crystal clock freq now
has four possible values.
This patch gets rid of the "Unknown gen, unable to compute..." message
at boot for gen11.
Reviewed-by: Lionel Landwerlin
Still
Reviewed-by: Lionel Landwerlin
On 28/03/18 00:39, Paulo Zanoni wrote:
Em Ter, 2018-03-27 às 15:42 -0700, Paulo Zanoni escreveu:
Em Sex, 2018-03-23 às 16:28 +, Lionel Landwerlin escreveu:
Hi Mika,
Even after this series, we're still missing support for reading
the
timestamp frequency (read_timestamp_frequency in
intel_de
Quoting Joonas Lahtinen (2018-03-28 14:27:19)
> Quoting Jackie Li (2018-03-23 01:59:22)
> > GuC Address Space and WOPCM Layout diagrams won't be generated correctly by
> > sphinx build if not using proper reST syntax.
> >
> > This patch uses reST literal blocks to make sure GuC Address Space and
>
Before adding a new feature to execlists submission, we should endeavour
to cover the baseline behaviour with selftests. So start the ball
rolling.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
CC: Michel Thierry
Cc: Jeff McGee
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i91
Quoting Michał Winiarski (2018-03-23 14:34:04)
> We're seeing "RPM wakelock ref not held during HW access" warning
> otherwise. And since IRQ are synced for runtime suspend, we can use the
> variant without wakeref assert.
>
> Reported-by: Marta Löfstedt
> Bugzilla: https://bugs.freedesktop.org/s
== Series Details ==
Series: drm/i915/selftests: Add basic sanitychecks for execlists
URL : https://patchwork.freedesktop.org/series/40805/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
90e2fd06c407 drm/i915/selftests: Add basic sanitychecks for execlists
-:43: WARNING:FILE_PAT
== Series Details ==
Series: drm: Use srcu to protect drm_device.unplugged
URL : https://patchwork.freedesktop.org/series/40793/
State : success
== Summary ==
Known issues:
Test kms_flip:
Subgroup 2x-plain-flip-ts-check-interruptible:
fail -> PASS (sha
== Series Details ==
Series: drm/i915/selftests: Add basic sanitychecks for execlists
URL : https://patchwork.freedesktop.org/series/40805/
State : success
== Summary ==
Series 40805v1 drm/i915/selftests: Add basic sanitychecks for execlists
https://patchwork.freedesktop.org/api/1.0/series/408
Chris Wilson writes:
> Now that we reload both RING_HEAD and RING_TAIL when rebinding the
> context, we do not need to scrub those registers immediately on resume.
>
> v2: Handle the perma-pinned contexts.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Mika Kuoppala
> ---
> driver
Quoting Daniele Ceraolo Spurio (2018-03-23 19:17:49)
>
>
> On 23/03/18 05:34, Michał Winiarski wrote:
> > We're seeing "RPM wakelock ref not held during HW access" warning
> > otherwise. And since IRQ are synced for runtime suspend, we can use the
> > variant without wakeref assert.
> >
> > Repo
On Wed, Mar 28, 2018 at 10:38:35AM +0300, Oleksandr Andrushchenko wrote:
> From: Noralf Trønnes
>
> Use srcu to protect drm_device.unplugged in a race free manner.
> Drivers can use drm_dev_enter()/drm_dev_exit() to protect and mark
> sections preventing access to device resources that are not av
== Series Details ==
Series: Add NV12 support (rev5)
URL : https://patchwork.freedesktop.org/series/39670/
State : success
== Summary ==
Known issues:
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass -> FAIL (shard-hsw) fdo#102887
On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i91
On 3/27/2018 4:13 PM, Chris Wilson wrote:
Quoting Zhang, Yunwei (2018-03-27 23:49:27)
On 3/27/2018 3:27 PM, Chris Wilson wrote:
Quoting Yunwei Zhang (2018-03-27 23:14:16)
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers,
Quoting Zhang, Yunwei (2018-03-28 16:54:26)
>
>
> On 3/27/2018 4:13 PM, Chris Wilson wrote:
> > Quoting Zhang, Yunwei (2018-03-27 23:49:27)
> >>
> >> On 3/27/2018 3:27 PM, Chris Wilson wrote:
> >>> Quoting Yunwei Zhang (2018-03-27 23:14:16)
> WaProgramMgsrForCorrectSliceSpecificMmioReads dic
On 3/27/2018 3:49 PM, Michel Thierry wrote:
On 3/27/2018 2:41 PM, Michal Wajdeczko wrote:
When running on platform with CTB based GuC communication enabled,
GuC to Host event data will be delivered as CT request message.
However, content of the data[1] of this CT message follows format
of the
On 2018-03-28 01:27, Chris Wilson wrote:
Quoting Tomasz Lis (2018-03-27 16:17:59)
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result from
Context Status Buffer.
Preemption in previous gens required a s
On 3/28/2018 9:03 AM, Chris Wilson wrote:
Quoting Zhang, Yunwei (2018-03-28 16:54:26)
On 3/27/2018 4:13 PM, Chris Wilson wrote:
Quoting Zhang, Yunwei (2018-03-27 23:49:27)
On 3/27/2018 3:27 PM, Chris Wilson wrote:
Quoting Yunwei Zhang (2018-03-27 23:14:16)
WaProgramMgsrForCorrectSliceSpeci
Op 28-03-18 om 12:21 schreef Jani Nikula:
> On Wed, 28 Mar 2018, Maarten Lankhorst
> wrote:
>> Adding a i915_fifo_underrun_reset debugfs file will make it possible
>> for IGT tests to clear FIFO underrun fallout at the start of each
>> subtest, and make re-enable FBC so tests always have maximum
On Fri, Mar 23, 2018 at 05:28:03PM +0100, Noralf Trønnes wrote:
>
> Den 23.03.2018 16.35, skrev Ville Syrjala:
> > From: Ville Syrjälä
> >
> > mipi_dbi_enable_flush() wants to call the fb->dirty() hook from the
> > bowels of the .atomic_enable() hook. That prevents us from taking the
> > plane mu
On 27/03/2018 22:01, Chris Wilson wrote:
Tvrtko uncovered a fun issue with recovering from a wedge device. In his
tests, he wedged the driver by injecting an unrecoverable hang whilst a
batch was spinning. As we reset the gpu in the middle of the spinner,
when resumed it would continue on from t
Quoting Tvrtko Ursulin (2018-03-28 17:26:37)
>
> On 27/03/2018 22:01, Chris Wilson wrote:
> > Tvrtko uncovered a fun issue with recovering from a wedge device. In his
> > tests, he wedged the driver by injecting an unrecoverable hang whilst a
> > batch was spinning. As we reset the gpu in the midd
On Wed, Mar 28, 2018 at 04:51:55PM +0300, Joonas Lahtinen wrote:
> Quoting Daniele Ceraolo Spurio (2018-03-23 19:17:49)
> >
> >
> > On 23/03/18 05:34, Michał Winiarski wrote:
> > > We're seeing "RPM wakelock ref not held during HW access" warning
> > > otherwise. And since IRQ are synced for runt
The rework looks good to me.
Thanks Mika for testing this.
>-Original Message-
>From: Kahola, Mika
>Sent: Wednesday, March 28, 2018 1:26 AM
>To: Sripada, Radhakrishna ; igt-
>d...@lists.freedesktop.org
>Cc: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
>; Ville Syrjälä ;
>Vetter,
>Da
On Wed, 2018-03-28 at 13:28 +0300, Ville Syrjälä wrote:
> On Tue, Mar 27, 2018 at 06:33:11PM +, Pandiyan, Dhinakaran wrote:
> > On Tue, 2018-03-27 at 13:24 +0300, Ville Syrjälä wrote:
> > > On Mon, Mar 26, 2018 at 06:16:22PM -0700, Dhinakaran Pandiyan wrote:
> > > > Interrupts other than the
From: Tvrtko Ursulin
Some messages are using %d and some %x which creates confusion while
reading the traces.
I also added:
1. Fence context/seqno to elsp traces - so it is easier to correlate
events.
2. New GEM_TRACE logging to port and request cancellation sites.
Signed-off-by: Tvrtko
Quoting Tvrtko Ursulin (2018-03-28 18:39:59)
> From: Tvrtko Ursulin
>
> Some messages are using %d and some %x which creates confusion while
> reading the traces.
>
> I also added:
>
> 1. Fence context/seqno to elsp traces - so it is easier to correlate
> events.
>
> 2. New GEM_TRACE log
As intel_wait_for_register_fw() may use, and if successful only use, a
busy-wait loop, the might_sleep() warning is a little over-zealous.
Restrict it to a might_sleep_if() a slow timeout is specified (and so
the caller authorises use of a usleep).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm
Instead of synchronously cancelling the timer and re-enabling it inside
the reset callbacks, keep the timer enabled and let it die on its next
wakeup if no longer required. This allows
intel_engine_reset_breadcrumbs() to be used from an atomic
(timer/softirq) context such as required for resetting
Instead of synchronously cancelling the timer and re-enabling it inside
the reset callbacks, keep the timer enabled and let it die on its next
wakeup if no longer required. This allows
intel_engine_reset_breadcrumbs() to be used from an atomic
(timer/softirq) context such as required for resetting
== Series Details ==
Series: drm/i915/execlists: Consistent seqno reporting in GEM_TRACE
URL : https://patchwork.freedesktop.org/series/40821/
State : success
== Summary ==
Series 40821v1 drm/i915/execlists: Consistent seqno reporting in GEM_TRACE
https://patchwork.freedesktop.org/api/1.0/seri
From: Tvrtko Ursulin
intel-gpu-top is a dangerous tool which can hang machines due unsafe mmio
register access. This patch rewrites it to use only PMU.
Only overall command streamer busyness and GPU global data such as power
and frequencies are included in this new version.
For access to more G
Quoting Tvrtko Ursulin (2018-03-28 19:29:48)
> From: Tvrtko Ursulin
>
> intel-gpu-top is a dangerous tool which can hang machines due unsafe mmio
> register access. This patch rewrites it to use only PMU.
>
> Only overall command streamer busyness and GPU global data such as power
> and frequenc
On 28/03/18 19:29, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
intel-gpu-top is a dangerous tool which can hang machines due unsafe mmio
register access. This patch rewrites it to use only PMU.
Only overall command streamer busyness and GPU global data such as power
and frequencies are included
On Wed, 2018-03-28 at 18:53 +0100, Chris Wilson wrote:
> As intel_wait_for_register_fw() may use, and if successful only use, a
> busy-wait loop, the might_sleep() warning is a little over-zealous.
> Restrict it to a might_sleep_if() a slow timeout is specified (and so
> the caller authorises use
Hi Chris,
Chris Wilson writes:
> Quoting Francisco Jerez (2018-03-28 07:38:45)
>> This allows cpufreq governors to realize when the system becomes
>> non-CPU-bound due to GPU rendering activity, which will cause the
>> intel_pstate LP controller to behave more conservatively: CPU energy
>> usage
== Series Details ==
Series: drm/i915: Only warn for might_sleep() before a slow wait_for_register
URL : https://patchwork.freedesktop.org/series/40823/
State : success
== Summary ==
Series 40823v1 drm/i915: Only warn for might_sleep() before a slow
wait_for_register
https://patchwork.freedes
Quoting Pandiyan, Dhinakaran (2018-03-28 20:01:40)
>
> On Wed, 2018-03-28 at 18:53 +0100, Chris Wilson wrote:
> > As intel_wait_for_register_fw() may use, and if successful only use, a
> > busy-wait loop, the might_sleep() warning is a little over-zealous.
> > Restrict it to a might_sleep_if() a s
Hi Dave,
Here's a lonely fix for -next, please pull at your convenience.
drm-misc-next-fixes-2018-03-28:
UABI:
- Mask mode type garbage from userspace (Ville)
Cc: Ville Syrjälä
Cheers, Sean
The following changes since commit b4eec0fa537165efc3265cdbb4bac06e6bdaf596:
Merge tag 'drm-intel-
Quoting Francisco Jerez (2018-03-28 19:55:12)
> Hi Chris,
>
[snip]
> That said, it wouldn't hurt to call each of them once per sequence of
> overlapping requests. Do you want me to call them from
> execlists_set/clear_active() themselves when bit == EXECLISTS_ACTIVE_USER,
> or at each callsite of
== Series Details ==
Series: drm/i915/breadcrumbs: Keep the fake irq armed across reset (rev2)
URL : https://patchwork.freedesktop.org/series/40825/
State : success
== Summary ==
Series 40825v2 drm/i915/breadcrumbs: Keep the fake irq armed across reset
https://patchwork.freedesktop.org/api/1.0
Quoting Patchwork (2018-03-28 08:07:45)
> == Series Details ==
>
> Series: drm/i915/execlists: Reset ring registers on rebinding contexts
> URL : https://patchwork.freedesktop.org/series/40763/
> State : failure
>
> == Summary ==
>
> Possible new issues:
>
> Test kms_flip:
> Subg
On Wed, 2018-03-28 at 20:13 +0100, Chris Wilson wrote:
> Quoting Pandiyan, Dhinakaran (2018-03-28 20:01:40)
> >
> > On Wed, 2018-03-28 at 18:53 +0100, Chris Wilson wrote:
> > > As intel_wait_for_register_fw() may use, and if successful only use, a
> > > busy-wait loop, the might_sleep() warning
Quoting Patchwork (2018-03-28 09:22:48)
> == Series Details ==
>
> Series: drm/i915/guc: Support for Guc responses and requests (rev5)
> URL : https://patchwork.freedesktop.org/series/28393/
> State : failure
>
> == Summary ==
>
> Possible new issues:
>
> Test debugfs_test:
> Sub
== Series Details ==
Series: drm/i915/selftests: Add basic sanitychecks for execlists
URL : https://patchwork.freedesktop.org/series/40805/
State : success
== Summary ==
Possible new issues:
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-spr-indfb-onoff:
From: Michal Wajdeczko
Stolen from...
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c96360398072..53037b5eff22 100644
---
Probably lost while rebasing commit eacd8391f977 ("drm/i915/guc: Keep GuC
interrupts enabled when using GuC").
Not really needed since i915_gem_init_hw is called before uc_resume, but
it brings symmetry to uc_suspend.
Signed-off-by: Michel Thierry
Cc: Michał Winiarski
Reviewed-by: Michał Winiar
1 - 100 of 169 matches
Mail list logo
