Re: [Intel-gfx] [PATCH] drm/i915: Tell vga_switcheroo whether runtime PM is used

2018-03-25 Thread Lukas Wunner
On Mon, Mar 05, 2018 at 05:37:11PM +0200, Imre Deak wrote: > On Mon, Feb 26, 2018 at 04:57:11PM +0100, Lukas Wunner wrote: > > On Mon, Feb 26, 2018 at 04:41:09PM +0200, Imre Deak wrote: > > > On Sun, Feb 25, 2018 at 12:42:30AM +0100, Lukas Wunner wrote: > > > > DRM drivers need to tell vga_switcher

[Intel-gfx] [PATCH v15 05/18] drm/i915/skl+: NV12 related changes for WM

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. v2: Addressed review comments from Shashank Sharma. v3: Addressed review comments from Shashank Sharma Changed plane_num to plane_id in skl_compute_plane_wm_par

[Intel-gfx] [PATCH v15 01/18] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1: - also change name of skl

[Intel-gfx] [PATCH v15 03/18] drm/i915/skl+: add NV12 in skl_format_to_fourcc

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. v2: Added reviewed by tag from Mika Kahola v3: Added reviewed by from Juha-Pekka Heikkila Reviewed-by: Juha-Pekka Heikkila Reviewed-by: Mika Kahola Signed-off-by: Mahesh Kumar --- drivers/gpu/dr

[Intel-gfx] [PATCH v15 08/18] drm/i915/skl+: nv12 workaround disable WM level 1-7

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C states or do not enable late

[Intel-gfx] [PATCH v15 06/18] drm/i915/skl+: pass skl_wm_level struct to wm compute func

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar This patch passes skl_wm_level structure itself to watermark computation function skl_compute_plane_wm function (instead of its internal parameters). It reduces number of arguments required to be passed. v2: Addressed review comments by Shashank Sharma v3: Adding reviewed by

[Intel-gfx] [PATCH v15 00/18] Add NV12 support

2018-03-25 Thread Vidya Srinivas
MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786

[Intel-gfx] [PATCH v15 02/18] drm/i915/skl+: refactor WM calculation for NV12

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten v3: Rebased and addressed r

[Intel-gfx] [PATCH v15 04/18] drm/i915/skl+: support verification of DDB HW state for NV12

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in the Plane NV12 Buffer Conf

[Intel-gfx] [PATCH v15 09/18] drm/i915/skl: split skl_compute_ddb function

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. v2: Added reviewed by tag from Shashank Sharma v3: Added reviewed by from Juha-Pekka Heikkila Reviewed-

[Intel-gfx] [PATCH v15 10/18] drm/i915: Set scaler mode for NV12

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode, skylake scaler does either chroma-upsampling or chroma-upsampling and resolution scaling v2: Review comments from Ville addressed NV12 case to be checked first for setting the scaler v3: Rebased (me) v

[Intel-gfx] [PATCH v15 13/18] drm/i915: Add NV12 as supported format for primary plane

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing skl_primary_formats v5: Rebased (me) v6: M

[Intel-gfx] [PATCH v15 07/18] drm/i915/skl+: make sure higher latency level has higher wm value

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements. v2: Change

[Intel-gfx] [PATCH v15 17/18] drm/i915: Display WA 827

2018-03-25 Thread Vidya Srinivas
Display WA 827 applies to GEN9 (excluede GLK) and CNL. Switching the plane format from NV12 to RGB and leaving system idle results in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane is enabled. v2: Addressed review

[Intel-gfx] [PATCH v15 12/18] drm/i915: Upscale scaler max scale for NV12

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) v3: Rebased (me) v4: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v5: Addressed review comments from Ville and rebased - calculation of max

[Intel-gfx] [PATCH v15 15/18] drm/i915: Add NV12 support to intel_framebuffer_init

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in intel_framebuffer_init Removed offs

[Intel-gfx] [PATCH v15 11/18] drm/i915: Update format_is_yuv() to include NV12

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch adds NV12 to format_is_yuv() function for sprite planes. v2: -Use intel_ prefix for format_is_yuv (Ville) v3: Rebased (me) v4: Rebased and addressed review comments from Clinton A Taylor. "static function in intel_sprite.c is not available to the primary plane

[Intel-gfx] [PATCH v15 18/18] drm/i915: Add checks to primary plane

2018-03-25 Thread Vidya Srinivas
Patch adds checks to primary plane related to scaling, clipping, rotation and fb formats. These checks currently, were being done only for sprites. These are required for primary plane as well. Credits-to: Maarten Lankhorst Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH v15 14/18] drm/i915: Add NV12 as supported format for sprite plane

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats v4: Addressed review comments

[Intel-gfx] [PATCH v15 16/18] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-03-25 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. v2: Addressed review comments from Shashank Sharma Alignment issue fixed in i915_reg.h v3: Adding Reviewed By from Shashank Sharma v4: Rebased the patch. As part of rebasing, re-using the color series defines which are a

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add NV12 support (rev3)

2018-03-25 Thread Patchwork
== Series Details == Series: Add NV12 support (rev3) URL : https://patchwork.freedesktop.org/series/39670/ State : failure == Summary == Applying: drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Applying: drm/i915/skl+: refactor WM calculation for NV12 Applying: drm/i915/skl+: add

[Intel-gfx] [PATCH v16 00/18] Add NV12 support

2018-03-25 Thread Vidya Srinivas
This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches were reviewed when floated b

[Intel-gfx] [PATCH v16 02/18] drm/i915/skl+: refactor WM calculation for NV12

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten v3: Rebased and addressed r

[Intel-gfx] [PATCH v16 05/18] drm/i915/skl+: NV12 related changes for WM

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. v2: Addressed review comments from Shashank Sharma. v3: Addressed review comments from Shashank Sharma Changed plane_num to plane_id in skl_compute_plane_wm_par

[Intel-gfx] [PATCH v16 01/18] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1: - also change name of skl

[Intel-gfx] [PATCH v16 07/18] drm/i915/skl+: make sure higher latency level has higher wm value

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements. v2: Change

[Intel-gfx] [PATCH v16 03/18] drm/i915/skl+: add NV12 in skl_format_to_fourcc

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. v2: Added reviewed by tag from Mika Kahola v3: Added reviewed by from Juha-Pekka Heikkila v4: Rebased the series Reviewed-by: Juha-Pekka Heikkila Reviewed-by: Mika Kahola Signed-off-by: Mahesh Ku

[Intel-gfx] [PATCH v16 10/18] drm/i915: Set scaler mode for NV12

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode, skylake scaler does either chroma-upsampling or chroma-upsampling and resolution scaling v2: Review comments from Ville addressed NV12 case to be checked first for setting the scaler v3: Rebased (me) v

[Intel-gfx] [PATCH v16 06/18] drm/i915/skl+: pass skl_wm_level struct to wm compute func

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar This patch passes skl_wm_level structure itself to watermark computation function skl_compute_plane_wm function (instead of its internal parameters). It reduces number of arguments required to be passed. v2: Addressed review comments by Shashank Sharma v3: Adding reviewed by

[Intel-gfx] [PATCH v16 09/18] drm/i915/skl: split skl_compute_ddb function

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. v2: Added reviewed by tag from Shashank Sharma v3: Added reviewed by from Juha-Pekka Heikkila v4: Rebas

[Intel-gfx] [PATCH v16 04/18] drm/i915/skl+: support verification of DDB HW state for NV12

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in the Plane NV12 Buffer Conf

[Intel-gfx] [PATCH v16 08/18] drm/i915/skl+: nv12 workaround disable WM level 1-7

2018-03-25 Thread Vidya Srinivas
From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C states or do not enable late

[Intel-gfx] [PATCH v16 14/18] drm/i915: Add NV12 as supported format for sprite plane

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats v4: Addressed review comments

[Intel-gfx] [PATCH v16 11/18] drm/i915: Update format_is_yuv() to include NV12

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch adds NV12 to format_is_yuv() function for sprite planes. v2: -Use intel_ prefix for format_is_yuv (Ville) v3: Rebased (me) v4: Rebased and addressed review comments from Clinton A Taylor. "static function in intel_sprite.c is not available to the primary plane

[Intel-gfx] [PATCH v16 13/18] drm/i915: Add NV12 as supported format for primary plane

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing skl_primary_formats v5: Rebased (me) v6: M

[Intel-gfx] [PATCH v16 15/18] drm/i915: Add NV12 support to intel_framebuffer_init

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in intel_framebuffer_init Removed offs

[Intel-gfx] [PATCH v16 18/18] drm/i915: Add checks to primary plane

2018-03-25 Thread Vidya Srinivas
Patch adds checks to primary plane related to scaling, clipping, rotation and fb formats. These checks currently, were being done only for sprites. These are required for primary plane as well. Credits-to: Maarten Lankhorst Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH v16 12/18] drm/i915: Upscale scaler max scale for NV12

2018-03-25 Thread Vidya Srinivas
From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) v3: Rebased (me) v4: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v5: Addressed review comments from Ville and rebased - calculation of max

[Intel-gfx] [PATCH v16 17/18] drm/i915: Display WA 827

2018-03-25 Thread Vidya Srinivas
Display WA 827 applies to GEN9 (excluede GLK) and CNL. Switching the plane format from NV12 to RGB and leaving system idle results in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane is enabled. v2: Addressed review

[Intel-gfx] [PATCH v16 16/18] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-03-25 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. v2: Addressed review comments from Shashank Sharma Alignment issue fixed in i915_reg.h v3: Adding Reviewed By from Shashank Sharma v4: Rebased the patch. As part of rebasing, re-using the color series defines which are a

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add NV12 support (rev4)

2018-03-25 Thread Patchwork
== Series Details == Series: Add NV12 support (rev4) URL : https://patchwork.freedesktop.org/series/39670/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0503b1db737a drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values de530aafc1d7 drm/i915/skl+: refactor WM calculation

[Intel-gfx] ✓ Fi.CI.BAT: success for Add NV12 support (rev4)

2018-03-25 Thread Patchwork
== Series Details == Series: Add NV12 support (rev4) URL : https://patchwork.freedesktop.org/series/39670/ State : success == Summary == Series 39670v4 Add NV12 support https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/4/mbox/ Known issues: Test kms_pipe_crc_basic:

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add NV12 support (rev4)

2018-03-25 Thread Patchwork
== Series Details == Series: Add NV12 support (rev4) URL : https://patchwork.freedesktop.org/series/39670/ State : failure == Summary == Possible new issues: Test kms_plane_scaling: Subgroup pipe-a-scaler-with-pixel-format: pass -> FAIL (shard-apl)

Re: [Intel-gfx] [RFC] splitting dri-devel to drm core and drivers lists?

2018-03-25 Thread Joonas Lahtinen
Quoting Daniel Vetter (2018-03-23 18:39:04) > On Fri, Mar 23, 2018 at 06:22:46PM +0200, Jani Nikula wrote: > > There was some discussion on the dim-tools list about splitting the > > dri-devel list to drm core and drivers lists [1]. Moving the discussion > > to the list in question seems prudent. ;