On Wed, Mar 14, 2018 at 07:19:18PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 14, 2018 at 09:31:32AM -0700, Lucas De Marchi wrote:
> > Reorder fields so we save 8 bytes per instance: this removes a 4-bytes
> > hole after enum intel_dpll_id and a 4-bytes padding.
> >
> > Signed-off-by: Lucas De Marc
Hi,
There is a missing #include at amdgpu_amdkfd.h
I'll send a patch to Dave to apply to his drm-next tree to fix this.
Thanks for catching this,
Oded
On Thu, Mar 15, 2018 at 4:50 AM, kbuild test robot
wrote:
> tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
> head: 178cfb9373cc2bdfc
From: Mahesh Kumar
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
v2: Addressed review comments by Maarten
v3: Rebased and addressed r
This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Previous revision history:
The first version of patches were reviewed when floated b
From: Mahesh Kumar
This patch passes skl_wm_level structure itself to watermark
computation function skl_compute_plane_wm function (instead
of its internal parameters). It reduces number of arguments
required to be passed.
v2: Addressed review comments by Shashank Sharma
v3: Adding reviewed by
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.
v2: Change
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
v2: Addressed review comments from Shashank Sharma.
v3: Addressed review comments from Shashank Sharma
Changed plane_num to plane_id in skl_compute_plane_wm_par
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
v2: Added reviewed by tag from Mika Kahola
v3: Added reviewed by from Juha-Pekka Heikkila
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Mika Kahola
Signed-off-by: Mahesh Kumar
---
drivers/gpu/dr
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
v2: Added reviewed by tag from Shashank Sharma
v3: Added reviewed by from Juha-Pekka Heikkila
Reviewed-
From: Mahesh Kumar
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable late
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: M
From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane
From: Mahesh Kumar
For YUV 420 Planar formats like NV12,
buffer allocation is done for Y and UV surfaces separately.
For NV12 plane formats, the UV buffer
allocation must be programmed in the Plane Buffer Config register
and the Y buffer allocation must be programmed in the
Plane NV12 Buffer Conf
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offs
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
v2: Addressed review comments from Shashank Sharma
Alignment issue fixed in i915_reg.h
v3: Adding Reviewed By from Shashank Sharma
v4: Rebased the patch. As part of rebasing, re-using
the color series defines which are a
Display WA 827 applies to GEN9 (excluede GLK) and CNL.
Switching the plane format from NV12 to RGB and leaving system idle
results in display underrun and corruption.
WA: Set the bit 15 & bit 19 to 1b in the CLKGATE_DIS_PSL
register for the pipe in which NV12 plane is enabled.
v2: Addressed review
== Series Details ==
Series: Add NV12 support (rev2)
URL : https://patchwork.freedesktop.org/series/39670/
State : failure
== Summary ==
Series 39670v2 Add NV12 support
https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/2/mbox/
Possible new issues:
Test kms_pipe_crc_basic:
Quoting Patchwork (2018-03-15 01:23:05)
> == Series Details ==
>
> Series: series starting with [v4,1/4] drm/i915: store all mmio bases in
> intel_engines
> URL : https://patchwork.freedesktop.org/series/39981/
> State : success
>
> == Summary ==
>
> Known issues:
>
> Test gem_eio:
>
On Wed, Mar 14, 2018 at 10:19:21AM +, Chris Wilson wrote:
> Quoting Chris Wilson (2018-03-13 23:19:20)
> > From: Michal Wajdeczko
> >
> > We should not mix MMIO with MI_INSTR definitions.
> >
> > v2: sanitize comment, change include order (Chris)
> >
> > Suggested-by: Chris Wilson
> > Sign
On 3/14/2018 3:07 PM, Chris Wilson wrote:
Valleyview and Cherryview update the GPU frequency via the punit, which
is very expensive as we have to ensure the cores do not sleep during the
comms.
But the patch 5 applies this workaround to only VLV.
If we perform frequent RPS evaluations, the fr
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Mahesh Kumar
> Sent: Wednesday, March 14, 2018 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas ; Vivi, Rodrigo
>
> Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/cnl; A
We still have an odd race with wedging/unwedging as shown by igt/gem_eio
that defies expectations. Add some more trace_printks to try and
visualize the flow over the precipice.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 14 +++
> -Original Message-
> From: Chauhan, Madhav
> Sent: Thursday, March 15, 2018 2:55 PM
> To: 'Mahesh Kumar' ; intel-
> g...@lists.freedesktop.org
> Cc: De Marchi, Lucas ; Vivi, Rodrigo
>
> Subject: RE: [Intel-gfx] [PATCH v4 1/2] drm/i915/cnl; Add macro to get
> PORT_TX register
>
> > -
On Thu, Mar 15, 2018 at 01:01:14AM -0700, Lucas De Marchi wrote:
> On Wed, Mar 14, 2018 at 07:19:18PM +0200, Ville Syrjälä wrote:
> > On Wed, Mar 14, 2018 at 09:31:32AM -0700, Lucas De Marchi wrote:
> > > Reorder fields so we save 8 bytes per instance: this removes a 4-bytes
> > > hole after enum i
== Series Details ==
Series: drm/i915: Split GPU commands definitions into separate header
URL : https://patchwork.freedesktop.org/series/40018/
State : success
== Summary ==
Series 40018v1 drm/i915: Split GPU commands definitions into separate header
https://patchwork.freedesktop.org/api/1.0/
From: Tvrtko Ursulin
Request tracepoints have been renames so update the tool to be able to
find them.
v2: Only support new names.
Signed-off-by: Tvrtko Ursulin
---
overlay/gpu-perf.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/overlay/gpu-perf.c b/overlay/gpu-pe
Hi,
Here's more gvt-fixes for final 4.16. Sorry it's a little late,
as Zhi had two days off this week and more regression tests
have been done for this.
Thanks.
--
The following changes since commit 88d3dfb6a69042381161290c7ce19e1f53fc2a66:
drm/i915: Suspend submission tasklets around wedgin
== Series Details ==
Series: drm/i915: Trace GEM steps between submit and wedging
URL : https://patchwork.freedesktop.org/series/40020/
State : failure
== Summary ==
Series 40020v1 drm/i915: Trace GEM steps between submit and wedging
https://patchwork.freedesktop.org/api/1.0/series/40020/revis
Currently tests modify i915.enable_psr and then do a modeset cycle
to change PSR. We can write a value to i915_edp_psr_status to force
a certain value without a modeset.
To retain compatibility with older userspace, we also still allow
the override through the module parameter, and add some tracki
On Wed, Dec 20, 2017 at 2:14 AM, Byungchul Park wrote:
> On 12/19/2017 6:59 PM, Daniel Vetter wrote:
>>
>> On Mon, Dec 18, 2017 at 09:42:13AM -0800, Linus Torvalds wrote:
>>>
>>> On Sun, Dec 17, 2017 at 11:11 PM, Daniel Vetter wrote:
This didn't seem to have made it into -rc4. Anyt
Quoting Tvrtko Ursulin (2018-03-15 10:01:22)
> From: Tvrtko Ursulin
>
> Request tracepoints have been renames so update the tool to be able to
> find them.
>
> v2: Only support new names.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
-Chris
__
== Series Details ==
Series: drm/i915: Control PSR at runtime through debugfs only (rev3)
URL : https://patchwork.freedesktop.org/series/39955/
State : success
== Summary ==
Series 39955v3 drm/i915: Control PSR at runtime through debugfs only
https://patchwork.freedesktop.org/api/1.0/series/39
Quoting Patchwork (2018-03-15 09:55:20)
> == Series Details ==
>
> Series: drm/i915: Split GPU commands definitions into separate header
> URL : https://patchwork.freedesktop.org/series/40018/
> State : success
>
> == Summary ==
>
> Series 40018v1 drm/i915: Split GPU commands definitions into
Quoting Michal Wajdeczko (2018-03-14 14:45:39)
> We moved GuC log related data and code to separate files and
> definition but we didn't change functions syntax to follow
> object-verb pattern. Let's fix that before we continue with
> next round of code refactoring.
>
> v2: rebased
>
> Signed-off
== Series Details ==
Series: drm/i915: Split GPU commands definitions into separate header
URL : https://patchwork.freedesktop.org/series/40018/
State : success
== Summary ==
Known issues:
Test gem_eio:
Subgroup in-flight-contexts:
pass -> INCOMPLETE (shard-
On Wed, 14 Mar 2018, Lucas De Marchi wrote:
> Reorder fields so we save 8 bytes per instance: this removes a 4-bytes
> hole after enum intel_dpll_id and a 4-bytes padding.
Does GCC have anything like the Clang -Wpadded option to warn us about
alignment holes and padding? Certainly it would be too
== Series Details ==
Series: drm/i915: Trace GEM steps between submit and wedging
URL : https://patchwork.freedesktop.org/series/40020/
State : success
== Summary ==
Series 40020v1 drm/i915: Trace GEM steps between submit and wedging
https://patchwork.freedesktop.org/api/1.0/series/40020/revis
== Series Details ==
Series: Add NV12 support (rev2)
URL : https://patchwork.freedesktop.org/series/39670/
State : success
== Summary ==
Series 39670v2 Add NV12 support
https://patchwork.freedesktop.org/api/1.0/series/39670/revisions/2/mbox/
fi-bdw-5557u total:285 pass:264 dwarn:0 dfa
On 3/14/2018 3:07 PM, Chris Wilson wrote:
We now have two locks for sideband access. The general one covering
sideband access across all generation, sb_lock, and a specific one
covering sideband access via the punit on vlv/chv. After lifting the
sb_lock around the punit into the callers, the pc
== Series Details ==
Series: drm/i915: Control PSR at runtime through debugfs only (rev3)
URL : https://patchwork.freedesktop.org/series/39955/
State : success
== Summary ==
Known issues:
Test gem_eio:
Subgroup in-flight-contexts:
pass -> INCOMPLETE (shard-a
On Wed, 14 Mar 2018, Jackie Li wrote:
> GuC Address Space and WOPCM Layout diagrams won't be generated correctly by
> sphinx build if not using proper reST syntax.
>
> This patch uses reST literal blocks to make sure GuC Address Space and
> WOPCM Layout diagrams to be generated correctly.
>
> Sign
On Thu, Mar 15, 2018 at 11:31:57AM +0100, Daniel Vetter wrote:
> Is there any progress on getting cross-release enabled again?
Not yet, I'm still fighting the meltdown/spectre induced backlog.
We'll get to it eventually.
___
Intel-gfx mailing list
Intel
== Series Details ==
Series: drm/i915: Trace GEM steps between submit and wedging
URL : https://patchwork.freedesktop.org/series/40020/
State : success
== Summary ==
Known issues:
Test gem_eio:
Subgroup in-flight-contexts:
pass -> INCOMPLETE (shard-apl) fdo#
From: Tvrtko Ursulin
More than one test assumes that the spinner is running pretty much
immediately after we have create or submitted it.
In actuality there is a variable delay, especially on execlists platforms,
between submission and spin batch starting to run on the hardware.
To enable tests
Hello Chris Wilson,
The patch 2889caa92321: "drm/i915: Eliminate lots of iterations over
the execobjects array" from Jun 16, 2017, leads to the following
static checker warning:
drivers/gpu/drm/i915/i915_gem_execbuffer.c:2546
i915_gem_execbuffer_ioctl()
warn: calling '__copy_to_u
Quoting Tvrtko Ursulin (2018-03-15 12:56:17)
> From: Tvrtko Ursulin
>
> More than one test assumes that the spinner is running pretty much
> immediately after we have create or submitted it.
>
> In actuality there is a variable delay, especially on execlists platforms,
> between submission and s
We still have an odd race with wedging/unwedging as shown by igt/gem_eio
that defies expectations. Add some more trace_printks to try and
visualize the flow over the precipice.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 14 +++
If we fail to reset the GPU, we declare the machine wedged. However, the
GPU may well still be running in the background with an in-flight
request. So despite our efforts in cleaning up the request queue and
faking the breadcrumb in the HWSP, the GPU may eventually write the
in-flght seqno there br
Quoting Dan Carpenter (2018-03-15 13:10:30)
> Hello Chris Wilson,
>
> The patch 2889caa92321: "drm/i915: Eliminate lots of iterations over
> the execobjects array" from Jun 16, 2017, leads to the following
> static checker warning:
>
> drivers/gpu/drm/i915/i915_gem_execbuffer.c:2546
> i9
Chris Wilson writes:
> We still have an odd race with wedging/unwedging as shown by igt/gem_eio
> that defies expectations. Add some more trace_printks to try and
> visualize the flow over the precipice.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> ---
> drivers/
If we fail to reset the GPU, we declare the machine wedged. However, the
GPU may well still be running in the background with an in-flight
request. So despite our efforts in cleaning up the request queue and
faking the breadcrumb in the HWSP, the GPU may eventually write the
in-flght seqno there br
Op 13-03-18 om 23:02 schreef Joe Perches:
> drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary
> arguments that can be removed by creating separate functins.
>
> Create specific functions for these calls to reduce x86/64 defconfig
> size by ~20k.
>
> Modify the existing macros to
Quoting Chris Wilson (2018-03-15 13:14:50)
> We still have an odd race with wedging/unwedging as shown by igt/gem_eio
> that defies expectations. Add some more trace_printks to try and
> visualize the flow over the precipice.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursul
On Tue, Mar 13, 2018 at 03:02:15PM -0700, Joe Perches wrote:
> drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary
> arguments that can be removed by creating separate functins.
>
> Create specific functions for these calls to reduce x86/64 defconfig
> size by ~20k.
>
> Modify th
On Thu, Mar 15, 2018 at 01:17:23PM +, Chris Wilson wrote:
> Quoting Dan Carpenter (2018-03-15 13:10:30)
> > Hello Chris Wilson,
> >
> > The patch 2889caa92321: "drm/i915: Eliminate lots of iterations over
> > the execobjects array" from Jun 16, 2017, leads to the following
> > static checker w
Since Coffee Lake uses the Kaby Lake DMC it's a safe
bet that the debug registers are the same. I haven't
double-checked that the GLK DMC uses the same registers
as BXT, but it seems as good of a guess as any.
Signed-off-by: David Weinehall
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++--
1 fi
On 15/03/2018 13:14, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-03-15 12:56:17)
From: Tvrtko Ursulin
More than one test assumes that the spinner is running pretty much
immediately after we have create or submitted it.
In actuality there is a variable delay, especially on execlists plat
== Series Details ==
Series: series starting with [1/2] drm/i915: Trace GEM steps between submit and
wedging (rev2)
URL : https://patchwork.freedesktop.org/series/40029/
State : success
== Summary ==
Series 40029v2 series starting with [1/2] drm/i915: Trace GEM steps between
submit and wedgi
== Series Details ==
Series: drm/i915: Show dmc debug registers on CFL and GLK
URL : https://patchwork.freedesktop.org/series/40031/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
C
Quoting Tvrtko Ursulin (2018-03-15 13:36:26)
>
> On 15/03/2018 13:14, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-03-15 12:56:17)
> >> From: Tvrtko Ursulin
> >>
> >> More than one test assumes that the spinner is running pretty much
> >> immediately after we have create or submitted it.
Since Coffee Lake uses the Kaby Lake DMC it's a safe
bet that the debug registers are the same. I haven't
double-checked that the GLK DMC uses the same registers
as BXT, but it seems as good of a guess as any.
v2: Add parentheses to silence warning
Signed-off-by: David Weinehall
---
drivers/gpu
On Wed, Mar 14, 2018 at 05:11:02PM +0200, Jani Nikula wrote:
> Until now, the drm-intel commit access have been handed out ad hoc,
> without transparency, consistency, or fairness. With pressure to add
> more committers, this is no longer tenable, if it ever was. Document the
> requirements and exp
Op 15-03-18 om 14:30 schreef Ville Syrjälä:
> On Tue, Mar 13, 2018 at 03:02:15PM -0700, Joe Perches wrote:
>> drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary
>> arguments that can be removed by creating separate functins.
>>
>> Create specific functions for these calls to reduc
== Series Details ==
Series: Add NV12 support (rev2)
URL : https://patchwork.freedesktop.org/series/39670/
State : failure
== Summary ==
Possible new issues:
Test gem_exec_capture:
Subgroup capture-vebox:
pass -> FAIL (shard-apl)
Test kms_plane_scaling
== Series Details ==
Series: drm/i915: Show dmc debug registers on CFL and GLK (rev2)
URL : https://patchwork.freedesktop.org/series/40031/
State : success
== Summary ==
Series 40031v2 drm/i915: Show dmc debug registers on CFL and GLK
https://patchwork.freedesktop.org/api/1.0/series/40031/revi
On 15/03/2018 13:45, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-03-15 13:36:26)
On 15/03/2018 13:14, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-03-15 12:56:17)
From: Tvrtko Ursulin
More than one test assumes that the spinner is running pretty much
immediately after we have crea
Fixes false negatives on everything that doesn't happen to be at a
specific hard-coded sysfs path...
Signed-off-by: Ulrich Hecht
---
lib/igt_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 5bf5b2e..641157b 100644
--- a/lib/igt_pm.c
+++ b
Fixes failed assertion on non-i915 devices.
Signed-off-by: Ulrich Hecht
---
lib/igt_gt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 9cb07c2..825ea52 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -166,14 +166,15 @@ igt_hang_t igt_a
Fixes fails on low-memory devices.
Signed-off-by: Ulrich Hecht
---
tests/kms_addfb_basic.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index cf9ba37..d1da718 100644
--- a/tests/kms_addfb_basic.
Add is_i915_device() requirement to tests using Intel-specific APIs.
Signed-off-by: Ulrich Hecht
---
tests/kms_plane_lowres.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c
index d1e4b3c..8fc7654 100644
--- a/tests/kms_plane_lowres.c
+++ b
Quoting Tvrtko Ursulin (2018-03-15 14:37:59)
>
> On 15/03/2018 13:45, Chris Wilson wrote:
> > As we are making changes to igt_spin_t, one of the ideas was that we put
> > the obj[] array there (with the offsets and flags setup correctly) so
> > that we could just feed that in again later without h
Fixes false negatives on non-i915 platforms.
Signed-off-by: Ulrich Hecht
---
tests/kms_panel_fitting.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/kms_panel_fitting.c b/tests/kms_panel_fitting.c
index b3cee22..6d0be50 100644
--- a/tests/kms_panel_fitting.c
+++ b/tests/kms_panel_fit
Hi!
I have run the tests on a Renesas R-Car M3-W's DU device, and have found a
number of false negatives that mostly stem from use of Intel-specifics
without checking if that makes sense first. So here's a bunch of fixes for
those, hope they are generic enough for upstreaming.
CU
Uli
Ulrich Hec
Add is_i915_device() requirement to tests using Intel-specific APIs.
Signed-off-by: Ulrich Hecht
---
tests/kms_addfb_basic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index 7d8852f..cf9ba37 100644
--- a/tests/kms_addfb_basic.c
+++ b/
Checks if we have an i915 device before using intel_get_drm_devid().
Signed-off-by: Ulrich Hecht
---
lib/igt_gt.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index e630550..9cb07c2 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt
Ignores failure to add DRM_FORMAT_C8 frame buffer; some devices do not
support any 8-bit format.
Signed-off-by: Ulrich Hecht
---
tests/kms_addfb_basic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index d1da718..db7982
On Thu, 2018-03-15 at 14:22 +0100, Maarten Lankhorst wrote:
> Op 13-03-18 om 23:02 schreef Joe Perches:
> > drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary
> > arguments that can be removed by creating separate functins.
> >
> > Create specific functions for these calls to red
On 15/03/2018 14:46, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-03-15 14:37:59)
On 15/03/2018 13:45, Chris Wilson wrote:
As we are making changes to igt_spin_t, one of the ideas was that we put
the obj[] array there (with the offsets and flags setup correctly) so
that we could just feed
Quoting Tvrtko Ursulin (2018-03-15 14:53:08)
>
> On 15/03/2018 14:46, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-03-15 14:37:59)
> >>
> >> On 15/03/2018 13:45, Chris Wilson wrote:
> >>> As we are making changes to igt_spin_t, one of the ideas was that we put
> >>> the obj[] array there (
== Series Details ==
Series: Non-Intel test suite fixes
URL : https://patchwork.freedesktop.org/series/40038/
State : failure
== Summary ==
Applying: tests/kms_addfb_basic: skip i915-specific tests on other platforms
Applying: tests/kms_panel_fitting: check for i915 before checking version
App
On Thu, Mar 15, 2018 at 03:04:52PM +0100, Maarten Lankhorst wrote:
> Op 15-03-18 om 14:30 schreef Ville Syrjälä:
> > On Tue, Mar 13, 2018 at 03:02:15PM -0700, Joe Perches wrote:
> >> drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary
> >> arguments that can be removed by creating
If we fail to reset the GPU, we declare the machine wedged. However, the
GPU may well still be running in the background with an in-flight
request. So despite our efforts in cleaning up the request queue and
faking the breadcrumb in the HWSP, the GPU may eventually write the
in-flght seqno there br
On Thu, 2018-03-15 at 17:05 +0200, Ville Syrjälä wrote:
> On Thu, Mar 15, 2018 at 03:04:52PM +0100, Maarten Lankhorst wrote:
> > Op 15-03-18 om 14:30 schreef Ville Syrjälä:
> > > On Tue, Mar 13, 2018 at 03:02:15PM -0700, Joe Perches wrote:
> > > > drm_printk is used for both DRM_ERROR and DRM_DEBUG
From: Ville Syrjälä
While we want to potentially support multiple different gamma/degamma
LUT sizes we can (and should) at least check that the blob length
is a multiple of the LUT entry size.
v2: s/expected_size_mod/expected_elem_size/ (Daniel)
Add kernel doc (Daniel)
Cc: Daniel Vetter
Si
From: Ville Syrjälä
Provide a small helper to convert the blob length in bytes
to the number of LUT entries.
v2: Add kerneldoc (Daniel)
Cc: Daniel Vetter
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
include/drm/drm_color_mgmt.h | 12
1 file changed, 12 insertions
Quoting Ville Syrjälä (2018-03-01 11:12:53)
> On Thu, Mar 01, 2018 at 02:20:48AM +0100, Mario Kleiner wrote:
> > The various clut handling functions like a setup
> > consistent with the x-screen color depth. Otherwise
> > we observe improper sampling in the gamma tables
> > at depth 30.
> >
> > Th
In commit 56b9a8b08387 ("drm/i915/guc: Update syntax of GuC
log functions") we accidentally removed debugfs.h header
where needed stub functions were defined.
Reported-by: Mike Lothian
Signed-off-by: Michal Wajdeczko
Cc: Mike Lothian
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc_log.c |
On Thu, 15 Mar 2018, Daniel Vetter wrote:
> On Wed, Mar 14, 2018 at 05:11:02PM +0200, Jani Nikula wrote:
>> Until now, the drm-intel commit access have been handed out ad hoc,
>> without transparency, consistency, or fairness. With pressure to add
>> more committers, this is no longer tenable, if
On Thu, Mar 15, 2018 at 08:17:53AM -0700, Joe Perches wrote:
> On Thu, 2018-03-15 at 17:05 +0200, Ville Syrjälä wrote:
> > On Thu, Mar 15, 2018 at 03:04:52PM +0100, Maarten Lankhorst wrote:
> > > Op 15-03-18 om 14:30 schreef Ville Syrjälä:
> > > > On Tue, Mar 13, 2018 at 03:02:15PM -0700, Joe Perch
On Thu, 2018-03-15 at 17:37 +0200, Ville Syrjälä wrote:
> On Thu, Mar 15, 2018 at 08:17:53AM -0700, Joe Perches wrote:
> > On Thu, 2018-03-15 at 17:05 +0200, Ville Syrjälä wrote:
> > > On Thu, Mar 15, 2018 at 03:04:52PM +0100, Maarten Lankhorst wrote:
> > > > Op 15-03-18 om 14:30 schreef Ville Syrj
== Series Details ==
Series: series starting with [1/2] drm/i915: Trace GEM steps between submit and
wedging (rev3)
URL : https://patchwork.freedesktop.org/series/40029/
State : success
== Summary ==
Series 40029v3 series starting with [1/2] drm/i915: Trace GEM steps between
submit and wedgi
== Series Details ==
Series: series starting with [1/6] Revert "drm: Use a flexible array member for
blob property data" (rev3)
URL : https://patchwork.freedesktop.org/series/38886/
State : failure
== Summary ==
Applying: Revert "drm: Use a flexible array member for blob property data"
Applyi
From: Tvrtko Ursulin
More than one test assumes that the spinner is running pretty much
immediately after we have create or submitted it.
In actuality there is a variable delay, especially on execlists platforms,
between submission and spin batch starting to run on the hardware.
To enable tests
On Thu, Mar 15, 2018 at 03:28:47PM +, Michal Wajdeczko wrote:
> In commit 56b9a8b08387 ("drm/i915/guc: Update syntax of GuC
> log functions") we accidentally removed debugfs.h header
> where needed stub functions were defined.
>
> Reported-by: Mike Lothian
> Signed-off-by: Michal Wajdeczko
>
Chris Wilson writes:
> If we fail to reset the GPU, we declare the machine wedged. However, the
> GPU may well still be running in the background with an in-flight
> request. So despite our efforts in cleaning up the request queue and
> faking the breadcrumb in the HWSP, the GPU may eventually wr
On Wed, Mar 14, 2018 at 06:37:15PM +, Michal Wajdeczko wrote:
> We should avoid using guc_log prefix for functions that don't
> operate on GuC log, but rather request action from the GuC.
> Better to use guc_action prefix.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Michal Winiarski
> Cc: Saga
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