for I915: Acked-by: Shashank Sharma
Regards
Shashank
On 2/27/2018 6:26 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Currently we have a mix of static and dynamic information stored in
the display info structure. That makes it rather difficult to repopulate
the dynamic parts when a new EDID ap
Regards
Shashank
On 2/27/2018 6:26 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Now that we have split the display info into static and dynamic parts,
we can just zero out the entire dynamic part with memset(). Previously
we were just clearing parts of it, leaving stale data in other parts
(
On Tue, 27 Feb 2018, Manasi Navare wrote:
> default_rates[] array is a superset of all the link rates supported
> by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate
> to the set of link rates supported by sink. This patch adds this rate
> to default_rates[] array that gets used to
Chris Wilson writes:
> As the ftrace log is overflowing the pstore capture, we lose the gasps
> from dmesg which includes the GEM_BUG_ON function:line and condition that
> failed. Vital information for tracking down the bug, so append it to the
> frace log as well.
>
> Signed-off-by: Chris Wilson
On 27.02.2018 13:56, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we have a mix of static and dynamic information stored in
> the display info structure. That makes it rather difficult to repopulate
> the dynamic parts when a new EDID appears. Let's make life easier by
> splitting the
Quoting Mika Kuoppala (2018-02-28 09:14:41)
> Chris Wilson writes:
>
> > As the ftrace log is overflowing the pstore capture, we lose the gasps
> > from dmesg which includes the GEM_BUG_ON function:line and condition that
> > failed. Vital information for tracking down the bug, so append it to th
On Tue, 27 Feb 2018, Mustamin B Mustaffa wrote:
> Currently, BXT_PP is hardcoded with value '0'.
> It practically disabled eDP backlight on MRB (BXT) platform.
>
> This patch will tell which BXT_PP registers (there are two set of
> PP_CONTROL in the spec) to be used as defined in VBT (Video Bios T
Although we protect the request itself, we don't lock inside
intel_engine_dump() and so the request maybe retired as we peek into it.
One consequence is that the request->ctx may be freed before we
dereference it, leading to a use-after-free. Replace the hw_id we are
peeking from inside request->ct
== Series Details ==
Series: drm/i915/dp: move link rate arrays where they're used
URL : https://patchwork.freedesktop.org/series/39032/
State : success
== Summary ==
Series 39032v1 drm/i915/dp: move link rate arrays where they're used
https://patchwork.freedesktop.org/api/1.0/series/39032/rev
Hi Dave,
Cannonlake driver support is fine for the hardware we've had at our disposal
to test on, so we've removed the alpha_support protection for it. That'll be
the biggest visible change.
Other than there's fixes for Dell Venue 8 Pro display issues, audio only HDMI
and out-fences from execbuf.
From: Chris Wilson
CPU hotplug, especially CPU0, can be flaky on commodity hardware.
To improve test reliability and reponse times when testing larger runs we
need to handle those cases better.
Handle failures to off-line a CPU by immediately skipping the test, and
failures to on-line a CPU by
From: Tvrtko Ursulin
Mark drrs_set as static to avoid a build warning.
Signed-off-by: Tvrtko Ursulin
---
tests/kms_frontbuffer_tracking.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 1483c228044e..
From: Tvrtko Ursulin
Move variable declaration to top of scope to avoid C90 build warning.
Signed-off-by: Tvrtko Ursulin
---
tests/perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/perf.c b/tests/perf.c
index c302a355b850..78bf6cdd3504 100644
--- a/tests/perf.c
+
From: Tvrtko Ursulin
Gen11 will add more VCS and VECS rings so prepare the
infrastructure to support that.
Bspec: 7021
v2: Rebase.
v3: Rebase.
v4: Rebase.
v5: Rebase.
v6:
- Update for POR changes. (Daniele Ceraolo Spurio)
- Add provisional guc engine ids - to be checked and confirmed.
v7:
v2: Rebase.
v3:
* Remove DPF, it has been removed from SKL+.
* Fix -internal rebase wrt. execlists interrupt handling.
v4: Rebase.
v5:
* Updated for POR changes. (Daniele Ceraolo Spurio)
* Merged with irq handling fixes by Daniele Ceraolo Spurio:
* Simplify the code by using gen8_c
Thanks Jani.
Best regard
Mustamin
-Original Message-
From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
Sent: Wednesday, February 28, 2018 5:42 PM
To: Mustaffa, Mustamin B ;
intel-gfx@lists.freedesktop.org
Cc: Mustaffa, Mustamin B
Subject: Re: [Intel-gfx] [PATCH] [V3] drm/i915:
Reviewed-by: Lionel Landwerlin
On 28/02/18 10:08, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Move variable declaration to top of scope to avoid C90 build warning.
Signed-off-by: Tvrtko Ursulin
---
tests/perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/perf
Quoting Tvrtko Ursulin (2018-02-28 10:07:59)
> From: Tvrtko Ursulin
>
> Mark drrs_set as static to avoid a build warning.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
ht
== Series Details ==
Series: drm/i915/dp: move link rate arrays where they're used
URL : https://patchwork.freedesktop.org/series/39032/
State : warning
== Summary ==
Possible new issues:
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-scndscrn-indfb-msflip-blt:
pa
From: Tvrtko Ursulin
Some tests (the ones which call igt_setup_runtime_pm and
igt_pm_enable_audio_runtime_pm) change default system configuration and
never restore it.
The configured runtime suspend is aggressive and may influence behaviour
of subsequent tests, so it is better to restore to prev
On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote:
> On Tue, 2018-02-27 at 23:34 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 27, 2018 at 01:23:59PM -0800, José Roberto de Souza
> > wrote:
> > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > > self, so lets use the
Quoting Tvrtko Ursulin (2018-02-28 11:08:29)
> From: Tvrtko Ursulin
>
> Some tests (the ones which call igt_setup_runtime_pm and
> igt_pm_enable_audio_runtime_pm) change default system configuration and
> never restore it.
>
> The configured runtime suspend is aggressive and may influence behavi
== Series Details ==
Series: drm/i915: Don't deref request->ctx inside unlocked print_request()
URL : https://patchwork.freedesktop.org/series/39098/
State : success
== Summary ==
Series 39098v1 drm/i915: Don't deref request->ctx inside unlocked
print_request()
https://patchwork.freedesktop.o
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/icl: Prepare for more rings
URL : https://patchwork.freedesktop.org/series/39102/
State : warning
== Summary ==
Series 39102v1 series starting with [CI,1/2] drm/i915/icl: Prepare for more
rings
https://patchwork.freedesktop.o
On 28/02/2018 11:12, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-02-28 11:08:29)
From: Tvrtko Ursulin
Some tests (the ones which call igt_setup_runtime_pm and
igt_pm_enable_audio_runtime_pm) change default system configuration and
never restore it.
The configured runtime suspend is aggr
We're seeing on CI that some contexts don't have the programmed OA
period timer that directs the OA unit on how often to write reports.
The issue is that we're not holding the drm lock from when we edit the
context images down to when we set the exclusive_stream variable. This
leaves a window for
On Mon, Jan 22, 2018 at 11:14:01AM +0200, Chris Wilson wrote:
> Apply a random load to one or all engines in order to apply stress to
> RPS as it tries to constantly adjust the GPU frequency to meet the
> changing workload.
Doing some IGT archeology here.
Seems like both 'all' and 'pulse' subtest
== Series Details ==
Series: drm/i915/perf: fix perf stream opening lock
URL : https://patchwork.freedesktop.org/series/39112/
State : success
== Summary ==
Series 39112v1 drm/i915/perf: fix perf stream opening lock
https://patchwork.freedesktop.org/api/1.0/series/39112/revisions/1/mbox/
Quoting Arkadiusz Hiler (2018-02-28 12:11:41)
> On Mon, Jan 22, 2018 at 11:14:01AM +0200, Chris Wilson wrote:
> > Apply a random load to one or all engines in order to apply stress to
> > RPS as it tries to constantly adjust the GPU frequency to meet the
> > changing workload.
>
> Doing some IGT a
Quoting Tvrtko Ursulin (2018-02-28 11:38:01)
>
> On 28/02/2018 11:12, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-02-28 11:08:29)
> >> From: Tvrtko Ursulin
> >>
> >> Some tests (the ones which call igt_setup_runtime_pm and
> >> igt_pm_enable_audio_runtime_pm) change default system config
Chris Wilson writes:
> Although we protect the request itself, we don't lock inside
> intel_engine_dump() and so the request maybe retired as we peek into it.
> One consequence is that the request->ctx may be freed before we
> dereference it, leading to a use-after-free. Replace the hw_id we are
Quoting Mika Kuoppala (2018-02-28 12:32:40)
> Chris Wilson writes:
>
> > Although we protect the request itself, we don't lock inside
> > intel_engine_dump() and so the request maybe retired as we peek into it.
> > One consequence is that the request->ctx may be freed before we
> > dereference it
Chris Wilson writes:
> Although we protect the request itself, we don't lock inside
> intel_engine_dump() and so the request maybe retired as we peek into it.
> One consequence is that the request->ctx may be freed before we
> dereference it, leading to a use-after-free. Replace the hw_id we are
On Fri, Feb 23, 2018 at 04:04:10PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 23, 2018 at 01:52:22PM +, Brian Starkey wrote:
> > Hi Ville,
> >
> > On Thu, Feb 22, 2018 at 11:42:29PM +0200, Ville Syrjala wrote:
> > >From: Ville Syrjälä
> > >
> > >The documentation for the ctm matrix suggests a
On Fri, Feb 23, 2018 at 01:05:25PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
> >Sent: Friday, February 23, 2018 3:13 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Lin, Johnson ; Shankar, Uma
> >; Sharma, Shashank
Patchwork writes:
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/i915/icl: Prepare for more rings
> URL : https://patchwork.freedesktop.org/series/39102/
> State : warning
>
> == Summary ==
>
> Series 39102v1 series starting with [CI,1/2] drm/i915/icl: Prepare for more
>
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 23, 2018 7:23 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ;
>Sharma, Shashank
>Subject: Re: [PATCH 4/4] drm/i915: Don't mangle the CTM on pre-HSW
>
>On Fri
On Wed, Feb 28, 2018 at 01:11:12PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Friday, February 23, 2018 7:23 PM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ;
> >Sharma, Shashank
Quoting Mika Kuoppala (2018-02-28 12:49:00)
> Chris Wilson writes:
>
> > Although we protect the request itself, we don't lock inside
> > intel_engine_dump() and so the request maybe retired as we peek into it.
> > One consequence is that the request->ctx may be freed before we
> > dereference it
Quoting Tvrtko Ursulin (2018-02-28 11:08:29)
> From: Tvrtko Ursulin
>
> Some tests (the ones which call igt_setup_runtime_pm and
> igt_pm_enable_audio_runtime_pm) change default system configuration and
> never restore it.
>
> The configured runtime suspend is aggressive and may influence behavi
On 28/02/2018 12:27, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-02-28 11:38:01)
On 28/02/2018 11:12, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-02-28 11:08:29)
From: Tvrtko Ursulin
Some tests (the ones which call igt_setup_runtime_pm and
igt_pm_enable_audio_runtime_pm) change d
== Series Details ==
Series: drm/i915: Don't deref request->ctx inside unlocked print_request()
URL : https://patchwork.freedesktop.org/series/39098/
State : success
== Summary ==
Possible new issues:
Test kms_rotation_crc:
Subgroup primary-rotation-270:
fail
== Series Details ==
Series: drm/i915/perf: fix perf stream opening lock
URL : https://patchwork.freedesktop.org/series/39112/
State : success
== Summary ==
Possible new issues:
Test kms_rotation_crc:
Subgroup primary-rotation-270:
fail -> PASS (shard-
From: Tvrtko Ursulin
Some tests (the ones which call igt_setup_runtime_pm and
igt_pm_enable_audio_runtime_pm) change default system configuration and
never restore it.
The configured runtime suspend is aggressive and may influence behaviour
of subsequent tests, so it is better to restore to prev
Enabling FBC on a plane having a Y-offset that isn't dividable by 4 may
cause pipe FIFO underruns and flickers, so disable FBC on such a config.
I tried to the followings to work around the issue:
- enable each HW work around in ILK_DPFC_CHICKEN
- disable each compression algorithm in ILK_DPFC_CON
Hi Dave,
A few more fixes for 4.16, including 2 regression fixes. Please pull.
Thanks,
Gustavo
drm-misc-fixes-2018-02-28:
Two regression fixes here: a fb format regression on nouveau and a 4.16-rc1
regression with on LVDS with one sun4i device. Plus a sun4i and a virtio-gpu
fixes.
The followin
On Wednesday 14 February 2018 08:24 PM, Winkler, Tomas wrote:
Signed-off-by: Ramalingam C
---
drivers/misc/mei/Kconfig | 6 ++
drivers/misc/mei/Makefile | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index
c49e1d2269af..90977
__igt_spin_batch_new() may be used inside a background helper which is
competing against the GPU being reset. As such, we cannot even assert
that the spin->handle is busy immediately after submission as it may
have already been reset by another client writing to i915_wedged.
Signed-off-by: Chris W
Just a small variant to apply a continuous context-switch load to all
engines.
---
tests/gem_ctx_switch.c | 83 ++
1 file changed, 83 insertions(+)
diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
index 79b1d74b..4c7c5391 100644
--- a/te
If we do a global wait while trying to execute spinners in parallel,
it ends badly with a GPU hang.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104352
Signed-off-by: Chris Wilson
---
tests/gem_spin_batch.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --
Execute the same batch on each engine and check that the composite fence
across all engines completes only after the batch is completed on every
engine.
Signed-off-by: Chris Wilson
---
tests/gem_exec_fence.c | 127 +
1 file changed, 127 insertions(
EXEC_OBJECT_CAPTURE extends the type of buffers we may read during error
capture. Previously we knew that we would only see batch buffers (which
limited the objects to being from gem_create()), but now we need to
check that any buffer the user can create can be read. The first
alternate buffer type
== Series Details ==
Series: drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset
URL : https://patchwork.freedesktop.org/series/39129/
State : success
== Summary ==
Series 39129v1 drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset
https://patchwork.freedesktop.org/api/
On Wed, Feb 28, 2018 at 05:36:56PM +0200, Imre Deak wrote:
> Enabling FBC on a plane having a Y-offset that isn't dividable by 4 may
> cause pipe FIFO underruns and flickers, so disable FBC on such a config.
>
> I tried to the followings to work around the issue:
> - enable each HW work around in
> On Wednesday 14 February 2018 08:24 PM, Winkler, Tomas wrote:
> >> Signed-off-by: Ramalingam C
> >> ---
> >> drivers/misc/mei/Kconfig | 6 ++
> >> drivers/misc/mei/Makefile | 2 ++
> >> 2 files changed, 8 insertions(+)
> >>
> >> diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/K
On Thu, Feb 22, 2018 at 08:10:33PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> While it seems totally unlikely that any system would mix a cpu/north
> aux channel with a pch/south port (or vice versa) we should still
> consult intel_dp->aux_ch rather than encoder->port when figuring out
On Wed, Feb 28, 2018 at 06:05:11PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 28, 2018 at 05:36:56PM +0200, Imre Deak wrote:
> > Enabling FBC on a plane having a Y-offset that isn't dividable by 4 may
> > cause pipe FIFO underruns and flickers, so disable FBC on such a config.
> >
> > I tried to th
From: Tvrtko Ursulin
Verify that the reported busyness is in line with what would we expect
from a batch which causes a hang and gets kicked out from the engine.
v2: Change to explicit igt_force_gpu_reset instead of guessing when a spin
batch will hang. (Chris Wilson)
Signed-off-by: Tvrtko
From: Tvrtko Ursulin
In decimal its just a weird big number, while in hex can actually log
which engines were requested to be wedged.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
On Wed, Feb 28, 2018 at 11:05:24AM +0200, Jani Nikula wrote:
> On Tue, 27 Feb 2018, Manasi Navare wrote:
> > default_rates[] array is a superset of all the link rates supported
> > by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate
> > to the set of link rates supported by sink. T
== Series Details ==
Series: drm/i915: Wedged engine mask makes more sense in hex
URL : https://patchwork.freedesktop.org/series/39147/
State : success
== Summary ==
Series 39147v1 drm/i915: Wedged engine mask makes more sense in hex
https://patchwork.freedesktop.org/api/1.0/series/39147/revis
On 2/26/2018 9:49 PM, Sagar Arun Kamble wrote:
On 2/27/2018 4:34 AM, Oscar Mateo wrote:
On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote:
On 2/23/2018 4:35 AM, Oscar Mateo wrote:
+ * We might have detected that some engines are fused off after
we initialized
+ * the forcewake domains
On 28 February 2018 at 11:45, Lionel Landwerlin
wrote:
> We're seeing on CI that some contexts don't have the programmed OA
> period timer that directs the OA unit on how often to write reports.
>
> The issue is that we're not holding the drm lock from when we edit the
> context images down to whe
On Wed, 28 Feb 2018, Manasi Navare wrote:
> On Wed, Feb 28, 2018 at 11:05:24AM +0200, Jani Nikula wrote:
>> On Tue, 27 Feb 2018, Manasi Navare wrote:
>> > default_rates[] array is a superset of all the link rates supported
>> > by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate
>
In the i915 driver, there is a function, intel_guc_init_params(),
which initializes the GuC parameter block which is passed into
the GuC. There is parameter GUC_CTL_DEVICE_INFO with values
GfxGtType and GfxCoreFamily unused by GuC.
This patch remove GUC_CTL_DEVICE_INFO with GfxGtType and
GfxCoreFa
On 28/02/18 09:18, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
In decimal its just a weird big number, while in hex can actually log
which engines were requested to be wedged.
And IGT is not reading the hang reason in this case, so
Reviewed-by: Michel Thierry
Signed-off-by: Tvrtko Ursuli
On Tue, 2018-02-27 at 23:17 -0800, Manasi Navare wrote:
> Ville, thanks for the patch and
> Sorry for not being able to review this earlier.
> Please find some comments below:
>
> On Wed, Jan 31, 2018 at 03:27:10PM +0200, Ville Syrjälä wrote:
> > On Tue, Jan 30, 2018 at 06:16:59PM -0500, Lyude P
On 28/02/18 07:51, Chris Wilson wrote:
Just a small variant to apply a continuous context-switch load to all
engines.
---
tests/gem_ctx_switch.c | 83 ++
1 file changed, 83 insertions(+)
diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_swit
== Series Details ==
Series: drm/i915/guc: Removed unused GuC parameters.
URL : https://patchwork.freedesktop.org/series/39154/
State : success
== Summary ==
Series 39154v1 drm/i915/guc: Removed unused GuC parameters.
https://patchwork.freedesktop.org/api/1.0/series/39154/revisions/1/mbox/
fi
On Wed, Feb 28, 2018 at 02:07:34PM -0500, Lyude Paul wrote:
>
> On Tue, 2018-02-27 at 23:17 -0800, Manasi Navare wrote:
> > Ville, thanks for the patch and
> > Sorry for not being able to review this earlier.
> > Please find some comments below:
> >
> > On Wed, Jan 31, 2018 at 03:27:10PM +0200,
On Wed, 2018-02-28 at 11:27 -0800, Manasi Navare wrote:
> On Wed, Feb 28, 2018 at 02:07:34PM -0500, Lyude Paul wrote:
> >
> > On Tue, 2018-02-27 at 23:17 -0800, Manasi Navare wrote:
> > > Ville, thanks for the patch and
> > > Sorry for not being able to review this earlier.
> > > Please find some
On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote:
> Add PWM mode to pwm_config() function. The drivers which uses pwm_config()
> were adapted to this change.
>
> Signed-off-by: Claudiu Beznea
> ---
> arch/arm/mach-s3c24xx/mach-rx1950.c | 11 +--
> drivers/bus/ts-nbus.c
On Wed, Feb 28, 2018 at 02:41:06PM -0500, Lyude Paul wrote:
> On Wed, 2018-02-28 at 11:27 -0800, Manasi Navare wrote:
> > On Wed, Feb 28, 2018 at 02:07:34PM -0500, Lyude Paul wrote:
> > >
> > > On Tue, 2018-02-27 at 23:17 -0800, Manasi Navare wrote:
> > > > Ville, thanks for the patch and
> > > >
On Thu, Feb 22, 2018 at 12:55:05AM -0300, Paulo Zanoni wrote:
> HDMI mode DPLL programming on ICL is the same as CNL, so just reuse
> the CNL code.
>
> v2:
> - Properly detect HDMI crtcs.
> - Rebase after changes to the cnl function (clock * 1000).
>
> Signed-off-by: Paulo Zanoni
> ---
> driv
== Series Details ==
Series: drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset
URL : https://patchwork.freedesktop.org/series/39129/
State : warning
== Summary ==
Possible new issues:
Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-bottom-edge:
pas
On Wed, 28 Feb 2018, Thierry Reding wrote:
> Anyone that needs something other than normal mode should use the new
> atomic PWM API.
At the risk of revealing my true ignorance, what is the new atomic PWM
API? Where? Examples of how one would convert old code over to the new
API?
BR,
Jani.
--
J
On Wed, Jan 17, 2018 at 09:21:49PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> LSPCON likes to throw short HPDs during the enable seqeunce prior to the
> link being trained. These obviously result in the channel CR/EQ check
> failing and thus we schedule a pointless hotplug work to retr
On Thu, Feb 22, 2018 at 12:55:06AM -0300, Paulo Zanoni wrote:
> Just use the hardcoded tables provided by our spec.
>
> v2: Rebase.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 86
> ++-
> 1 file changed, 85 insertions(+), 1 de
On Thu, Jan 18, 2018 at 10:59:04PM -0800, Rodrigo Vivi wrote:
> On Wed, Jan 17, 2018 at 07:21:48PM +, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > intel_dp->channel_eq_status is used in exactly one function, and we
> > don't need it to persist between calls. So just go back to using a
On Wed, 2018-02-28 at 11:57 -0800, Manasi Navare wrote:
> On Wed, Feb 28, 2018 at 02:41:06PM -0500, Lyude Paul wrote:
> > On Wed, 2018-02-28 at 11:27 -0800, Manasi Navare wrote:
> > > On Wed, Feb 28, 2018 at 02:07:34PM -0500, Lyude Paul wrote:
> > > >
> > > > On Tue, 2018-02-27 at 23:17 -0800, Man
On 28/02/18 10:42, Piotr Piórkowski wrote:
In the i915 driver, there is a function, intel_guc_init_params(),
which initializes the GuC parameter block which is passed into
the GuC. There is parameter GUC_CTL_DEVICE_INFO with values
GfxGtType and GfxCoreFamily unused by GuC.
This patch remove GUC
On Sat, Feb 24, 2018 at 03:24:55AM +, Pandiyan, Dhinakaran wrote:
>
>
>
> On Mon, 2018-02-19 at 10:07 +0100, Maarten Lankhorst wrote:
> > Op 16-02-18 om 20:27 schreef Pandiyan, Dhinakaran:
> > > On Fri, 2018-02-16 at 08:55 +, Chris Wilson wrote:
> > >> Quoting Dhinakaran Pandiyan (2018-0
Hi Dave,
Here's this weeks pull, relatively small when you pull out the trivial fixes.
drm-misc-next-2018-02-28:
drm-misc-next for 4.17:
UAPI Changes:
Fix drm_color_ctm matrix docs to match usage and change the type to
__u64 make it obvious (Ville)
Core Changes:
Check modifier with format wh
On Wed, Feb 28, 2018 at 10:28:13PM +0200, Ville Syrjälä wrote:
> On Sat, Feb 24, 2018 at 03:24:55AM +, Pandiyan, Dhinakaran wrote:
> >
> >
> >
> > On Mon, 2018-02-19 at 10:07 +0100, Maarten Lankhorst wrote:
> > > Op 16-02-18 om 20:27 schreef Pandiyan, Dhinakaran:
> > > > On Fri, 2018-02-16 a
On Gen9 systems, with SAGV enabled, we have seen display
corruption(screenshots attached in the bug) which eventually lead to a
system hang. This happens when we have overlay plane and on enabling
and disabling the overlay plane. When the system hangs, we do not have
enough logs or information to d
On Wed, Feb 14, 2018 at 09:23:24PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On GLK the plane CSC controls moved into the COLOR_CTL register.
> Update the code to progam the YCbCr->RGB CSC mode correctly when
> faced with an YCbCr framebuffer.
>
> The spec is rather confusing as it c
On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote:
> Localize link rate arrays by moving them to the functions where they're
> used. Further clarify the distinction between source and sink
> capabilities. Split pre and post Haswell arrays, and get rid of the
> array size arithmetics. Use
On Tue, Feb 27, 2018 at 7:56 AM, Ville Syrjala
wrote:
> From: Ville Syrjälä
>
> Currently we have a mix of static and dynamic information stored in
> the display info structure. That makes it rather difficult to repopulate
> the dynamic parts when a new EDID appears. Let's make life easier by
> s
On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote:
> Localize link rate arrays by moving them to the functions where they're
> used. Further clarify the distinction between source and sink
> capabilities. Split pre and post Haswell arrays, and get rid of the
> array size arithmetics. Use
== Series Details ==
Series: drm/i915: Add an option to disable SAGV
URL : https://patchwork.freedesktop.org/series/39161/
State : success
== Summary ==
Series 39161v1 drm/i915: Add an option to disable SAGV
https://patchwork.freedesktop.org/api/1.0/series/39161/revisions/1/mbox/
Possibl
On Wed, 28 Feb 2018, Manasi Navare wrote:
> On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote:
>> Localize link rate arrays by moving them to the functions where they're
>> used. Further clarify the distinction between source and sink
>> capabilities. Split pre and post Haswell arrays, a
On 28/02/18 12:26, Michel Thierry wrote:
On 28/02/18 10:42, Piotr Piórkowski wrote:
In the i915 driver, there is a function, intel_guc_init_params(),
which initializes the GuC parameter block which is passed into
the GuC. There is parameter GUC_CTL_DEVICE_INFO with values
GfxGtType and GfxCoreFa
== Series Details ==
Series: drm/i915: Wedged engine mask makes more sense in hex
URL : https://patchwork.freedesktop.org/series/39147/
State : failure
== Summary ==
Possible new issues:
Test kms_draw_crc:
Subgroup draw-method-xrgb-mmap-cpu-xtiled:
skip
dp_rates[] array is a superset of all the link rates supported
by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate
to the set of link rates supported by sink. This patch adds this rate
to dp_rates[] array that gets used to populate the sink_rates[]
array limited by max rate obtained
On 28/02/18 07:51, Chris Wilson wrote:
Execute the same batch on each engine and check that the composite fence
across all engines completes only after the batch is completed on every
engine.
Signed-off-by: Chris Wilson
LGTM.
Reviewed-by: Antonio Argenziano
---
tests/gem_exec_fence.c
== Series Details ==
Series: drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array
URL : https://patchwork.freedesktop.org/series/39165/
State : success
== Summary ==
Series 39165v1 drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array
https://patchwork.freedesktop.org/api/1.0/series/39165
On Wed, 2018-02-28 at 22:38 +0200, Ville Syrjälä wrote:
> On Wed, Feb 28, 2018 at 10:28:13PM +0200, Ville Syrjälä wrote:
> > On Sat, Feb 24, 2018 at 03:24:55AM +, Pandiyan, Dhinakaran wrote:
> > >
> > >
> > >
> > > On Mon, 2018-02-19 at 10:07 +0100, Maarten Lankhorst wrote:
> > > > Op 16-
On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote:
> On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote:
> > On Tue, 2018-02-27 at 23:34 +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 27, 2018 at 01:23:59PM -0800, José Roberto de Souza
> > > wrote:
> > > > When PSR/PSR2/GTC is enabled
== Series Details ==
Series: drm/i915/guc: Removed unused GuC parameters.
URL : https://patchwork.freedesktop.org/series/39154/
State : failure
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-apl)
Test drv_selftest:
Subgroup
Signed-off-by: Jackie Li
---
drivers/gpu/drm/i915/i915_params.c | 2 +-
drivers/gpu/drm/i915/i915_params.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 08108ce..b49ae20 100644
--- a/drivers/gp
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