[Intel-gfx] [RFC] drm/i915: Eliminate devid sprinkle

From: Tvrtko Ursulin Introduce subplatform mask to eliminate throughout the code devid checking sprinkle, mostly courtesy of IS_*_UL[TX] macros. Subplatform mask initialization is moved either to static tables (Ironlake M) or runtime device info init (Pineview, Haswell, Broadwell, Skylake, Kabyl

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

== Series Details == Series: series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it URL : https://patchwork.freedesktop.org/series/38744/ State : success == Summary == Series 38744v1 series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux i

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Eliminate devid sprinkle

== Series Details == Series: drm/i915: Eliminate devid sprinkle URL : https://patchwork.freedesktop.org/series/38749/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2cce38de5993 drm/i915: Eliminate devid sprinkle -:171: WARNING: line over 80 characters #171: FILE: drivers/gpu/dr

Re: [Intel-gfx] [RFC] drm/i915: Eliminate devid sprinkle

Quoting Tvrtko Ursulin (2018-02-22 08:09:07) > From: Tvrtko Ursulin > > Introduce subplatform mask to eliminate throughout the code devid checking > sprinkle, mostly courtesy of IS_*_UL[TX] macros. > > Subplatform mask initialization is moved either to static tables (Ironlake > M) or runtime dev

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

On 22/02/2018 07:51, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-22 06:07:32) From: Tvrtko Ursulin Place context in/out hooks into the GuC backend, when contexts are assigned to ports, and removed from them, in order to be able to provide engine busy stats in GuC mode. Signed-off-by:

[Intel-gfx] [PATCH igt] igt/gem_ctx_isolation: Fix checking for context support

Missed the new method for igt_require(gem_has_contexts()) in the rebase. Signed-off-by: Chris Wilson --- tests/gem_ctx_isolation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c index cb822c5b..d8109aa0 100644 --- a/tests

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Eliminate devid sprinkle

== Series Details == Series: drm/i915: Eliminate devid sprinkle URL : https://patchwork.freedesktop.org/series/38749/ State : warning == Summary == Series 38749v1 drm/i915: Eliminate devid sprinkle https://patchwork.freedesktop.org/api/1.0/series/38749/revisions/1/mbox/ Test gem_mmap_gtt:

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

Quoting Tvrtko Ursulin (2018-02-22 08:26:58) > > On 22/02/2018 07:51, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-02-22 06:07:32) > >> From: Tvrtko Ursulin > >> > >> Place context in/out hooks into the GuC backend, when contexts are > >> assigned to ports, and removed from them, in order

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Eliminate devid sprinkle

Quoting Patchwork (2018-02-22 08:30:36) > == Series Details == > > Series: drm/i915: Eliminate devid sprinkle > URL : https://patchwork.freedesktop.org/series/38749/ > State : warning > > == Summary == > > Series 38749v1 drm/i915: Eliminate devid sprinkle > https://patchwork.freedesktop.org/ap

[Intel-gfx] [PATCH igt] lib/dummyload: Avoid assertions in lowlevel spin constructor

__igt_spin_batch_new() may be used inside a background helper which is competing against the GPU being reset. As such, we cannot even assert that the spin->handle is busy immediately after submission as it may have already been reset by another client writing to i915_wedged. Signed-off-by: Chris W

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Add a GEM_TRACE to show when the context is completed

Chris Wilson writes: > Quoting Mika Kuoppala (2018-02-21 15:21:04) >> Chris Wilson writes: >> >> > Include a GEM_TRACE to show when the context is complete and we advance >> > the ELSP port. >> > >> > Signed-off-by: Chris Wilson >> > Cc: Mika Kuoppala >> > --- >> > drivers/gpu/drm/i915/intel

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Move the GEM_BUG_ON context matches CSB later

Chris Wilson writes: > Print out the current request/context before doing the GEM_BUG_ON, so > that we can inspect the values in the ftrace. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_lrc.c | 7 --- > 1 file changed,

[Intel-gfx] ✓ Fi.CI.BAT: success for Iterate over physical engines

== Series Details == Series: Iterate over physical engines URL : https://patchwork.freedesktop.org/series/38746/ State : success == Summary == IGT patchset tested on top of latest successful build af65798b6674e28816bd13c096963c2d7fcdd856 lib/igt_perf: Find active perf CPU with latest DRM-Tip

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Eliminate devid sprinkle

On 22/02/2018 08:35, Chris Wilson wrote: Quoting Patchwork (2018-02-22 08:30:36) == Series Details == Series: drm/i915: Eliminate devid sprinkle URL : https://patchwork.freedesktop.org/series/38749/ State : warning == Summary == Series 38749v1 drm/i915: Eliminate devid sprinkle https://pat

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2) URL : https://patchwork.freedesktop.org/series/38717/ State : failure == Summary == Test drv_missed_irq: pass -> SKIP (shard-apl) Test drv_selftest: Subgr

[Intel-gfx] [RFC v2] drm/i915: Eliminate devid sprinkle

From: Tvrtko Ursulin Introduce subplatform mask to eliminate throughout the code devid checking sprinkle, mostly courtesy of IS_*_UL[TX] macros. Subplatform mask initialization is moved either to static tables (Ironlake M) or runtime device info init (Pineview, Haswell, Broadwell, Skylake, Kabyl

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Move the GEM_BUG_ON context matches CSB later

Quoting Mika Kuoppala (2018-02-22 08:51:40) > Chris Wilson writes: > > > Print out the current request/context before doing the GEM_BUG_ON, so > > that we can inspect the values in the ftrace. > > > > Signed-off-by: Chris Wilson > > Cc: Mika Kuoppala > > Reviewed-by: Mika Kuoppala Thanks, pu

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Reduce context HW ID lifetime

Quoting Lionel Landwerlin (2018-02-21 01:12:46) > On 09/02/18 20:47, Chris Wilson wrote: > > Quoting Daniele Ceraolo Spurio (2018-02-09 18:56:36) > >> > >> On 09/02/18 02:22, Chris Wilson wrote: > >>> Future gen reduce the number of bits we will have available to > >>> differentiate between context

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Eliminate devid sprinkle (rev2)

== Series Details == Series: drm/i915: Eliminate devid sprinkle (rev2) URL : https://patchwork.freedesktop.org/series/38749/ State : warning == Summary == Series 38749v2 drm/i915: Eliminate devid sprinkle https://patchwork.freedesktop.org/api/1.0/series/38749/revisions/2/mbox/ Test debugfs_te

[Intel-gfx] [PATCH 2/2] drm/i915/breadcrumbs: Assert all missed breadcrumbs were signaled

When parking the engines and their breadcrumbs, if we have waiters left then they missed their wakeup. Verify that each waiter's seqno did complete. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_breadcrumbs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/

[Intel-gfx] [PATCH 1/2] drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list

The goal here is to try and reduce the latency of signaling additional requests following the wakeup from interrupt by reducing the list of to-be-signaled requests from an rbtree to a sorted linked list. The original choice of using an rbtree was to facilitate random insertions of request into the

Re: [Intel-gfx] [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs

Daniele Ceraolo Spurio writes: > On 20/02/18 07:37, Mika Kuoppala wrote: >> From: Tvrtko Ursulin >> >> Show GEN11 specific interrupt registers in debugfs >> >> v2: Update for POR changes. (Daniele Ceraolo Spurio) >> v3: get runtime pm ref. unify common parts with gen8 (Daniele) >> >> Cc: Cera

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Extend partial vma coverage to check parallel creation

Quoting Chris Wilson (2018-01-16 10:11:43) > One important use of partial vma is to provide mappable access to the > object while it is being used elsewhere (pinned entirely into the > unmappable portion of the Global GTT, i.e. for use as a display scanout). > > Signed-off-by: Chris Wilson > Cc:

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

== Series Details == Series: series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it URL : https://patchwork.freedesktop.org/series/38744/ State : warning == Summary == Test kms_pipe_crc_basic: Subgroup read-crc-pipe-c-frame-sequence: p

[Intel-gfx] [RFC v3] drm/i915: Eliminate devid sprinkle

From: Tvrtko Ursulin Introduce subplatform mask to eliminate throughout the code devid checking sprinkle, mostly courtesy of IS_*_UL[TX] macros. Subplatform mask initialization is moved either to static tables (Ironlake M) or runtime device info init (Pineview, Haswell, Broadwell, Skylake, Kabyl

Re: [Intel-gfx] [RFC v3] drm/i915: Eliminate devid sprinkle

Quoting Tvrtko Ursulin (2018-02-22 10:15:04) > +#define INTEL_SUBPLATFORM_IRONLAKE_M (0) > + > +#define INTEL_SUBPLATFORM_PINEVIEW_G (0) > +#define INTEL_SUBPLATFORM_PINEVIEW_M (1) Looking at these, we can reduce these to IS_MOBILE. Clearer before or after this conversion? Pretty orthogonal I thin

Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: New power domain for AUX IO.

On Wed, Feb 21, 2018 at 11:28:56PM -0800, Dhinakaran Pandiyan wrote: > PSR on CNL requires AUX IO wells to be kept on and the existing AUX domain > for AUX-A enables DC_OFF well too. This is not required, so add a new > AUX_IO_A domain for AUX-A to allow DC states to remain enabled. Other AUX > cha

[Intel-gfx] [CI] drm/i915/icl: Prepare for more rings

From: Tvrtko Ursulin Gen11 will add more VCS and VECS rings so prepare the infrastructure to support that. Bspec: 7021 v2: Rebase. v3: Rebase. v4: Rebase. v5: Rebase. v6: - Update for POR changes. (Daniele Ceraolo Spurio) - Add provisional guc engine ids - to be checked and confirmed. v7:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list

== Series Details == Series: series starting with [1/2] drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list URL : https://patchwork.freedesktop.org/series/38755/ State : success == Summary == Series 38755v1 series starting with [1/2] drm/i915/breadcrumbs: Reduce signaler rbtree to

[Intel-gfx] [PATCH igt] Iterate over physical engines

We current have a single for_each_engine() iterator which we use to generate both a set of uABI engines and a set of physical engines. Determining what uABI ring-id corresponds to an actual HW engine is tricky, so pull that out to a library function and introduce for_each_physical_engine() for case

[Intel-gfx] [PATCH igt] igt/perf_pmu: Fix 64b printf-isms

My bad, perf_pmu.c: In function ‘accuracy’: perf_pmu.c:1533:4: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 5 has type ‘uint64_t’ [-Wformat] perf_pmu.c:1533:4: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 6 has type ‘uint64_

Re: [Intel-gfx] [RFC] drm/i915: Eliminate devid sprinkle

On 22/02/2018 08:24, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-22 08:09:07) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 71fdfb0451ef..7b6211061fba 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Eliminate devid sprinkle (rev3)

== Series Details == Series: drm/i915: Eliminate devid sprinkle (rev3) URL : https://patchwork.freedesktop.org/series/38749/ State : warning == Summary == Series 38749v3 drm/i915: Eliminate devid sprinkle https://patchwork.freedesktop.org/api/1.0/series/38749/revisions/3/mbox/ Test gem_exec_s

Re: [Intel-gfx] [PATCH igt v3] Iterate over physical engines

On 22/02/2018 07:52, Chris Wilson wrote: We current have a single for_each_engine() iterator which we use to generate both a set of uABI engines and a set of physical engines. Determining what uABI ring-id corresponds to an actual HW engine is tricky, so pull that out to a library function and i

Re: [Intel-gfx] [RFC v3] drm/i915: Eliminate devid sprinkle

Quoting Tvrtko Ursulin (2018-02-22 10:15:04) > +void intel_device_info_subplatform_init(struct intel_device_info *info) > +{ > + struct drm_i915_private *i915 = > + container_of(info, struct drm_i915_private, info); > + u16 devid = INTEL_DEVID(i915); > + > + if (IS_P

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Prepare for more rings (rev2)

== Series Details == Series: drm/i915/icl: Prepare for more rings (rev2) URL : https://patchwork.freedesktop.org/series/38150/ State : success == Summary == Series 38150v2 drm/i915/icl: Prepare for more rings https://patchwork.freedesktop.org/api/1.0/series/38150/revisions/2/mbox/ Test gem_mm

Re: [Intel-gfx] [CI] drm/i915/icl: Prepare for more rings

Quoting Mika Kuoppala (2018-02-22 10:28:39) > diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h > index e920dab7f1b8..1b61b7f8c2ec 100644 > --- a/drivers/gpu/drm/i915/i915_gem.h > +++ b/drivers/gpu/drm/i915/i915_gem.h > @@ -54,6 +54,6 @@ > #define GEM_TRACE(...) do { }

Re: [Intel-gfx] [PATCH igt] igt/perf_pmu: Fix 64b printf-isms

On 22/02/2018 10:33, Chris Wilson wrote: My bad, perf_pmu.c: In function ‘accuracy’: perf_pmu.c:1533:4: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 5 has type ‘uint64_t’ [-Wformat] perf_pmu.c:1533:4: warning: format ‘%lu’ expects argument of type ‘long uns

[Intel-gfx] [PATCH] drm/i915: Move page sizes out of the 8-bit sandwich

From: Tvrtko Ursulin Slightly smaller code and a bit more logical layout. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_device_info.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_de

Re: [Intel-gfx] [PATCH] drm/i915: Move page sizes out of the 8-bit sandwich

Quoting Tvrtko Ursulin (2018-02-22 11:16:58) > From: Tvrtko Ursulin > > Slightly smaller code and a bit more logical layout. > > Signed-off-by: Tvrtko Ursulin > --- > drivers/gpu/drm/i915/intel_device_info.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/

[Intel-gfx] ✗ Fi.CI.IGT: failure for Iterate over physical engines

== Series Details == Series: Iterate over physical engines URL : https://patchwork.freedesktop.org/series/38746/ State : failure == Summary == Test kms_chv_cursor_fail: Subgroup pipe-b-128x128-top-edge: dmesg-warn -> PASS (shard-snb) fdo#105185 Test gem_exec_sched

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Reduce context HW ID lifetime

On 22/02/18 09:17, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-02-21 01:12:46) On 09/02/18 20:47, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2018-02-09 18:56:36) On 09/02/18 02:22, Chris Wilson wrote: Future gen reduce the number of bits we will have available to differentiat

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Move page sizes out of the 8-bit sandwich

== Series Details == Series: drm/i915: Move page sizes out of the 8-bit sandwich URL : https://patchwork.freedesktop.org/series/38764/ State : failure == Summary == Series 38764v1 drm/i915: Move page sizes out of the 8-bit sandwich https://patchwork.freedesktop.org/api/1.0/series/38764/revisio

[Intel-gfx] ✓ Fi.CI.BAT: success for lib/dummyload: Avoid assertions in lowlevel spin constructor

== Series Details == Series: lib/dummyload: Avoid assertions in lowlevel spin constructor URL : https://patchwork.freedesktop.org/series/38753/ State : success == Summary == IGT patchset tested on top of latest successful build f09f5c6a197424cef70d6864416ac1f4fd23 igt/perf_pmu: Fix 64b pri

Re: [Intel-gfx] [PATCH v3 05/10] pwm: add PWM mode to pwm_config()

On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote: > Add PWM mode to pwm_config() function. The drivers which uses pwm_config() > were adapted to this change. > > Signed-off-by: Claudiu Beznea > --- > arch/arm/mach-s3c24xx/mach-rx1950.c | 11 +-- > drivers/bus/ts-nbus.c

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Nuke aux regs from intel_dp

On Thu, Feb 22, 2018 at 07:16:07AM +, Pandiyan, Dhinakaran wrote: > > On Tue, 2018-02-20 at 21:00 +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Just store function pointers that give us the correct register offsets > > instead of storing the register offsets themselves. Slightl

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

On Thu, Feb 22, 2018 at 07:25:22AM +, Pandiyan, Dhinakaran wrote: > > > > On Tue, 2018-02-20 at 11:31 -0800, Rodrigo Vivi wrote: > > On Tue, Feb 20, 2018 at 07:05:22PM +0200, Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > > > Since we no longer have a 1:1 correspondence between por

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move page sizes out of the 8-bit sandwich

== Series Details == Series: drm/i915: Move page sizes out of the 8-bit sandwich URL : https://patchwork.freedesktop.org/series/38764/ State : success == Summary == Series 38764v1 drm/i915: Move page sizes out of the 8-bit sandwich https://patchwork.freedesktop.org/api/1.0/series/38764/revisio

Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

On 22.02.2018 04:39, Srinivas, Vidya wrote: -Original Message- From: Juha-Pekka Heikkila [mailto:juhapekka.heikk...@gmail.com] Sent: Wednesday, February 21, 2018 7:52 PM To: Srinivas, Vidya ; intel- g...@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list

== Series Details == Series: series starting with [1/2] drm/i915/breadcrumbs: Reduce signaler rbtree to a sorted list URL : https://patchwork.freedesktop.org/series/38755/ State : success == Summary == Test pm_rps: Subgroup reset: incomplete -> PASS (shard-apl) f

Re: [Intel-gfx] [PATCH v3 3/6] drm/i915: Clean up fbc vs. plane checks

On Wed, Feb 21, 2018 at 09:59:27PM +, Chris Wilson wrote: > Quoting Ville Syrjala (2018-02-21 17:31:01) > > From: Ville Syrjälä > > > > Let's record the information whether a plane can do fbc or not under > > struct inte_plane. > > > > v2: Rebase due to i9xx_plane_id > > Handle BDW/HSW c

[Intel-gfx] [PATCH] drm/i915/preemption: Allow preemption between submission ports

Sometimes we need to boost the priority of an in-flight request, which may lead to the situation where the second submission port then contains a higher priority context than the first and so we need to inject a preemption event. To do so we must always check inside execlists_dequeue() whether ther

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout

On Wed, Feb 21, 2018 at 09:52:04PM +, Chris Wilson wrote: > Quoting Ville Syrjala (2018-02-21 16:02:30) > > From: Ville Syrjälä > > > > Gen2/3 display engine depends on the fence for tiled scanout. So if we > > fail to get a fence fail the entire operation. > > > > Cc: Chris Wilson > > Sign

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move page sizes out of the 8-bit sandwich

On 22/02/2018 13:01, Patchwork wrote: == Series Details == Series: drm/i915: Move page sizes out of the 8-bit sandwich URL : https://patchwork.freedesktop.org/series/38764/ State : success == Summary == Series 38764v1 drm/i915: Move page sizes out of the 8-bit sandwich https://patchwork.fre

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout

Quoting Ville Syrjälä (2018-02-22 14:13:34) > On Wed, Feb 21, 2018 at 09:52:04PM +, Chris Wilson wrote: > > Ok, I'd like to see INTEL_GEN(dev_priv) < 4 be replaced with say > > needs_fence (and may be passed in from the caller like wants_fence?). > > I had that earlier, but then I didn't have

[Intel-gfx] [PATCH] drm/i915/preemption: Allow preemption between submission ports

Sometimes we need to boost the priority of an in-flight request, which may lead to the situation where the second submission port then contains a higher priority context than the first and so we need to inject a preemption event. To do so we must always check inside execlists_dequeue() whether ther

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Prepare for more rings (rev2)

== Series Details == Series: drm/i915/icl: Prepare for more rings (rev2) URL : https://patchwork.freedesktop.org/series/38150/ State : failure == Summary == Test kms_flip: Subgroup 2x-plain-flip-fb-recreate: fail -> PASS (shard-hsw) fdo#100368 Subgro

Re: [Intel-gfx] [PATCH] drm/i915/preemption: Allow preemption between submission ports

Quoting Chris Wilson (2018-02-22 14:22:29) > Sometimes we need to boost the priority of an in-flight request, which > may lead to the situation where the second submission port then contains > a higher priority context than the first and so we need to inject a > preemption event. To do so we must a

Re: [Intel-gfx] [PATCH 22/43] drm/i915: Async execution of hdcp authentication

On Wed, Feb 14, 2018 at 07:43:37PM +0530, Ramalingam C wrote: > Each HDCP authentication, could take upto 5.1Sec, based on the > downstream HDCP topology. > > Hence to avoid this much delay in the atomic_commit path, this patch > schedules the HDCP authentication into a asynchronous work. > > Thi

Re: [Intel-gfx] [PATCH 23/43] drm/i915: wrapping all hdcp var into intel_hdcp

On Wed, Feb 14, 2018 at 07:43:38PM +0530, Ramalingam C wrote: > Considering the upcoming significant no HDCP2.2 variables, it will > be clean to have separate struct fo HDCP. > > New structure called intel_hdcp is introduced. > > Signed-off-by: Ramalingam C > --- > drivers/gpu/drm/i915/intel_di

Re: [Intel-gfx] [PATCH 25/43] drm/i915: Define HDCP2.2 related variables

On Wed, Feb 14, 2018 at 07:43:40PM +0530, Ramalingam C wrote: > For upcoming implementation of HDCP2.2 in I915, all variable required > for HDCP2.2 are defined. > > This includes a translation layer called hdcp2_shim for encoder > specific HDCP2.2 spec deviations. > > Signed-off-by: Ramalingam C

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/preemption: Allow preemption between submission ports (rev2)

== Series Details == Series: drm/i915/preemption: Allow preemption between submission ports (rev2) URL : https://patchwork.freedesktop.org/series/38774/ State : success == Summary == Series 38774v2 drm/i915/preemption: Allow preemption between submission ports https://patchwork.freedesktop.org

Re: [Intel-gfx] [PATCH igt] igt/gem_ctx_isolation: Fix checking for context support

Chris Wilson writes: > Missed the new method for igt_require(gem_has_contexts()) in the rebase. > > Signed-off-by: Chris Wilson > --- > tests/gem_ctx_isolation.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c > inde

Re: [Intel-gfx] [PATCH 26/43] drm/i915: Define Intel HDCP2.2 registers

On Wed, Feb 14, 2018 at 07:43:41PM +0530, Ramalingam C wrote: > Intel HDCP2.2 registers are defined with addr offsets and bit details. > > Macros are defined for referencing the register offsets based on the > port index. > > Signed-off-by: Ramalingam C > --- > drivers/gpu/drm/i915/i915_reg.h |

Re: [Intel-gfx] [PATCH 24/43] drm/i915: wait for cp_irq

On Wed, Feb 14, 2018 at 07:43:39PM +0530, Ramalingam C wrote: > DP HDCP asserts the CP_IRQ to indicate the msg availability and > auth state change at the panel. > > Implements a completion structure to communicate the cp_irq > assertion and provides a function to wait for cp_irq with a timeout. >

[Intel-gfx] ✗ Fi.CI.IGT: failure for lib/dummyload: Avoid assertions in lowlevel spin constructor

== Series Details == Series: lib/dummyload: Avoid assertions in lowlevel spin constructor URL : https://patchwork.freedesktop.org/series/38753/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race-interruptible: fail -> PASS (shard-hs

Re: [Intel-gfx] [v4] drm/i915: Fix Limited Range Color Handling

On Tue, Jan 30, 2018 at 09:21:29PM +0530, Uma Shankar wrote: > From: Johnson Lin > > Some panels support limited range output (16-235) compared > to full range RGB values (0-255). Also userspace can control > the RGB range using "Broadcast RGB" property. Currently the > code to handle full range

Re: [Intel-gfx] [PATCH v3 3/6] drm/i915: Clean up fbc vs. plane checks

On Thu, Feb 22, 2018 at 04:07:53PM +0200, Ville Syrjälä wrote: > On Wed, Feb 21, 2018 at 09:59:27PM +, Chris Wilson wrote: > > Quoting Ville Syrjala (2018-02-21 17:31:01) > > > From: Ville Syrjälä > > > > > > Let's record the information whether a plane can do fbc or not under > > > struct in

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

On Tue, Feb 20, 2018 at 11:31:09AM -0800, Rodrigo Vivi wrote: > On Tue, Feb 20, 2018 at 07:05:22PM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Since we no longer have a 1:1 correspondence between ports and AUX > > channels, let's give AUX channels their own enum. Makes it easier >

[Intel-gfx] [PATCH] drm/i915: Update missing parts after the rename to i915_request

Mostly doc/print messages that were not updated after commit e61e0f51ba79 ("drm/i915: Rename drm_i915_gem_request to i915_request"). Signed-off-by: Michel Thierry Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.h | 2 +- drivers/gpu/drm/i915/i915_request.c | 4 +

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Move page sizes out of the 8-bit sandwich

== Series Details == Series: drm/i915: Move page sizes out of the 8-bit sandwich URL : https://patchwork.freedesktop.org/series/38764/ State : failure == Summary == Test kms_vblank: Subgroup pipe-a-ts-continuation-suspend: pass -> INCOMPLETE (shard-hsw) fdo#103540

Re: [Intel-gfx] [PATCH v3 06/10] pwm: add PWM modes

On Thu, Feb 22, 2018 at 2:01 PM, Claudiu Beznea wrote: > Add PWM normal and complementary modes. > +- PWM_DTMODE_COMPLEMENTARY: PWM complementary working mode (for PWM > +channels two outputs); if not specified, the default for PWM channel will > +be used What DT stands for? -- With Best Regar

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure

On Wed, 21 Feb 2018 09:27:51 +0100, Chris Wilson wrote: Quoting Michal Wajdeczko (2018-02-20 22:57:10) Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure") we believed that we correctly handle all errors encountered during GuC initialization, including special one that indi

Re: [Intel-gfx] [PATCH] drm/i915: Update missing parts after the rename to i915_request

Quoting Michel Thierry (2018-02-22 17:24:05) > Mostly doc/print messages that were not updated after commit e61e0f51ba79 > ("drm/i915: Rename drm_i915_gem_request to i915_request"). > > Signed-off-by: Michel Thierry > Cc: Chris Wilson > --- > drivers/gpu/drm/i915/i915_gem_context.h | 2

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Update missing parts after the rename to i915_request

== Series Details == Series: drm/i915: Update missing parts after the rename to i915_request URL : https://patchwork.freedesktop.org/series/38794/ State : success == Summary == Series 38794v1 drm/i915: Update missing parts after the rename to i915_request https://patchwork.freedesktop.org/api/

[Intel-gfx] [PATCH v14 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu

Now that we have that information in topology fields, let's just reuse it. v2: Style tweaks (Tvrtko) Signed-off-by: Lionel Landwerlin Reviewed-by: Tvrtko Ursulin Acked-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 27 +++ drivers/gpu/drm/i915/intel_de

[Intel-gfx] [PATCH v14 6/6] drm/i915: expose rcs topology through query uAPI

With the introduction of asymmetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate numbers. This is essential for monitoring parts o

[Intel-gfx] [PATCH v14 5/6] drm/i915: add query uAPI

There are a number of information that are readable from hardware registers and that we would like to make accessible to userspace. One particular example is the topology of the execution units (how are execution units grouped in subslices and slices and also which ones have been fused off for die

[Intel-gfx] [PATCH v14 1/6] drm/i915: store all subslice masks

Up to now, subslice mask was assumed to be uniform across slices. But starting with Cannonlake, slices can be asymmetric (for example slice0 has different number of subslices as slice1+). This change stores all subslices masks for all slices rather than having a single mask that applies to all slic

[Intel-gfx] [PATCH v14 4/6] drm/i915: add rcs topology to error state

This might be useful information for developers looking at an error state. v2: Place topology towards the end of the error state (Chris) v3: Reuse common printing code (Michal) v4: Make this a one-liner (Chris) Signed-off-by: Lionel Landwerlin Reviewed-by: Tvrtko Ursulin Acked-by: Chris Wilso

[Intel-gfx] [PATCH v14 0/6] drm/i915: expose RCS topology to userspace

Hi all, This iteration has 2 main changes : - Joonas wanted to have stride fields into the drm_i915_query_topology_info, so the layout has changed a bit. Tvrtko also suggested alignment stuff. - In commit b8ec759e6f1c6da0418238df066a0f1ef8fd2075 I added slice/subslice mask reporting f

[Intel-gfx] [PATCH v14 3/6] drm/i915/debugfs: add rcs topology entry

While the end goal is to make this information available to userspace through a new ioctl, there is no reason we can't display it in a human readable fashion through debugfs. slice0: 3 subslice(s) (0x7): subslice0: 8 EUs (0xff) subslice1: 8 EUs (0xff) subslice2: 8 EUs (0xff

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: expose RCS topology to userspace

== Series Details == Series: drm/i915: expose RCS topology to userspace URL : https://patchwork.freedesktop.org/series/38801/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: store all subslice masks Okay! Commit: drm/i915/debugfs: reuse max slice/subslices already

[Intel-gfx] [PATCH 2/8] drm/i915: Add enum aux_ch and clean up the aux init to use it

From: Ville Syrjälä Since we no longer have a 1:1 correspondence between ports and AUX channels, let's give AUX channels their own enum. Makes it easier to tell the apples from the oranges, and we get rid of the port E AUX power domain FIXME since we now derive the power domain from the actual AU

[Intel-gfx] [PATCH 7/8] drm/i915: Keep the AKSV details in intel_dp_hdcp_write_an_aksv()

From: Ville Syrjälä Let's try to keep the details on the AKSV stuff concentrated in one place. So move the control bit and +5 data size handling there. Cc: Sean Paul Cc: Ramalingam C Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 42 +--

[Intel-gfx] [PATCH 5/8] drm/i915: Consult aux_ch instead of port in ->get_aux_clock_divider()

From: Ville Syrjälä While it seems totally unlikely that any system would mix a cpu/north aux channel with a pch/south port (or vice versa) we should still consult intel_dp->aux_ch rather than encoder->port when figuring out which clock is actually used by the aux ch. Signed-off-by: Ville Syrjäl

[Intel-gfx] [PATCH 6/8] drm/i915: s/intel_dp_aux_ch/intel_dp_aux_xfer/

From: Ville Syrjälä Rename intel_dp_aux_ch() to intel_dp_aux_xfer() to better convey what it actually does. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/

[Intel-gfx] [PATCH 8/8] drm/i915: Deduplicate the code to fill the aux message header

From: Ville Syrjälä We have two instances of the code to fill out the header for the aux message. Pull it into a small helper. Cc: Sean Paul Cc: Ramalingam C Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 32 1 file changed, 20 insertions(

[Intel-gfx] [PATCH 4/8] drm/i915: Collect aux ch vfunc setup into intel_dp_aux_init()

From: Ville Syrjälä Collect all the aux ch vfunc assignments into intel_dp_aux_init() instead of having it spread around. Reviewed-by: Chris Wilson Reviewed-by: Rodrigo Vivi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 53 +++-- 1 fil

[Intel-gfx] [PATCH 3/8] drm/i915: Nuke aux regs from intel_dp

From: Ville Syrjälä Just store function pointers that give us the correct register offsets instead of storing the register offsets themselves. Slightly less efficient perhaps but saves a few bytes and better matches how we do things elsewhere. v2: Keep a local array of data registers (Chris) Re

[Intel-gfx] [PATCH 1/8] drm/i915: Use the correct power domain for aux ch

From: Ville Syrjälä Select the aux power domain based on the aux ch rather than based on the port. Now we can rid ourselves of the port E FIXME as well. v2: Split from the enum aux_ch patch (Rodrigo) Reviewed-by: Rodrigo Vivi #v1 Reviewed-by: Chris Wilson #v1 Signed-off-by: Ville Syrjälä ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: expose RCS topology to userspace

== Series Details == Series: drm/i915: expose RCS topology to userspace URL : https://patchwork.freedesktop.org/series/38801/ State : success == Summary == Series 38801v1 drm/i915: expose RCS topology to userspace https://patchwork.freedesktop.org/api/1.0/series/38801/revisions/1/mbox/ Test g

Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: New power domain for AUX IO.

On Thu, Feb 22, 2018 at 12:28:11PM +0200, Imre Deak wrote: > On Wed, Feb 21, 2018 at 11:28:56PM -0800, Dhinakaran Pandiyan wrote: > > PSR on CNL requires AUX IO wells to be kept on and the existing AUX domain > > for AUX-A enables DC_OFF well too. This is not required, so add a new > > AUX_IO_A dom

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/8] drm/i915: Use the correct power domain for aux ch

== Series Details == Series: series starting with [1/8] drm/i915: Use the correct power domain for aux ch URL : https://patchwork.freedesktop.org/series/38802/ State : failure == Summary == Series 38802v1 series starting with [1/8] drm/i915: Use the correct power domain for aux ch https://pa

Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: New power domain for AUX IO.

On Wed, Feb 21, 2018 at 11:28:56PM -0800, Dhinakaran Pandiyan wrote: > PSR on CNL requires AUX IO wells to be kept on and the existing AUX domain > for AUX-A enables DC_OFF well too. This is not required, so add a new > AUX_IO_A domain for AUX-A to allow DC states to remain enabled. Other AUX > cha

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza wrote: > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it > self, so lets use the mutex register that is available in gen9+ to > avoid concurrent access by hardware and driver. > > Reference: > https://01.org/sites

[Intel-gfx] [PATCH] drm/i915/uc: Start preparing GuC/HuC for reset

Right after GPU reset there will be a small window of time during which some of GuC/HuC fields will still show state before reset. Let's start to fix that by sanitizing firmware status as we will use it shortly. Suggested-by: Daniele Ceraolo Spurio Signed-off-by: Michal Wajdeczko Cc: Daniele Cer

Re: [Intel-gfx] [PATCH v14 0/6] drm/i915: expose RCS topology to userspace

I forgot to add the series that require this change in Mesa : https://patchwork.freedesktop.org/series/38795/ On 22/02/18 17:53, Lionel Landwerlin wrote: Hi all, This iteration has 2 main changes : - Joonas wanted to have stride fields into the drm_i915_query_topology_info, so the layou

Re: [Intel-gfx] [PATCH] drm/i915/uc: Start preparing GuC/HuC for reset

On 22/02/18 10:45, Michal Wajdeczko wrote: Right after GPU reset there will be a small window of time during which some of GuC/HuC fields will still show state before reset. Let's start to fix that by sanitizing firmware status as we will use it shortly. Suggested-by: Daniele Ceraolo Spurio S

[Intel-gfx] [PATCH] drm/i915: Disable SAGV on pre plane update.

According to Spec "Requirement before plane enabling or configuration change: Disable SAGV if any enabled plane will not be able to enable watermarks for memory latency >= SAGV block time, or any transcoder is interlaced. Else, enable SAGV." Currently we are only enabling and disabling SAGV on ful

  1   2   >