== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation. (rev3)
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Series 37325v3 drm/i915/icl: remove port A/E lane sharing limitation.
https://patchwork.freedesktop.org/api/1.0/series/
Hi guys:
Here are the latest gvt-next-fixes pull. It contains vGPU reset
enhancement, which refines vGPU reset flow and the support of virtual
aperture read/write when x-no-mmap=on is set in KVM, which is required
by a test case from Redhat and also another fix for virtual OpRegion.
Thank
Quoting Rafael Antognolli (2018-02-05 23:33:30)
> This workaround should prevent a bug that can be hit on a context
> restore. To avoid the issue, we must emit a PIPE_CONTROL with CS stall
> (0x7a04 0x0010 0x 0x) followed by 12DW's of
> NOOP(0x0) in the indirect context batc
== Series Details ==
Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev2)
URL : https://patchwork.freedesktop.org/series/37575/
State : success
== Summary ==
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-atomic:
fail -> PASS (shard-hsw) fd
Regards
Shashank
On 2/2/2018 7:30 PM, Ville Syrjälä wrote:
On Fri, Feb 02, 2018 at 11:38:07AM +0530, Sharma, Shashank wrote:
Thanks for the comments, mine inline.
Regards
Shashank
On 2/2/2018 12:39 AM, Ville Syrjälä wrote:
On Tue, Jan 30, 2018 at 03:05:57PM +0530, Shashank Sharma wrote:
Fr
Regards
Shashank
On 2/2/2018 7:22 PM, Ville Syrjälä wrote:
On Fri, Feb 02, 2018 at 11:44:01AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 2/2/2018 12:39 AM, Ville Syrjälä wrote:
On Tue, Jan 30, 2018 at 03:06:03PM +0530, Shashank Sharma wrote:
From: "Sharma, Shashank"
LSPCON chip
When a request is preempted, it is unsubmitted from the HW queue and
removed from the active list of breadcrumbs. In the process, this
however triggers the signaler and it may see the clear rbtree with the
old, and still valid, seqno. This confuses the signaler into action and
signaling the fence.
When a request is preempted, it is unsubmitted from the HW queue and
removed from the active list of breadcrumbs. In the process, this
however triggers the signaler and it may see the clear rbtree with the
old, and still valid, seqno. This confuses the signaler into action and
signaling the fence.
The goal here is to try and reduce the latency of signaling additional
requests following the wakeup from interrupt by reducing the list of
to-be-signaled requests from an rbtree to a sorted linked list. The
original choice of using an rbtree was to facilitate random insertions
of request into the
When parking the engines and their breadcrumbs, if we have waiters left
then they missed their wakeup. Verify that each waiter's seqno did
complete.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation. (rev3)
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Test gem_eio:
Subgroup in-flight-contexts:
pass -> DMESG-WARN (shard-snb) fdo#104058
Test
== Series Details ==
Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)
URL : https://patchwork.freedesktop.org/series/37575/
State : success
== Summary ==
Series 37575v4 drm/i915/pmu: Fix PMU enable vs execlists tasklet race
https://patchwork.freedesktop.org/api/1.0/series/
Quoting Chris Wilson (2018-02-06 09:46:33)
> When a request is preempted, it is unsubmitted from the HW queue and
> removed from the active list of breadcrumbs. In the process, this
> however triggers the signaler and it may see the clear rbtree with the
> old, and still valid, seqno. This confuses
Quoting Jackie Li (2018-02-06 00:02:38)
> diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c
> b/drivers/gpu/drm/i915/intel_guc_ads.c
> index ac62753..7215594 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ads.c
> @@ -113,17 +113,6 @@ int intel_guc_ads_cr
== Series Details ==
Series: drm/i915/breadcrumbs: Ignore unsubmitted signalers
URL : https://patchwork.freedesktop.org/series/37724/
State : success
== Summary ==
Series 37724v1 drm/i915/breadcrumbs: Ignore unsubmitted signalers
https://patchwork.freedesktop.org/api/1.0/series/37724/revisions
Quoting Jackie Li (2018-02-06 00:02:41)
> +static inline bool __reg_locked(struct drm_i915_private *dev_priv,
> + i915_reg_t reg)
> +{
> + /* Explicitly cast the return value to bool. */
You already did by using bool.
> + return !!(I915_READ(reg) & GUC_WO
== Series Details ==
Series: series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted
signalers
URL : https://patchwork.freedesktop.org/series/37725/
State : failure
== Summary ==
Series 37725v1 series starting with [1/3] drm/i915/breadcrumbs: Ignore
unsubmitted signalers
https://
== Series Details ==
Series: drm/i915: pch detection refactoring
URL : https://patchwork.freedesktop.org/series/37673/
State : warning
== Summary ==
Series 37673v1 drm/i915: pch detection refactoring
https://patchwork.freedesktop.org/api/1.0/series/37673/revisions/1/mbox/
Test debugfs_test:
From: Chandra Konduru
Display WA #0827:
Switching the plane format from NV12 to RGB and leaving system idle results
in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b
in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane is enabled.
Signed-off-by: Chandra Konduru
S
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_atomic.c | 5 ++---
drivers/gpu/drm/i915/intel_display.c | 7 ++-
drivers/gpu/drm/i915/intel_sprite.c | 4
3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 24 +---
drivers/gpu/drm/i915/intel_sprite.c | 12 +---
include/uapi/drm/drm_fourcc.h| 3 +++
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 42 +++-
drivers/gpu/drm/i915/intel_sprite.c | 7 +-
include/uapi/drm/drm_fourcc.h|
== Series Details ==
Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)
URL : https://patchwork.freedesktop.org/series/37575/
State : success
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-scndscrn-cur-indfb-move:
skip -> PASS
On 06/02/2018 09:51, Patchwork wrote:
== Series Details ==
Series: drm/i915/pmu: Fix PMU enable vs execlists tasklet race (rev4)
URL : https://patchwork.freedesktop.org/series/37575/
State : success
== Summary ==
Series 37575v4 drm/i915/pmu: Fix PMU enable vs execlists tasklet race
https://
== Series Details ==
Series: drm/i915: Display WA #0827 for NV12 to RGB switch (rev4)
URL : https://patchwork.freedesktop.org/series/37729/
State : failure
== Summary ==
Applying: YUV444 10/12/16 bit declarations and additions
error: Failed to merge in the changes.
Using index info to reconstr
Apparently using the manual Maud/Naud mode does not work on KBL. The
details on the failure mode are scarce, except that there's no audio,
and there is obviously no idea on the root cause either. It is also
unknown whether the failure can be reproduced on newer platforms in some
scenarios.
The pro
On Tue, Feb 06, 2018 at 04:36:42PM +0530, Vidya Srinivas wrote:
> From: Chandra Konduru
>
> Display WA #0827:
> Switching the plane format from NV12 to RGB and leaving system idle results
> in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b
> in the CLKGATE_DIS_PSL register for
== Series Details ==
Series: drm/i915/audio: do not set Maud/Naud values manually on KBL
URL : https://patchwork.freedesktop.org/series/37730/
State : success
== Summary ==
Series 37730v1 drm/i915/audio: do not set Maud/Naud values manually on KBL
https://patchwork.freedesktop.org/api/1.0/seri
== Series Details ==
Series: drm/i915/breadcrumbs: Ignore unsubmitted signalers
URL : https://patchwork.freedesktop.org/series/37724/
State : warning
== Summary ==
Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS (shard-snb) fdo#104058
Test kms_flip:
S
From: Mahesh Kumar
NV12 formats have two registers for DDB. Verify both the registers for
NV12 during verify_wm_state.
v2: Addressed review comments by Maarten.
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/in
From: Mahesh Kumar
This will reduce number of arguments required to be passed in
skl_compute_plane_wm function.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 157 ++---
From: Mahesh Kumar
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
v2: Addressed review comments by Maarten
v3: Rebased and addressed r
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 54 +++
This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Previous revision history:
The first version of patches were reviewed when floated b
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments
From: Mahesh Kumar
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable late
From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: M
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offs
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.
From: Mahesh Kumar
This will reduce number of arguments required to be passed in
skl_compute_plane_wm function.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.
From: Mahesh Kumar
NV12 formats have two registers for DDB. Verify both the registers for
NV12 during verify_wm_state.
v2: Addressed review comments by Maarten.
Signed-off-by: Mahesh Kumar
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/in
From: Mahesh Kumar
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 54 +++
From: Mahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl
This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Previous revision history:
The first version of patches were reviewed when floated b
From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max
From: Mahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar
From: Mahesh Kumar
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
v2: Addressed review comments by Maarten
v3: Rebased and addressed r
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: M
From: Mahesh Kumar
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable late
From: Mahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 157 ++---
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offs
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
Quoting Chris Wilson (2018-02-02 21:15:09)
> Quoting Ville Syrjala (2018-02-02 20:42:52)
> > From: Ville Syrjälä
> >
> > SKL reintroduced plane scaling once more. Let's try to make use of it.
> >
> > The one annoying caveat is that you can't do colorkeying and scaling at
> > the same time :( Fo
== Series Details ==
Series: series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted
signalers
URL : https://patchwork.freedesktop.org/series/37725/
State : success
== Summary ==
Series 37725v1 series starting with [1/3] drm/i915/breadcrumbs: Ignore
unsubmitted signalers
https://
Sorry, my bad. This was a wrong push from my end. I have changed the tag to Not
applicable.
Apologies.
Have sent out the NV12 series separately.
Regards
Vidya
> -Original Message-
> From: David Weinehall [mailto:david.weineh...@linux.intel.com]
> Sent: Tuesday, February 6, 2018 5:34 PM
Hi,
On 02-02-18 17:13, Ville Syrjälä wrote:
On Mon, Jan 29, 2018 at 03:47:34PM +0100, Hans de Goede wrote:
Add a new intel_bios_cleanup function to free memdup-ed bios data
structures and call it from i915_driver_unload().
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/i915_drv.c |
== Series Details ==
Series: drm/i915/audio: do not set Maud/Naud values manually on KBL
URL : https://patchwork.freedesktop.org/series/37730/
State : success
== Summary ==
Test perf:
Subgroup enable-disable:
fail -> PASS (shard-apl) fdo#103715
Subgr
== Series Details ==
Series: Adding NV12 support (rev8)
URL : https://patchwork.freedesktop.org/series/28103/
State : warning
== Summary ==
Series 28103v8 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/8/mbox/
Test gem_mmap_gtt:
Subgroup basic-sma
Hey,
Op 06-02-18 om 12:06 schreef Vidya Srinivas:
> From: Chandra Konduru
>
> Display WA #0827:
> Switching the plane format from NV12 to RGB and leaving system idle results
> in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b
> in the CLKGATE_DIS_PSL register for the pipe in w
== Series Details ==
Series: series starting with [1/3] drm/i915/breadcrumbs: Ignore unsubmitted
signalers
URL : https://patchwork.freedesktop.org/series/37725/
State : success
== Summary ==
Test perf:
Subgroup buffer-fill:
fail -> PASS (shard-apl) fdo#1037
Make intel_bios_cleanup function free the DSI VBT data structures which
are memdup-ed by parse_mipi_config() and parse_mipi_sequence().
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_bios.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
index = 3, one of which has been kindly provided to me by Jan Brummer,
where not working with the i915 driver, giving a black screen on the
first modeset.
The problem with at least these Dells is that their VBT defines a MIPI
ASSE
Add an intel_bios_cleanup() function to act as counterpart of
intel_bios_init() and move the cleanup of vbt related resources there,
putting it in the same file as the allocation.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/i915_drv.c | 14 +-
drivers/gpu/drm/i915/i915_dr
From: Tvrtko Ursulin
We are not allowed to call intel_runtime_pm_get from the PMU counter read
callback since the former can sleep, and the latter is running under IRQ
context.
To workaround this, we start our timer when we detect that we have failed
to obtain a runtime PM reference during read,
We only need to wake up the RPS worker once when initially enabling the
client boost, it remains in effect then until the last client no longer
requires the boost.
References: https://bugs.freedesktop.org/show_bug.cgi?id=102250
References: 7b92c1bd0540 ("drm/i915: Avoid keeping waitboost active fo
== Series Details ==
Series: series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup()
function
URL : https://patchwork.freedesktop.org/series/37741/
State : success
== Summary ==
Series 37741v1 series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup()
function
https://patchwor
== Series Details ==
Series: drm/i915/pmu: Fix sleep under atomic in RC6 readout
URL : https://patchwork.freedesktop.org/series/37742/
State : warning
== Summary ==
Series 37742v1 drm/i915/pmu: Fix sleep under atomic in RC6 readout
https://patchwork.freedesktop.org/api/1.0/series/37742/revisio
Hi! I'm periodically getting following message in dmesg on Lenovo
Thinkpad X1 Carbon 3rd generation:
[drm] Reducing the compressed framebuffer size. This may lead to less power
savings than a non-reduced-size. Try to increase stolen memory size if
available in BIOS.
In BIOS I already set GPU si
Em Seg, 2018-02-05 às 15:13 -0800, Ausmus, James escreveu:
> On Mon, Feb 05, 2018 at 01:40:42PM -0200, Paulo Zanoni wrote:
> > This commit adds the basic CDCLK functions, but it's still missing
> > pieces of the display initialization sequence.
> >
> > v2:
> > - Implement the voltage levels.
> >
== Series Details ==
Series: drm/i915: Remove superfluous worker wakeups when RPS is already boosted
URL : https://patchwork.freedesktop.org/series/37743/
State : success
== Summary ==
Series 37743v1 drm/i915: Remove superfluous worker wakeups when RPS is already
boosted
https://patchwork.fre
== Series Details ==
Series: series starting with [v4,1/3] drm/i915: Add intel_bios_cleanup()
function
URL : https://patchwork.freedesktop.org/series/37741/
State : warning
== Summary ==
Test gem_exec_schedule:
Subgroup reorder-wide-vebox:
incomplete -> PASS (sha
Quoting dom.const...@free.fr (2018-02-02 18:37:12)
> Hello,
>
> For my HTPC setup, I'm using the option "CustomEDID".
> With this option, output attaching and destroying events leads to crashes.
>
> The following sequence leads to a crash:
> - In xorg.conf: Option "CustomEDID" "HDMI2:/etc/my_edi
Quoting Tvrtko Ursulin (2018-02-06 14:31:07)
> +static u64 read_rc6_residency(struct drm_i915_private *i915)
> +{
> + u64 val;
> +
> + val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
> + VLV_GT_RENDER_RC6 :
> GEN6_GT_GFX_RC6);
> +
On Tue, Feb 06, 2018 at 04:04:10PM +, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-06 14:31:07)
> > +static u64 read_rc6_residency(struct drm_i915_private *i915)
> > +{
> > + u64 val;
> > +
> > + val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
> > +
On 03/02/18 02:33, Chris Wilson wrote:
Apply a random load to one or all engines in order to apply stress to
RPS as it tries to constantly adjust the GPU frequency to meet the
changing workload.
This can be used to reproduce the byt (j1900) system hang.
v2: igt_until_timeout
Signed-off-by: C
== Series Details ==
Series: drm/i915: Remove superfluous worker wakeups when RPS is already boosted
URL : https://patchwork.freedesktop.org/series/37743/
State : success
== Summary ==
Test perf:
Subgroup oa-exponents:
pass -> FAIL (shard-apl) fdo#102254
On 06/02/2018 16:10, Imre Deak wrote:
On Tue, Feb 06, 2018 at 04:04:10PM +, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-02-06 14:31:07)
+static u64 read_rc6_residency(struct drm_i915_private *i915)
+{
+ u64 val;
+
+ val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
Quoting Chris Wilson (2018-02-06 09:46:33)
> When a request is preempted, it is unsubmitted from the HW queue and
> removed from the active list of breadcrumbs. In the process, this
> however triggers the signaler and it may see the clear rbtree with the
> old, and still valid, seqno. This confuses
FORCEWAKE_ACK is depricated by BSpec at least starting from BDW,
referring to the multi-threaded version of it instead. Accessing
FORCEWAKE_ACK triggers an unclaimed register access error - at
least on GLK - see the Reference: below.
As opposed to this debugfs file we normally use the MT version o
From: Tvrtko Ursulin
We are not allowed to call intel_runtime_pm_get from the PMU counter read
callback since the former can sleep, and the latter is running under IRQ
context.
To workaround this, we record the last known RC6 and while runtime
suspended estimate its increase by querying the runt
On Tue, Feb 06, 2018 at 11:49:18AM +, Jani Nikula wrote:
> Apparently using the manual Maud/Naud mode does not work on KBL. The
> details on the failure mode are scarce, except that there's no audio,
> and there is obviously no idea on the root cause either. It is also
> unknown whether the fai
== Series Details ==
Series: series starting with [01/10] drm/vblank: Data type fixes for 64-bit
vblank sequences.
URL : https://patchwork.freedesktop.org/series/37598/
State : success
== Summary ==
Series 37598v1 series starting with [01/10] drm/vblank: Data type fixes for
64-bit vblank seq
> Quoting dom.const...@free.fr (2018-02-02 18:37:12)
> > Hello,
> >
> > For my HTPC setup, I'm using the option "CustomEDID".
> > With this option, output attaching and destroying events leads to
> > crashes.
> >
> > The following sequence leads to a crash:
> > - In xorg.conf: Option "CustomEDI
== Series Details ==
Series: drm/i915/ivb+: Use the correct render forcewake ACK register
URL : https://patchwork.freedesktop.org/series/37753/
State : success
== Summary ==
Series 37753v1 drm/i915/ivb+: Use the correct render forcewake ACK register
https://patchwork.freedesktop.org/api/1.0/se
== Series Details ==
Series: drm/i915/pmu: Fix sleep under atomic in RC6 readout (rev2)
URL : https://patchwork.freedesktop.org/series/37742/
State : success
== Summary ==
Series 37742v2 drm/i915/pmu: Fix sleep under atomic in RC6 readout
https://patchwork.freedesktop.org/api/1.0/series/37742/
This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.
v2:
- Implement the voltage levels.
- Rebase.
v3:
- Adjust to the new "bypass" clock (Imre).
- Call intel_dump_cdclk_state() too.
- Rename a variable to avoid confusion.
- Simpli
Hi Zhi,
Daniel asked few weeks ago about the scripts that you run there,
but I didn't see any follow-up.
I don't understand why yet, but apparently gvt pull request
is not going to patchwork so dim is not able to add the "Link:"
hence end up without mandatory patchwork links.
Last round I by-pa
== Series Details ==
Series: drm/i915/ivb+: Use the correct render forcewake ACK register
URL : https://patchwork.freedesktop.org/series/37753/
State : success
== Summary ==
Test gem_exec_schedule:
Subgroup reorder-wide-vebox:
incomplete -> PASS (shard-apl) fdo#10
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