On Mon, Dec 04, 2017 at 03:22:10PM -0800, Lucas De Marchi wrote:
> Display WA #1183 was recently added to workaround
> "Failures when enabling DPLL0 with eDP link rate 2.16
> or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz
> (CDCLK_CTL CD Frequency Select 10b or 11b) used in this
> enablin
== Series Details ==
Series: drm/i915: Fix up the CCS code (rev2)
URL : https://patchwork.freedesktop.org/series/29308/
State : success
== Summary ==
Series 29308v2 drm/i915: Fix up the CCS code
https://patchwork.freedesktop.org/api/1.0/series/29308/revisions/2/mbox/
Test gem_mmap_gtt:
This one works for me. Loads faster but identical output to the original
version.
Reviewed-by: John Harrison
On 12/22/2017 1:16 AM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
A couple of small optimizations which altogether bring around 30%
improvement in my testing.
1. Do less string pr
Hi Ville,Given you've tested, my reservations are dropped, so this series is:Acked-by: Daniel Stone Sorry for the mobile client formatting.Cheers,Daniel___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listin
Hi all,
This is the last one for 4.16.
The following changes tagged drm-intel-testing-2017-12-22:
Since I intend to immediately propagate that to Dave,
For the reference on testing, this was tested with CI
on https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3570/
drm-intel-next-2017-12-22:
- All
On Fri, Dec 22, 2017 at 08:28:55PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> During hpd processing we may want to do things both before and
> after the display detection. To that end split the encoder->hot_plug()
> hooks.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i91
On Fri, 2017-12-22 at 21:58 +0200, Ville Syrjälä wrote:
> On Mon, Dec 04, 2017 at 03:22:10PM -0800, Lucas De Marchi wrote:
> > Display WA #1183 was recently added to workaround
> > "Failures when enabling DPLL0 with eDP link rate 2.16
> > or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz
> >
On Fri, Dec 22, 2017 at 09:06:28PM +, De Marchi, Lucas wrote:
> On Fri, 2017-12-22 at 21:58 +0200, Ville Syrjälä wrote:
> > On Mon, Dec 04, 2017 at 03:22:10PM -0800, Lucas De Marchi wrote:
> > > Display WA #1183 was recently added to workaround
> > > "Failures when enabling DPLL0 with eDP link
Forward Error Correction is supported on DP 1.4.
This patch adds corresponding DPCD register definitions.
v2: Add dri-devel mailing list to the CC list(Jani)
v3: Change names, add missing masks (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Si
On Fri, Dec 22, 2017 at 08:28:57PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Doing link reatrining from the short pulse handler is problematic since
> that might introduce deadlocks with MST sideband processing. Currently
> we don't retrain MST links from this code, but we want to cha
When we require GEM, reset the global seqno. This gives each test a
clean slate to work with, and avoids left-over state from previous tests
impacting on the next. In particular, somes tests may be setting up long
sequence of stalling batches not expecting to hit a seqno wraparound
(leftover from,
Different GENs have a different ACK register. Use the correct
one for each case.
Suggested-by: Paulo Zanoni
Signed-off-by: Oscar Mateo
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/d
This register does not contain it. Instead, we have to look into
FAULT_TLB_DATA0 & 1
(where, by the way, we can also get the address space).
Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8
onwards")
Signed-off-by: Oscar Mateo
Cc: Michel Thierry
Cc: Chris Wilson
---
Quoting Oscar Mateo (2017-12-22 22:10:00)
> Different GENs have a different ACK register. Use the correct
> one for each case.
>
> Suggested-by: Paulo Zanoni
> Signed-off-by: Oscar Mateo
> Cc: Sagar Arun Kamble
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 15 ++-
> 1 file changed,
On some Cannonlake SKUs we have a dedicated Aux for port F,
that is only the full split between port A and port E.
There is still no Aux E for Port E, as in previous platforms,
because port_E still means shared lanes with port A.
v2: Rebase.
v3: Add couple missed PORT_F cases on intel_dp.
v4: Reb
Some Cannonlake SKUs will come with a full split between
port A and port E. This will be called port F although it
is not a 6th port, but only a split.
v2: Fix size of dvo_ports found by Ander.
v3: Adding missing cases from intel_bios.c for Port_F
v4: Adding other missing cases and fix the commit
By the Spec all CNL skus are GT2.
v2: Really include the PCI IDs to the picidlist[];
v3: Add the PCI Id for another SKU (Anusha).
v4: Update IDs, really include to pciidlists again.
v5: Unify all GT2 IDs.
v6: Unify in a way that we don't break early-quirks.c
Cc: Lucas De Marchi
Signed-off-by: An
This was wrong since its introduction on commit '04416108ccea
("drm/i915/cnl: Add registers related to voltage swing sequences.")'
But since no Port F was needed so far we don't need to
propagate fixes back there.
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
---
drivers/g
On CNP Pin 3 is for misc of Port F usage depending on the
configuration. For CNL that uses Port F, pin 3 is the one.
v2: Make it more generic and update commit message.
Cc: Anusha Srivatsa
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_hdmi.c
SKUs that lacks on the full port F split will just time out
when touching this power well bits, causing a noisy warn.
This macro style is a deviation from the original definition in use
for other platforms, but it at least avoid code duplication.
Other smart alternatives like providing a joint lis
Since when it got introduced with commit '555e38d27317
("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
was wrong, because Port F bits are far from bits used
for A to E.
Since Port F is not used so far we don't need to propagate
Fixes back there.
Cc: Lucas De Marchi
Cc: Manasi Navare
On CNL SKUs that uses port F, max DP rate is 8.1G for all
ports when we have the elevated voltage.
v2: Make commit message more generic.
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletio
Now let's finish the Port-F support by adding the
proper port F detection, irq and power well support.
v2: Rebase
v3: Use BIT_ULL
v4: Cover missed case on ddi init.
v5: Update commit message.
Cc: Manasi Navare
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h
Let's try to simplify this mapping to hpd_pin -> bit
instead using port.
So for CNL with port F where we have this port using
hdp_pin and bits of other ports we don't need to duplicated
the mapping.
But for now this is only a re-org with no functional change
expected.
Cc: Lucas De Marchi
Suggest
On CNP boards that are using DDI F,
bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
the Digital Port F hotplug line when the Digital
Port F hotplug detect input is enabled.
v2: Reuse all existent structure instead of adding a
new HPD_PORT_F pointing to pin of port E.
v3: Use IS_CNL_WITH_PORT_F so w
Quoting Oscar Mateo (2017-12-22 22:10:29)
> This register does not contain it. Instead, we have to look into
> FAULT_TLB_DATA0 & 1
> (where, by the way, we can also get the address space).
>
> Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8
> onwards")
> Signed-off-by:
This register does not contain it. Instead, we have to look into
FAULT_TLB_DATA0 & 1
(where, by the way, we can also get the address space).
v2: Right formatting
v3:
- Use 12 (as per the register format) instead of PAGE_SIZE (Chris)
- s/BITS_44_TO_47/HIGHBITS (Chris)
- Right formatting, thi
== Series Details ==
Series: drm/i915: Fix up the CCS code (rev2)
URL : https://patchwork.freedesktop.org/series/29308/
State : warning
== Summary ==
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
Test kms_plane:
Subgroup plane-pann
== Series Details ==
Series: drm: Add DPCD definitions for DP 1.4 FEC feature (rev3)
URL : https://patchwork.freedesktop.org/series/34259/
State : success
== Summary ==
Series 34259v3 drm: Add DPCD definitions for DP 1.4 FEC feature
https://patchwork.freedesktop.org/api/1.0/series/34259/revisi
== Series Details ==
Series: drm/i915: Update forcewake ack register used in debugfs
URL : https://patchwork.freedesktop.org/series/35742/
State : failure
== Summary ==
Series 35742v1 drm/i915: Update forcewake ack register used in debugfs
https://patchwork.freedesktop.org/api/1.0/series/35742
== Series Details ==
Series: series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU.
URL : https://patchwork.freedesktop.org/series/35744/
State : failure
== Summary ==
Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
Applying: drm/i915/cnl: Add Port
-next-2017-12-22
for you to fetch changes up to cfe4982ca488016d697cf0769ae70c9a78060c0d:
drm/i915: Update DRIVER_DATE to 20171222 (2017-12-22 11:41:50 -0800)
- Allow internal page allocation to fail (Chris)
- More improvements on
On Fri, Dec 22, 2017 at 10:58:03PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for
> another SKU.
> URL : https://patchwork.freedesktop.org/series/35744/
> State : failure
>
> == Summary ==
>
> Applying: drm/i915
By the Spec all CNL skus are GT2.
v2: Really include the PCI IDs to the picidlist[];
v3: Add the PCI Id for another SKU (Anusha).
v4: Update IDs, really include to pciidlists again.
v5: Unify all GT2 IDs.
v6: Unify in a way that we don't break early-quirks.c
Cc: Lucas De Marchi
Signed-off-by: An
On CNP Pin 3 is for misc of Port F usage depending on the
configuration. For CNL that uses Port F, pin 3 is the one.
v2: Make it more generic and update commit message.
Cc: Anusha Srivatsa
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_hdmi.c
On some Cannonlake SKUs we have a dedicated Aux for port F,
that is only the full split between port A and port E.
There is still no Aux E for Port E, as in previous platforms,
because port_E still means shared lanes with port A.
v2: Rebase.
v3: Add couple missed PORT_F cases on intel_dp.
v4: Reb
Let's try to simplify this mapping to hpd_pin -> bit
instead using port.
So for CNL with port F where we have this port using
hdp_pin and bits of other ports we don't need to duplicated
the mapping.
But for now this is only a re-org with no functional change
expected.
Cc: Lucas De Marchi
Suggest
On CNL SKUs that uses port F, max DP rate is 8.1G for all
ports when we have the elevated voltage.
v2: Make commit message more generic.
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletio
Some Cannonlake SKUs will come with a full split between
port A and port E. This will be called port F although it
is not a 6th port, but only a split.
v2: Fix size of dvo_ports found by Ander.
v3: Adding missing cases from intel_bios.c for Port_F
v4: Adding other missing cases and fix the commit
== Series Details ==
Series: drm/i915: Stop getting the fault address from RING_FAULT_REG (rev2)
URL : https://patchwork.freedesktop.org/series/35743/
State : failure
== Summary ==
Series 35743v2 drm/i915: Stop getting the fault address from RING_FAULT_REG
https://patchwork.freedesktop.org/api
SKUs that lacks on the full port F split will just time out
when touching this power well bits, causing a noisy warn.
This macro style is a deviation from the original definition in use
for other platforms, but it at least avoid code duplication.
Other smart alternatives like providing a joint lis
Since when it got introduced with commit '555e38d27317
("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
was wrong, because Port F bits are far from bits used
for A to E.
Since Port F is not used so far we don't need to propagate
Fixes back there.
Cc: Lucas De Marchi
Cc: Manasi Navare
On CNP boards that are using DDI F,
bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
the Digital Port F hotplug line when the Digital
Port F hotplug detect input is enabled.
v2: Reuse all existent structure instead of adding a
new HPD_PORT_F pointing to pin of port E.
v3: Use IS_CNL_WITH_PORT_F so w
This was wrong since its introduction on commit '04416108ccea
("drm/i915/cnl: Add registers related to voltage swing sequences.")'
But since no Port F was needed so far we don't need to
propagate fixes back there.
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
---
drivers/g
Now let's finish the Port-F support by adding the
proper port F detection, irq and power well support.
v2: Rebase
v3: Use BIT_ULL
v4: Cover missed case on ddi init.
v5: Update commit message.
v6: Rebase on top of display headers rework.
Cc: Manasi Navare
Cc: Ville Syrjälä
Signed-off-by: Rodrigo
On Fri, Dec 22, 2017 at 02:02:50PM -0800, Anusha Srivatsa wrote:
> Forward Error Correction is supported on DP 1.4.
> This patch adds corresponding DPCD register definitions.
>
> v2: Add dri-devel mailing list to the CC list(Jani)
>
> v3: Change names, add missing masks (Manasi)
>
> Cc: dri-de..
== Series Details ==
Series: series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU.
URL : https://patchwork.freedesktop.org/series/35745/
State : success
== Summary ==
Series 35745v1 series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI
IDs for another SKU
== Series Details ==
Series: lib/gem: Reset the global seqno at the start of each test
URL : https://patchwork.freedesktop.org/series/35741/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
6d27acafa3a2d80b6330e2380a3548bc98dcc3e5 igt/gem_exec_await: Flush th
== Series Details ==
Series: drm: Add DPCD definitions for DP 1.4 FEC feature (rev3)
URL : https://patchwork.freedesktop.org/series/34259/
State : failure
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass -> FAIL
Since the firmwares are released yet to public repo,
disable them on Geminilake.
v2: Remove the firmware versions (Michal)
Cc: Michal Wajdeczko
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 4
drivers/gpu/drm/i915/intel_huc.c| 4
2 fil
There is a new version of DMC available for CNL.
The release notes mentions:
1. Fix for the issue where DC_STATE was getting enabled
even when disabled by driver causing data corruption
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_cs
== Series Details ==
Series: series starting with [01/11] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU.
URL : https://patchwork.freedesktop.org/series/35745/
State : warning
== Summary ==
Test kms_flip:
Subgroup dpms-vs-vblank-race-interruptible:
pass ->
== Series Details ==
Series: drm/i915/glk: Disable Guc and HuC on GLK (rev3)
URL : https://patchwork.freedesktop.org/series/35381/
State : success
== Summary ==
Series 35381v3 drm/i915/glk: Disable Guc and HuC on GLK
https://patchwork.freedesktop.org/api/1.0/series/35381/revisions/3/mbox/
Tes
== Series Details ==
Series: drm/i915/dmc: DMC 1.07 for Cannonlake (rev2)
URL : https://patchwork.freedesktop.org/series/35651/
State : success
== Summary ==
Series 35651v2 drm/i915/dmc: DMC 1.07 for Cannonlake
https://patchwork.freedesktop.org/api/1.0/series/35651/revisions/2/mbox/
Test gem_
== Series Details ==
Series: lib/gem: Reset the global seqno at the start of each test
URL : https://patchwork.freedesktop.org/series/35741/
State : failure
== Summary ==
Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS (shard-snb) fdo#104058
Test perf:
== Series Details ==
Series: drm/i915/glk: Disable Guc and HuC on GLK (rev3)
URL : https://patchwork.freedesktop.org/series/35381/
State : success
== Summary ==
Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS (shard-snb) fdo#104058
Test pm_rc6_residency:
== Series Details ==
Series: drm/i915/dmc: DMC 1.07 for Cannonlake (rev2)
URL : https://patchwork.freedesktop.org/series/35651/
State : success
== Summary ==
Test kms_flip:
Subgroup vblank-vs-dpms-suspend-interruptible:
pass -> SKIP (shard-snb) fdo#102365
Te
101 - 157 of 157 matches
Mail list logo
