GEN6_RC_VIDEO_FREQ is deprecated for >= gen10;
don't try to program it.
v2: Use IS_GEN9() instead of INTEL_GEN() and remove comment (Rodrigo)
Signed-off-by: David Weinehall
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-
== Series Details ==
Series: drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2)
URL : https://patchwork.freedesktop.org/series/33608/
State : success
== Summary ==
Series 33608v2 drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+
https://patchwork.freedesktop.org/api/1.0/series/33608/revisi
On Thu, Nov 16, 2017 at 08:24:02PM +0200, David Weinehall wrote:
> On Wed, Nov 08, 2017 at 04:25:42PM +0200, David Weinehall wrote:
> > On Tue, Nov 07, 2017 at 05:18:21PM +0100, Daniel Vetter wrote:
> > > Now that we have CI, and that pm_rpm fully passes (I guess the audio
> > > folks have implemen
== Series Details ==
Series: drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+ (rev2)
URL : https://patchwork.freedesktop.org/series/33608/
State : warning
== Summary ==
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail -> PASS (shard-hsw) fd
On 16/11/2017 16:00, Lionel Landwerlin wrote:
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't aggregate numbers.
This is essential for monitoring parts
On 16/11/2017 16:00, Lionel Landwerlin wrote:
This enables userspace to discover the engines available on the GPU.
Here is the layout :
/sys/devices/pci:00/:00:02.0/drm/card0/engines
├── bcs0
│ ├── class
│ └── instance
├── rcs0
│ ├── class
│ └── instance
├── vcs0
│ ├── class
│
Quoting Jani Nikula (2017-11-17 07:44:08)
> On Thu, 16 Nov 2017, Rodrigo Vivi wrote:
> > On Thu, Nov 16, 2017 at 09:22:23AM +, Jani Nikula wrote:
> >> On Wed, 15 Nov 2017, Chris Wilson wrote:
> >> > Quoting David Weinehall (2017-11-15 18:01:41)
> >> >> On Tue, Nov 14, 2017 at 01:51:16PM +
On Fri, 17 Nov 2017, Chris Wilson wrote:
> That seems like a reasonably policy.
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 57dfaf04d819..0be79cf993fa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -833,6 +
If we can not run the drunk_hole test because we couldn't allocate the
memory for the permutation array (even after we tried trimming the
size), report a clear ENOMEM. Similary, if we are asked to operate on a
hole too small for ourselves, make it skip quietly.
Signed-off-by: Chris Wilson
Cc: Mat
Rodrigo gave a persuasive argument for keeping workarounds: that they
serve as a good guide for the bring up of the next generation. Not only
do workarounds persist into the early revisions, they show where the
workarounds were previously added to the code flow and sometimes the old
workarounds hav
== Series Details ==
Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure
URL : https://patchwork.freedesktop.org/series/33994/
State : success
== Summary ==
Series 33994v1 drm/i915/selftests: Report ENOMEM clearly for an allocation
failure
https://patchwork.freedesktop
On 17/11/17 09:37, Tvrtko Ursulin wrote:
On 16/11/2017 16:00, Lionel Landwerlin wrote:
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't aggregate numbers
On 17/11/17 09:51, Tvrtko Ursulin wrote:
On 16/11/2017 16:00, Lionel Landwerlin wrote:
This enables userspace to discover the engines available on the GPU.
Here is the layout :
/sys/devices/pci:00/:00:02.0/drm/card0/engines
├── bcs0
│ ├── class
│ └── instance
├── rcs0
│ ├── class
Quoting Lionel Landwerlin (2017-11-16 16:00:03)
> With the introduction of asymetric slices in CNL, we cannot rely on
> the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
> way of querying the Gen's GPU topology that doesn't aggregate numbers.
>
> This is essential for monitori
== Series Details ==
Series: drm/i915: Add a policy note for removing workarounds
URL : https://patchwork.freedesktop.org/series/33995/
State : success
== Summary ==
Series 33995v1 drm/i915: Add a policy note for removing workarounds
https://patchwork.freedesktop.org/api/1.0/series/33995/revis
Quoting Michel Thierry (2017-11-16 22:06:31)
> The first test aims to check guc_init_doorbell_hw, changing the existing
> guc clients and doorbells state before calling it.
>
> The second test tries to create as many clients as it is currently possible
> (currently limited to max number of doorbel
On 14 November 2017 at 17:35, Chris Wilson wrote:
> Commit 21cc6431e0c2 ("drm/i915: Mark the userptr invalidate workqueue
> as WQ_MEM_RECLAIM") tried to fixup the check_flush_dependency warning
> for hitting i915_gem_userptr_mn_invalidate_range_start from within the
> shrinker, but I failed to no
Quoting Matthew Auld (2017-11-17 10:56:54)
> On 14 November 2017 at 17:35, Chris Wilson wrote:
> > Commit 21cc6431e0c2 ("drm/i915: Mark the userptr invalidate workqueue
> > as WQ_MEM_RECLAIM") tried to fixup the check_flush_dependency warning
> > for hitting i915_gem_userptr_mn_invalidate_range_s
Quoting Tvrtko Ursulin (2017-11-15 09:11:13)
>
> On 14/11/2017 21:56, Chris Wilson wrote:
> > We should long past the time of trying to use wait_for() from inside
> > atomic contexts, so add a might_sleep() check to prevent misuse.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> >
On 17/11/17 10:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-16 16:00:03)
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't aggregate numbers.
On Fri, 17 Nov 2017, Chris Wilson wrote:
> Rodrigo gave a persuasive argument for keeping workarounds: that they
> serve as a good guide for the bring up of the next generation. Not only
> do workarounds persist into the early revisions, they show where the
> workarounds were previously added to t
On 17 November 2017 at 10:17, Chris Wilson wrote:
> If we can not run the drunk_hole test because we couldn't allocate the
> memory for the permutation array (even after we tried trimming the
> size), report a clear ENOMEM. Similary, if we are asked to operate on a
> hole too small for ourselves,
Quoting Lionel Landwerlin (2017-11-17 11:08:07)
> On 17/11/17 10:53, Chris Wilson wrote:
> > Is this subslicing only for the render unit; are all platforms going to
> > have the same fusing across all units? At the least, I thought we would
> > be able to configure the powergating of the different
Op 13-11-17 om 18:18 schreef Ville Syrjälä:
> On Fri, Nov 10, 2017 at 12:35:00PM +0100, Maarten Lankhorst wrote:
>> Changes since v1:
>> - Only pass crtc_state, not crtc.
>>
>> Signed-off-by: Maarten Lankhorst
> Reviewed-by: Ville Syrjälä
>
Thanks, pushed this and previous patch.
Need to think a
On 17/11/17 11:17, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-17 11:08:07)
On 17/11/17 10:53, Chris Wilson wrote:
Is this subslicing only for the render unit; are all platforms going to
have the same fusing across all units? At the least, I thought we would
be able to configure the
Cc: Greg
On Wed, 15 Nov 2017, Ville Syrjälä wrote:
> On Wed, Nov 15, 2017 at 04:44:54PM +, alexander.le...@verizon.com wrote:
>> On Wed, Nov 15, 2017 at 01:08:05PM +0200, Ville Syrjälä wrote:
>> >On Wed, Nov 15, 2017 at 02:45:43AM +, alexander.le...@verizon.com wrote:
>> >> From: Ville S
On Fri, Nov 17, 2017 at 08:49:49AM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 11/16/2017 9:53 PM, Ville Syrjälä wrote:
> > On Thu, Nov 16, 2017 at 08:21:44PM +0530, Sharma, Shashank wrote:
> >> Regards
> >>
> >> Shashank
> >>
> >>
> >> On 11/13/2017 10:34 PM, Ville Syrjala wr
On Fri, Nov 17, 2017 at 08:53:54AM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 11/16/2017 9:56 PM, Ville Syrjälä wrote:
> > On Thu, Nov 16, 2017 at 08:31:36PM +0530, Sharma, Shashank wrote:
> >> Regards
> >>
> >> Shashank
> >>
> >>
> >> On 11/13/2017 10:34 PM, Ville Syrjala wr
== Series Details ==
Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure
URL : https://patchwork.freedesktop.org/series/33994/
State : success
== Summary ==
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-a:
skip -> PA
With the atomic watermark calculations calculate intermediary watermark
values and update the watermarks atomically.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel_drv.h | 5 +-
drivers/gpu/drm/i915/intel_pm.c | 241 ++
It's time to kill off the legacy watermark infrastructure. Convert the
existing watermark calculations to atomic, and remove the legacy ones.
Resend, only rebased..
Maarten Lankhorst (6):
drm/i915: Calculate gen3- watermarks semi-atomically, v3.
drm/i915: Program gen3- watermarks atomically
Gen4 watermark is handled same as gen3-. Calculate
the optimal watermarks atomically first, and program
it in the legacy helper.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 141
1 file changed, 100 insertions(+), 41 deletions(-)
Use crtc->active directly instead. This is still not completely
optimal and needs fixing, but it's about as good as using
intel_crtc_active.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 19 ---
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gp
We're already calculating the watermarks correctly, now we have to
program them too.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/
Chris Wilson writes:
> Quoting Mika Kuoppala (2017-11-16 14:00:13)
>> Chris Wilson writes:
>>
>> > During request construction, after pinning the context we know whether
>> > or not we have to emit a context switch. So move this common operation
>> > from every caller into i915_gem_request_allo
The legacy watermark infrastructure is now unused, so remove it.
Changes since v1:
- Rebase on top of legacy_cursor_update fix.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_atomic.c | 2 -
drivers/gpu/drm/i915/intel_display.c | 7
The gen3 watermark calculations are converted to atomic,
but the wm update calls are still done through the legacy
functions.
This will make it easier to bisect things if they go wrong.
CI was having issues on the kms_cursor_legacy tests with too
much debug info printed out, in order to reduce th
During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.
v2: Always submit the request if we emitted some commands during request
construction, as typically
Regards
Shashank
On 11/17/2017 5:05 PM, Ville Syrjälä wrote:
On Fri, Nov 17, 2017 at 08:49:49AM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 11/16/2017 9:53 PM, Ville Syrjälä wrote:
On Thu, Nov 16, 2017 at 08:21:44PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 11/13/2017
Quoting Patchwork (2017-11-17 11:56:31)
> == Series Details ==
>
> Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure
> URL : https://patchwork.freedesktop.org/series/33994/
> State : success
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/
== Series Details ==
Series: drm/i915: Add a policy note for removing workarounds
URL : https://patchwork.freedesktop.org/series/33995/
State : success
== Summary ==
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-varying-size:
fail -> PASS (shard-hsw) fdo#1
On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote:
>
> Cc: Greg
>
> On Wed, 15 Nov 2017, Ville Syrjälä wrote:
> > On Wed, Nov 15, 2017 at 04:44:54PM +, alexander.le...@verizon.com wrote:
> >> On Wed, Nov 15, 2017 at 01:08:05PM +0200, Ville Syrjälä wrote:
> >> >On Wed, Nov 15, 2017
On Fri, Nov 17, 2017 at 05:50:11PM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 11/17/2017 5:05 PM, Ville Syrjälä wrote:
> > On Fri, Nov 17, 2017 at 08:49:49AM +0530, Sharma, Shashank wrote:
> >> Regards
> >>
> >> Shashank
> >>
> >>
> >> On 11/16/2017 9:53 PM, Ville Syrjälä wro
On Fri, Nov 17, 2017 at 01:41:23PM +0100, Greg KH wrote:
> On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote:
> >
> > Cc: Greg
> >
> > On Wed, 15 Nov 2017, Ville Syrjälä wrote:
> > > On Wed, Nov 15, 2017 at 04:44:54PM +, alexander.le...@verizon.com
> > > wrote:
> > >> On Wed, Nov
On Fri, Nov 17, 2017 at 02:53:43PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 17, 2017 at 01:41:23PM +0100, Greg KH wrote:
> > On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote:
> > >
> > > Cc: Greg
> > >
> > > On Wed, 15 Nov 2017, Ville Syrjälä wrote:
> > > > On Wed, Nov 15, 2017 at 04
On Fri, 17 Nov 2017, Greg KH wrote:
> On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote:
>>
>> Cc: Greg
>>
>> On Wed, 15 Nov 2017, Ville Syrjälä wrote:
>> > On Wed, Nov 15, 2017 at 04:44:54PM +, alexander.le...@verizon.com
>> > wrote:
>> >> On Wed, Nov 15, 2017 at 01:08:05PM +020
On Thu, Nov 16, 2017 at 09:01:03PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2017-11-16 19:14:50)
> > From: Ville Syrjälä
> >
> > Currently we're pinning the fence for the rotated GTT view. That doesn't
> > acually make any sense since the fence is used only for the FBC GTT
> > tracking
On Wed, 15 Nov 2017, David Weinehall wrote:
> On Mon, Nov 13, 2017 at 10:47:44AM -0800, Rodrigo Vivi wrote:
>> On Sat, Nov 11, 2017 at 09:43:44AM +, Sharma, Shashank wrote:
>> > Regards
>> >
>> > Shashank
>> >
>> >
>> > On 11/11/2017 3:56 AM, Rodrigo Vivi wrote:
>> > > Starting on GLK we su
Hi Greg, all,
Pardon for the silly question, but I'm struggling to find
documentation about this new 'autoselection' process?
Where can one read up on it - be that about the tooling or the heuristics used?
I think the above may be the core reason behind the discussion here.
Thanks
Emil
_
On Thu, Nov 16, 2017 at 09:06:08PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2017-11-16 19:14:47)
> > From: Ville Syrjälä
> >
> > The current code is trying to be lazy with fences on scanout buffers.
> > That looks broken for several reasons:
> > * gen2/3 always need a fence for tiled s
On Thu, Nov 16, 2017 at 12:49:23PM -0800, Rodrigo Vivi wrote:
> On Thu, Nov 16, 2017 at 07:14:47PM +, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The current code is trying to be lazy with fences on scanout buffers.
> > That looks broken for several reasons:
> > * gen2/3 always need
== Series Details ==
Series: drm/i915: Calculate watermarks for gen4 and lower atomically.
URL : https://patchwork.freedesktop.org/series/34001/
State : failure
== Summary ==
Applying: drm/i915: Calculate gen3- watermarks semi-atomically, v3.
Applying: drm/i915: Program gen3- watermarks atomic
Chris Wilson writes:
> Since removing the module parameter to force selection of ringbuffer
> emission for gen8, the code is defunct. Remove it.
>
> To put the difference into perspective, a couple of microbenchmarks
> (bdw i7-5557u, 20170324):
> ring
On Wed, Nov 15, 2017 at 05:31:56PM +0100, Maarten Lankhorst wrote:
> The watermarks it should calculate against are the old optimal watermarks.
> The currently active crtc watermarks are pure fiction, and are invalid in
> case of a nonblocking modeset, page flip enabling/disabling planes or any
> o
Thanks! Looks good to me.
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Wednesday, November 15, 2017 3:17 PM
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson ; Joonas Lahtinen
; Wang, Zhi A ; Ville
Syrjälä
Subject: [PATCH v2] drm/i915: Initialise ent
Chris Wilson writes:
> Comparing the state tested by intel_engine_is_idle() and printed by
> intel_engine_dump(), the only bit not shown is whether or not the device
> is wedged. Add that little bit of information to the pretty printer so
> that if the engine fails to idle we can see why.
>
> Sig
== Series Details ==
Series: drm/i915: Automatic i915_switch_context for legacy
URL : https://patchwork.freedesktop.org/series/34002/
State : success
== Summary ==
Series 34002v1 drm/i915: Automatic i915_switch_context for legacy
https://patchwork.freedesktop.org/api/1.0/series/34002/revisions
On Fri, Nov 17, 2017 at 03:01:08PM +0200, Jani Nikula wrote:
> On Fri, 17 Nov 2017, Greg KH wrote:
> > On Fri, Nov 17, 2017 at 01:28:05PM +0200, Jani Nikula wrote:
> >>
> >> Cc: Greg
> >>
> >> On Wed, 15 Nov 2017, Ville Syrjälä wrote:
> >> > On Wed, Nov 15, 2017 at 04:44:54PM +, alexander.l
From: Tvrtko Ursulin
We implement the new pmu->is_privileged callback and add our own sysctl
as /proc/sys/dev/i915/pmu_stream_paranoid (defaulting to true), which
enables system administrators to override the global
/proc/sys/kernel/perf_event_paranoid setting for i915 PMU only.
Signed-off-by: T
From: Tvrtko Ursulin
To allow system administrators finer-grained control over security
settings, we add an optional pmu->is_privileged(pmu, event) callback
which is consulted when unprivileged system-wide uncore event collection
is disabled.
Signed-off-by: Tvrtko Ursulin
Cc: Peter Zijlstra
Cc
On Fri, Nov 17, 2017 at 01:13:27PM +, Emil Velikov wrote:
> Hi Greg, all,
>
> Pardon for the silly question, but I'm struggling to find
> documentation about this new 'autoselection' process?
> Where can one read up on it - be that about the tooling or the heuristics
> used?
>
> I think the
Chris Wilson writes:
> If we can't find the enable_execlists parameter, presume that the switch
> is forced by the kernel and enabled for all hw supporting execlists. We
> don't have a GETPARAM or ENGINE_INFO to query the internal details.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuopp
== Series Details ==
Series: drm/i915: Automatic i915_switch_context for legacy
URL : https://patchwork.freedesktop.org/series/34002/
State : failure
== Summary ==
Test gem_exec_reloc:
Subgroup basic-range:
pass -> INCOMPLETE (shard-snb)
Subgroup basic-ran
Op 17-11-17 om 14:31 schreef Ville Syrjälä:
> On Wed, Nov 15, 2017 at 05:31:56PM +0100, Maarten Lankhorst wrote:
>> The watermarks it should calculate against are the old optimal watermarks.
>> The currently active crtc watermarks are pure fiction, and are invalid in
>> case of a nonblocking modese
On Fri, Nov 17, 2017 at 03:47:58PM +0100, Maarten Lankhorst wrote:
> Op 17-11-17 om 14:31 schreef Ville Syrjälä:
> > On Wed, Nov 15, 2017 at 05:31:56PM +0100, Maarten Lankhorst wrote:
> >> The watermarks it should calculate against are the old optimal watermarks.
> >> The currently active crtc wate
During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.
v2: Always submit the request if we emitted some commands during request
construction, as typically
As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the
Op 17-11-17 om 15:53 schreef Ville Syrjälä:
> On Fri, Nov 17, 2017 at 03:47:58PM +0100, Maarten Lankhorst wrote:
>> Op 17-11-17 om 14:31 schreef Ville Syrjälä:
>>> On Wed, Nov 15, 2017 at 05:31:56PM +0100, Maarten Lankhorst wrote:
The watermarks it should calculate against are the old optimal
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Automatic i915_switch_context
for legacy
URL : https://patchwork.freedesktop.org/series/34005/
State : failure
== Summary ==
Series 34005v1 series starting with [CI,1/2] drm/i915: Automatic
i915_switch_context for legacy
ht
Hi,
An update based on Chris & Tvrtko's feedback.
Cheers,
Lionel Landwerlin (4):
drm/i915: store all subslice masks
drm/i915/debugfs: reuse max slice/subslices already stored in sseu
drm/i915: expose engine availability through sysfs
drm/i915: expose EU topology through sysfs
drivers/g
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slice
This enables userspace to discover the engines available on the GPU.
Here is the layout on a Skylake GT4:
/sys/devices/pci:00/:00:02.0/drm/card0/gt
├── bcs
│ └── 0
│ ├── capabilities
│ ├── class
│ └── id
├── rcs
│ └── 0
│ ├── capabilities
│ ├── class
│
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't aggregate numbers.
This is essential for monitoring parts of the GPU with the OA unit,
because signals need
On 17/11/17 10:53, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-11-16 16:00:03)
With the introduction of asymetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
way of querying the Gen's GPU topology that doesn't aggregate numbers.
As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the
As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the
During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.
v2: Always submit the request if we emitted some commands during request
construction, as typically
If we can not run the drunk_hole test because we couldn't allocate the
memory for the permutation array (even after we tried trimming the
size), report a clear ENOMEM. Similary, if we are asked to operate on a
hole too small for ourselves, make it skip quietly.
v2: Avoid malloc(0) since that retur
This fix was originally reverted because it left a chromebook pixel
black, and no immediate fix was available. This has been fixed in the
meantime.
Rather than trying to remove the parameter, set it to default to true
for now, so we can always back out if required.
Signed-off-by: Maarten Lankhors
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8283e80597bd..38a1cdb3dbb2 100644
--- a/drivers/gpu/drm/i9
Small fixes for IPS, and then we flip the switch! :-)
Maarten Lankhorst (3):
drm/i915: Make ips_enabled a property depending on whether IPS is
enabled.
drm/i915: Enable IPS for sprite plane
drm/i915: Re-enable fastboot by default
drivers/gpu/drm/i915/i915_params.h| 2 +-
drivers/g
ips_enabled was used as a variable of whether IPS can be enabled or not,
but should be used to test whether IPS is actually enabled.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 75 ---
drivers/gpu/drm/i915/intel_pipe_crc.c | 2 -
== Series Details ==
Series: drm/i915: Expose more GPU properties through sysfs (rev2)
URL : https://patchwork.freedesktop.org/series/33950/
State : success
== Summary ==
Series 33950v2 drm/i915: Expose more GPU properties through sysfs
https://patchwork.freedesktop.org/api/1.0/series/33950/re
On Thu, Nov 16, 2017 at 03:21:32PM -0800, James Ausmus wrote:
> On Mon, Oct 23, 2017 at 05:50:32PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Rename enum plane to enum i9xx_plane_id to make it clear that it only
> > applies to pre-SKL platforms.
> >
> > enum i9xx_plane_id is a g
On Fri, Nov 17, 2017 at 04:37:54PM +0100, Maarten Lankhorst wrote:
> ips_enabled was used as a variable of whether IPS can be enabled or not,
> but should be used to test whether IPS is actually enabled.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 75
> +
== Series Details ==
Series: drm/i915: Pull the unconditional GPU cache invalidation into request
construction
URL : https://patchwork.freedesktop.org/series/34007/
State : failure
== Summary ==
Series 34007v1 drm/i915: Pull the unconditional GPU cache invalidation into
request construction
On Fri, Nov 17, 2017 at 04:37:55PM +0100, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 ++---
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915
On 17 November 2017 at 15:31, Chris Wilson wrote:
> If we can not run the drunk_hole test because we couldn't allocate the
> memory for the permutation array (even after we tried trimming the
> size), report a clear ENOMEM. Similary, if we are asked to operate on a
> hole too small for ourselves,
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Pull the unconditional GPU
cache invalidation into request construction
URL : https://patchwork.freedesktop.org/series/34008/
State : failure
== Summary ==
Series 34008v1 series starting with [CI,1/2] drm/i915: Pull the unco
On 17 November 2017 at 15:31, Chris Wilson wrote:
> If we can not run the drunk_hole test because we couldn't allocate the
> memory for the permutation array (even after we tried trimming the
> size), report a clear ENOMEM. Similary, if we are asked to operate on a
> hole too small for ourselves,
Quoting Chris Wilson (2017-11-17 15:23:58)
> @@ -1818,8 +1814,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
> /* Unconditionally flush any chipset caches (for streaming writes). */
> i915_gem_chipset_flush(eb->i915);
>
> - /* Unconditionally invalidate GPU cache
== Series Details ==
Series: drm/i915: Expose more GPU properties through sysfs (rev2)
URL : https://patchwork.freedesktop.org/series/33950/
State : success
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
fail -> PASS
As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the
== Series Details ==
Series: drm/i915/selftests: Report ENOMEM clearly for an allocation failure
(rev2)
URL : https://patchwork.freedesktop.org/series/33994/
State : success
== Summary ==
Series 33994v2 drm/i915/selftests: Report ENOMEM clearly for an allocation
failure
https://patchwork.fre
During request construction, after pinning the context we know whether
or not we have to emit a context switch. So move this common operation
from every caller into i915_gem_request_alloc() itself.
v2: Always submit the request if we emitted some commands during request
construction, as typically
As the request now may implicitly invoke a context-switch, we should
follow that with a GPU TLB invalidation. Also even before using GGTT, we
should invalidate the TLBs for any updates (as well as the ppgtt
invalidates that are unconditionally applied by execbuf). Since we
almost always require the
If we can not run the drunk_hole test because we couldn't allocate the
memory for the permutation array (even after we tried trimming the
size), report a clear ENOMEM. Similary, if we are asked to operate on a
hole too small for ourselves, make it skip quietly.
v2: Avoid malloc(0) since that retur
== Series Details ==
Series: drm/i915: Enable fastboot, v2!
URL : https://patchwork.freedesktop.org/series/34010/
State : success
== Summary ==
Series 34010v1 drm/i915: Enable fastboot, v2!
https://patchwork.freedesktop.org/api/1.0/series/34010/revisions/1/mbox/
Test chamelium:
Subgro
== Series Details ==
Series: drm/i915: Pull the unconditional GPU cache invalidation into request
construction (rev2)
URL : https://patchwork.freedesktop.org/series/34007/
State : warning
== Summary ==
Series 34007v2 drm/i915: Pull the unconditional GPU cache invalidation into
request constr
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