Op 27-10-17 om 03:09 schreef Matt Roper:
> On Wed, Oct 25, 2017 at 08:03:47AM +0200, Maarten Lankhorst wrote:
>> Op 25-10-17 om 01:01 schreef Matt Roper:
>>> On Thu, Oct 19, 2017 at 05:13:40PM +0200, Maarten Lankhorst wrote:
The original intent was to preserve watermarks as much as possible
>>
On Thu, 26 Oct 2017, James Ausmus wrote:
> On Thu, Oct 26, 2017 at 01:38:51PM +0200, Maarten Lankhorst wrote:
>> In kernel v4.10 the legacy crc api has been replaced by a generic
>> drm crc API. While at it, fix igt_require_pipe_crc, the file cannot be
>> opened any more when the crtc is not activ
On Thu, 26 Oct 2017, "Pandiyan, Dhinakaran"
wrote:
> On Thu, 2017-10-26 at 10:59 +0300, Jani Nikula wrote:
>> On Thu, 10 Aug 2017, Dhinakaran Pandiyan wrote:
>> > DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state
>> >
>> > 101 = Set Main-Link for local Sink device and all downstream
Hi Dave, as I said, I was aiming for the previous one to already be the
last, but here's one more i915 pull for v4.15.
There's a backmerge from drm-next as a dependency for the get/put
renames and timer setup updates.
BR,
Jani.
drm-intel-next-2017-10-23:
This time really the last i915 batch fo
The watermarks it should calculate against are the old optimal watermarks.
The currently active crtc watermarks are pure fiction, and are invalid in
case of a nonblocking modeset, page flip enabling/disabling planes or any
other reason.
When the crtc is disabled or during a modeset the intermediat
Originally we implemented skip_intermediate_wm to fix up garbage
watermarks for ILK watermarks that are insane, but it makes sense
to extend this to all platforms with 2-style watermark programming.
We don't know what the previous contents of the watermarks are, and they
could be something entirel
The watermarks it should calculate against are the old optimal watermarks.
The currently active crtc watermarks are pure fiction, and are invalid in
case of a nonblocking modeset, page flip enabling/disabling planes or any
other reason.
When the crtc is disabled or during a modeset the intermediat
== Series Details ==
Series: drm/i915: Do not rely on wm preservation for ILK watermarks
URL : https://patchwork.freedesktop.org/series/32197/
State : failure
== Summary ==
Series 32197 revision 1 was fully merged or fully failed: no git log
== Logs ==
For more details see: https://intel-gfx
On Thu, 26 Oct 2017, Chris Wilson wrote:
> Quoting Jani Nikula (2017-10-26 15:36:34)
>> On Tue, 24 Oct 2017, Chris Wilson wrote:
>> > Recently W=1 on gcc-7.2 (-Wunused-const-variable) caught a regression
>> > that had been lurking for 6 months, so lets try enabling the full set of
>> > warnings f
== Series Details ==
Series: series starting with [1/2] drm/i915: Do not rely on wm preservation for
ILK watermarks
URL : https://patchwork.freedesktop.org/series/32301/
State : failure
== Summary ==
Series 32301 revision 1 was fully merged or fully failed: no git log
== Logs ==
For more de
Op 27-10-17 om 09:39 schreef Jani Nikula:
> On Thu, 26 Oct 2017, James Ausmus wrote:
>> On Thu, Oct 26, 2017 at 01:38:51PM +0200, Maarten Lankhorst wrote:
>>> In kernel v4.10 the legacy crc api has been replaced by a generic
>>> drm crc API. While at it, fix igt_require_pipe_crc, the file cannot b
== Series Details ==
Series: series starting with [1/3] drm/i915: Calculate vlv/chv intermediate
watermarks correctly, v3.
URL : https://patchwork.freedesktop.org/series/32739/
State : success
== Summary ==
Series 32739v1 series starting with [1/3] drm/i915: Calculate vlv/chv
intermediate wa
On Thu, 26 Oct 2017, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Starting from version 204 VBT can specify the max TMDS clock we are
> allowed to use with HDMI ports. Parse that information and take it
> into account when filtering modes and computing a crtc state.
>
> Also take the opportunit
On Fri, 27 Oct 2017, Jani Nikula wrote:
> On Thu, 26 Oct 2017, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Starting from version 204 VBT can specify the max TMDS clock we are
>> allowed to use with HDMI ports. Parse that information and take it
>> into account when filtering modes and comp
On Thu, Oct 26, 2017 at 12:15:32PM +0100, Chris Wilson wrote:
> Quoting Michał Winiarski (2017-10-26 11:52:31)
> > On Thu, Oct 26, 2017 at 08:31:27AM +0100, Chris Wilson wrote:
> > > For measuring the cost of preemption, inject a low priority spinner
> > > between the two measurements; the differen
Quoting Mika Kuoppala (2017-10-27 07:44:31)
> Chris Wilson writes:
>
> > An interesting snippet from Sandybridge's prm:
> >
> > "Although a Ring Buffer can be enabled in the non-empty state, it must
> > not be disabled unless it is empty. Attempting to disable a Ring Buffer
> > in the non-empty s
== Series Details ==
Series: series starting with [1/3] drm/i915: Calculate vlv/chv intermediate
watermarks correctly, v3.
URL : https://patchwork.freedesktop.org/series/32739/
State : success
== Summary ==
Test kms_flip:
Subgroup dpms-vs-vblank-race:
fail -> PAS
On Fri, Oct 27, 2017 at 12:48:39AM +, Pandiyan, Dhinakaran wrote:
>
> On Thu, 2017-10-26 at 22:41 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > DP dongles may signal downstream HPD via short HPD pulses. Setting the
> > sink to DPMS off apparently kills the downstream HPD (at le
An interesting snippet from Sandybridge's prm:
"Although a Ring Buffer can be enabled in the non-empty state, it must
not be disabled unless it is empty. Attempting to disable a Ring Buffer
in the non-empty state is UNDEFINED."
Let's avoid the undefined behaviour as we disable the rings prior to
From: Ville Syrjälä
DP dongles may signal downstream HPD via short HPD pulses. Setting the
sink to DPMS off apparently kills the downstream HPD (at least on my
DP->VGA dongle), so skip the DPMS off for such dongles when we turn
off the port.
v2: Deal with DDI as well by moving the check into
On Fri, 27 Oct 2017, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> DP dongles may signal downstream HPD via short HPD pulses. Setting the
> sink to DPMS off apparently kills the downstream HPD (at least on my
> DP->VGA dongle), so skip the DPMS off for such dongles when we turn
> off the port.
>
== Series Details ==
Series: drm/i915: Empty the ring before disabling (rev2)
URL : https://patchwork.freedesktop.org/series/32727/
State : success
== Summary ==
Series 32727v2 drm/i915: Empty the ring before disabling
https://patchwork.freedesktop.org/api/1.0/series/32727/revisions/2/mbox/
T
== Series Details ==
Series: drm/i915: Improve DP downstream HPD handling (rev2)
URL : https://patchwork.freedesktop.org/series/32714/
State : warning
== Summary ==
Series 32714v2 drm/i915: Improve DP downstream HPD handling
https://patchwork.freedesktop.org/api/1.0/series/32714/revisions/2/mb
On Mon, 14 Aug 2017, Harry Wentland wrote:
> On 2017-08-11 02:10 PM, Dhinakaran Pandiyan wrote:
>> DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state
>>
>> 101 = Set Main-Link for local Sink device and all downstream Sink
>> devices to D3 (power-down mode), keep AUX block fully powere
An interesting snippet from Sandybridge's prm:
"Although a Ring Buffer can be enabled in the non-empty state, it must
not be disabled unless it is empty. Attempting to disable a Ring Buffer
in the non-empty state is UNDEFINED."
Let's avoid the undefined behaviour as we disable the rings prior to
Some machines, *cough* snb *cough*, fail catastrophically if asked to
reset the GPU under certain conditions. The initial guess is that this
is when the rings are still busy at the time of the reset request
(because that's a pattern we've seen elsewhere, hence why we do try
gen3_stop_engines() befo
== Series Details ==
Series: series starting with [1/2] drm/i915/edp: read edp display control
registers unconditionally
URL : https://patchwork.freedesktop.org/series/32695/
State : success
== Summary ==
Series 32695v1 series starting with [1/2] drm/i915/edp: read edp display
control regist
== Series Details ==
Series: drm/i915: Empty the ring before disabling (rev2)
URL : https://patchwork.freedesktop.org/series/32727/
State : warning
== Summary ==
Test kms_flip:
Subgroup dpms-vs-vblank-race:
fail -> PASS (shard-hsw) fdo#103060
Test kms_draw_c
pr_debug() is compiled out normally, and has to be selected in by
enabling dynamic-debug in Kconfig, or by code #define DEBUG. As we are
making more use of central debugging facilities using pr_debug, we need
to opt-in and enable the output for CI.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm
pr_debug() is conditionally compiled and requires either
dynamic-debugging to be enabled or for the code to opt-in using #define
DEBUG. Since drm_print provides a central debugging facility using
pr_debug(), make sure it will always produce output.
Signed-off-by: Chris Wilson
Cc: Rob Clark
Cc: D
We will want to break this down to give detailed per-engine warnings as
to why we still think we are active as we attempt to park the engines.
For the first step, just move the warning verbatim from the idle-worker
to intel_engines_park().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i91
If the we think the engine is still active when we attempt to park it,
we want more details -- so dump the engine state.
References: https://bugs.freedesktop.org/show_bug.cgi?id=103479
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_engine_cs.c | 20 +---
Quoting Patchwork (2017-10-27 12:04:04)
> == Series Details ==
>
> Series: drm/i915: Empty the ring before disabling (rev2)
> URL : https://patchwork.freedesktop.org/series/32727/
> State : warning
>
> == Summary ==
>
> Test kms_flip:
> Subgroup dpms-vs-vblank-race:
> f
== Series Details ==
Series: series starting with [1/2] drm/i915/edp: read edp display control
registers unconditionally
URL : https://patchwork.freedesktop.org/series/32695/
State : failure
== Summary ==
Series 32695v1 series starting with [1/2] drm/i915/edp: read edp display
control regist
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Empty the ring before disabling
URL : https://patchwork.freedesktop.org/series/32747/
State : failure
== Summary ==
Series 32747v1 series starting with [v2,1/2] drm/i915: Empty the ring before
disabling
https://patchwork.fre
On Fri, Oct 27, 2017 at 12:56:39AM +0100, Chris Wilson wrote:
> An interesting snippet from Sandybridge's prm:
>
> "Although a Ring Buffer can be enabled in the non-empty state, it must
> not be disabled unless it is empty. Attempting to disable a Ring Buffer
> in the non-empty state is UNDEFINED.
Quoting Ville Syrjälä (2017-10-27 12:27:59)
> On Fri, Oct 27, 2017 at 12:56:39AM +0100, Chris Wilson wrote:
> > An interesting snippet from Sandybridge's prm:
> >
> > "Although a Ring Buffer can be enabled in the non-empty state, it must
> > not be disabled unless it is empty. Attempting to disabl
On Fri, Oct 27, 2017 at 01:25:01PM +0300, Jani Nikula wrote:
> On Mon, 14 Aug 2017, Harry Wentland wrote:
> > On 2017-08-11 02:10 PM, Dhinakaran Pandiyan wrote:
> >> DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state
> >>
> >> 101 = Set Main-Link for local Sink device and all downstre
Op 19-10-17 om 15:37 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Pass an old crtc state to intel_ddi_post_disable() from the MST code.
>
> Note that this crtc state won't necessaitly match the one that was
> passed to intel_ddi_pre_enable() if the first stream to be enabled isn't
> the last s
Op 19-10-17 om 15:37 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Eliminate the partially duplicated DDI readout code from MST, and
> instead just call intel_ddi_get_config(). As a nice bonus we get
> more cross checking as intel_ddi_get_config() will populate
> output_types based on the actua
Quoting Patchwork (2017-10-26 16:00:53)
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Hold rcu_read_lock when
> iterating over the radixtree (objects)
> URL : https://patchwork.freedesktop.org/series/32693/
> State : warning
>
> == Summary ==
>
> Test kms_busy:
>
Op 19-10-17 om 15:37 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Reduce our general reliance on encoder->type and instead use
> output_types from the crtc state when enabling LPE audio.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_audio.c | 2 +-
> 1 file changed, 1 i
On Fri, Oct 27, 2017 at 01:39:00PM +0200, Maarten Lankhorst wrote:
> Op 19-10-17 om 15:37 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > Pass an old crtc state to intel_ddi_post_disable() from the MST code.
> >
> > Note that this crtc state won't necessaitly match the one that was
> > pass
On Fri, Oct 27, 2017 at 01:43:54PM +0200, Maarten Lankhorst wrote:
> Op 19-10-17 om 15:37 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > Reduce our general reliance on encoder->type and instead use
> > output_types from the crtc state when enabling LPE audio.
> >
> > Signed-off-by: Ville S
On Fri, Oct 27, 2017 at 01:43:03PM +0200, Maarten Lankhorst wrote:
> Op 19-10-17 om 15:37 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > Eliminate the partially duplicated DDI readout code from MST, and
> > instead just call intel_ddi_get_config(). As a nice bonus we get
> > more cross che
On Fri, Oct 27, 2017 at 09:59:47AM +0200, Maarten Lankhorst wrote:
> Originally we implemented skip_intermediate_wm to fix up garbage
> watermarks for ILK watermarks that are insane, but it makes sense
> to extend this to all platforms with 2-style watermark programming.
I don't particularly like
Op 19-10-17 om 15:37 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Currently the DDI encoder->type will change at runtime depending on
> what kind of hotplugs we've processed. That's quite bad since we can't
> really trust that that current value of encoder->type actually matches
> the type of
Chris Wilson writes:
> Some machines, *cough* snb *cough*, fail catastrophically if asked to
> reset the GPU under certain conditions. The initial guess is that this
> is when the rings are still busy at the time of the reset request
> (because that's a pattern we've seen elsewhere, hence why we
On Fri, Oct 27, 2017 at 10:05:39AM +0200, Maarten Lankhorst wrote:
> Op 27-10-17 om 09:39 schreef Jani Nikula:
> > On Thu, 26 Oct 2017, James Ausmus wrote:
> >> On Thu, Oct 26, 2017 at 01:38:51PM +0200, Maarten Lankhorst wrote:
> >>> In kernel v4.10 the legacy crc api has been replaced by a generi
Quoting Mika Kuoppala (2017-10-27 13:18:44)
> Chris Wilson writes:
>
> > Some machines, *cough* snb *cough*, fail catastrophically if asked to
> > reset the GPU under certain conditions. The initial guess is that this
> > is when the rings are still busy at the time of the reset request
> > (beca
== Series Details ==
Series: series starting with [1/4] drm: Enable pr_debug() for drm_printer
URL : https://patchwork.freedesktop.org/series/32750/
State : success
== Summary ==
Series 32750v1 series starting with [1/4] drm: Enable pr_debug() for drm_printer
https://patchwork.freedesktop.org/
On Fri, Oct 27, 2017 at 02:05:38PM +0200, Maarten Lankhorst wrote:
> Op 19-10-17 om 15:37 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > Currently the DDI encoder->type will change at runtime depending on
> > what kind of hotplugs we've processed. That's quite bad since we can't
> > really
A purely recursive batch has the downside that it is a severe drain on
system resources (see commit f978cc027cd0 "lib/dummyload: Pad with a few
nops so that we do not completely hog the system") which can result in
the test being starved and failing to make reasonably progress. For more
reliable re
On Fri, Oct 27, 2017 at 01:45:35PM +0100, Chris Wilson wrote:
> A purely recursive batch has the downside that it is a severe drain on
> system resources (see commit f978cc027cd0 "lib/dummyload: Pad with a few
> nops so that we do not completely hog the system") which can result in
> the test being
Quoting Ville Syrjälä (2017-10-27 13:54:49)
> On Fri, Oct 27, 2017 at 01:45:35PM +0100, Chris Wilson wrote:
> > A purely recursive batch has the downside that it is a severe drain on
> > system resources (see commit f978cc027cd0 "lib/dummyload: Pad with a few
> > nops so that we do not completely h
== Series Details ==
Series: drm/i915: Improve DP downstream HPD handling (rev2)
URL : https://patchwork.freedesktop.org/series/32714/
State : success
== Summary ==
Series 32714v2 drm/i915: Improve DP downstream HPD handling
https://patchwork.freedesktop.org/api/1.0/series/32714/revisions/2/mb
Quoting Chris Wilson (2017-10-27 13:59:17)
> Quoting Ville Syrjälä (2017-10-27 13:54:49)
> > On Fri, Oct 27, 2017 at 01:45:35PM +0100, Chris Wilson wrote:
> > > A purely recursive batch has the downside that it is a severe drain on
> > > system resources (see commit f978cc027cd0 "lib/dummyload: Pad
Chris Wilson writes:
> We will want to break this down to give detailed per-engine warnings as
> to why we still think we are active as we attempt to park the engines.
> For the first step, just move the warning verbatim from the idle-worker
> to intel_engines_park().
>
> Signed-off-by: Chris Wil
== Series Details ==
Series: lib/gt: Insert an arbitration point in our hang batch
URL : https://patchwork.freedesktop.org/series/32753/
State : warning
== Summary ==
IGT patchset tested on top of latest successful build
1fc4de1ca390adec9be8bd7cc0c36cab07465959 igt/gem_exec_latency: Wire up an
On Fri, Oct 27, 2017 at 01:59:17PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2017-10-27 13:54:49)
> > On Fri, Oct 27, 2017 at 01:45:35PM +0100, Chris Wilson wrote:
> > > A purely recursive batch has the downside that it is a severe drain on
> > > system resources (see commit f978cc027cd0
Chris Wilson writes:
> If the we think the engine is still active when we attempt to park it,
> we want more details -- so dump the engine state.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=103479
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Acked-by: Mika Kuoppala
You
Quoting Ville Syrjälä (2017-10-27 14:24:16)
> On Fri, Oct 27, 2017 at 01:59:17PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjälä (2017-10-27 13:54:49)
> > > On Fri, Oct 27, 2017 at 01:45:35PM +0100, Chris Wilson wrote:
> > > > A purely recursive batch has the downside that it is a severe drain
Quoting Mika Kuoppala (2017-10-27 14:25:09)
> Chris Wilson writes:
>
> > If the we think the engine is still active when we attempt to park it,
> > we want more details -- so dump the engine state.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=103479
> > Signed-off-by: Chris Wi
From: Tvrtko Ursulin
Mask out the bits which do not fit into the specified
width in order to avoid corrupting the stored pointer.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_utils.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_ut
From: Tvrtko Ursulin
GEM_BUG_ON if the packed bits do not fit into the specified width.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_utils.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_u
From: Tvrtko Ursulin
We have to reject unknown flags for uAPI considerations, and also
because the curent implementation limits their i915 storage space
to two bits.
Signed-off-by: Tvrtko Ursulin
Fixes: cf6e7bac6357 ("drm/i915: Add support for drm syncobjs")
Cc: Jason Ekstrand
Cc: Chris Wilson
== Series Details ==
Series: series starting with [1/2] drm/i915: Hold rcu_read_lock when iterating
over the radixtree (objects)
URL : https://patchwork.freedesktop.org/series/32693/
State : failure
== Summary ==
Series 32693 revision 1 was fully merged or fully failed: no git log
== Logs ==
== Series Details ==
Series: series starting with [1/2] drm/i915: Hold rcu_read_lock when iterating
over the radixtree (objects)
URL : https://patchwork.freedesktop.org/series/32693/
State : failure
== Summary ==
Series 32693 revision 1 was fully merged or fully failed: no git log
== Logs ==
From: Ville Syrjälä
Call the DDI .pre_pll_enable() hook from the MST code so that BXT gets
the correct lane latency optimal setting applied. And we obviously need
to compute the correct value, and read it out to keep the state checker
happy.
While at it drop the useless 'encoder' parameter to
bx
Quoting Tvrtko Ursulin (2017-10-27 14:40:14)
> From: Tvrtko Ursulin
>
> GEM_BUG_ON if the packed bits do not fit into the specified width.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_utils.h | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a
Quoting Tvrtko Ursulin (2017-10-27 14:40:12)
> From: Tvrtko Ursulin
>
> We have to reject unknown flags for uAPI considerations, and also
> because the curent implementation limits their i915 storage space
> to two bits.
>
> Signed-off-by: Tvrtko Ursulin
> Fixes: cf6e7bac6357 ("drm/i915: Add su
Op 27-10-17 om 14:44 schreef Ville Syrjälä:
> On Fri, Oct 27, 2017 at 02:05:38PM +0200, Maarten Lankhorst wrote:
>> Op 19-10-17 om 15:37 schreef Ville Syrjala:
>>> From: Ville Syrjälä
>>>
>>> Currently the DDI encoder->type will change at runtime depending on
>>> what kind of hotplugs we've proces
On Fri, Oct 27, 2017 at 04:43:48PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Call the DDI .pre_pll_enable() hook from the MST code so that BXT gets
> the correct lane latency optimal setting applied. And we obviously need
> to compute the correct value, and read it out to keep the sta
Op 27-10-17 om 15:43 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Call the DDI .pre_pll_enable() hook from the MST code so that BXT gets
> the correct lane latency optimal setting applied. And we obviously need
> to compute the correct value, and read it out to keep the state checker
> happy.
== Series Details ==
Series: series starting with [1/3] drm/i915: Reject unknown syncobj flags
URL : https://patchwork.freedesktop.org/series/32755/
State : failure
== Summary ==
Series 32755v1 series starting with [1/3] drm/i915: Reject unknown syncobj flags
https://patchwork.freedesktop.org/
On Fri, Oct 27, 2017 at 03:53:34PM +0200, Maarten Lankhorst wrote:
> Op 27-10-17 om 14:44 schreef Ville Syrjälä:
> > On Fri, Oct 27, 2017 at 02:05:38PM +0200, Maarten Lankhorst wrote:
> >> Op 19-10-17 om 15:37 schreef Ville Syrjala:
> >>> From: Ville Syrjälä
> >>>
> >>> Currently the DDI encoder->
There is a possibility on gen9 hardware to miss the forcewake ack
message. The recommended workaround is to use another free
bit and toggle it until original bit is successfully acknowledged.
Some future gen9 revs might or might not fix the underlying issue but
the fallback to reserve bit dance ca
Op 27-10-17 om 16:03 schreef Ville Syrjälä:
> On Fri, Oct 27, 2017 at 03:53:34PM +0200, Maarten Lankhorst wrote:
>> Op 27-10-17 om 14:44 schreef Ville Syrjälä:
>>> On Fri, Oct 27, 2017 at 02:05:38PM +0200, Maarten Lankhorst wrote:
Op 19-10-17 om 15:37 schreef Ville Syrjala:
> From: Ville S
Mika Kuoppala writes:
> There is a possibility on gen9 hardware to miss the forcewake ack
> message. The recommended workaround is to use another free
> bit and toggle it until original bit is successfully acknowledged.
>
> Some future gen9 revs might or might not fix the underlying issue but
> t
From: Tvrtko Ursulin
We have to reject unknown flags for uAPI considerations, and also
because the curent implementation limits their i915 storage space
to two bits.
v2: (Chris Wilson)
* Fix fail in ABI check.
* Added unknown flags and BUILD_BUG_ON.
Signed-off-by: Tvrtko Ursulin
Fixes: cf6e7
== Series Details ==
Series: drm/i915: Fix BXT lane latenccy optimal setting with MST
URL : https://patchwork.freedesktop.org/series/32756/
State : failure
== Summary ==
Series 32756v1 drm/i915: Fix BXT lane latenccy optimal setting with MST
https://patchwork.freedesktop.org/api/1.0/series/327
Op 27-10-17 om 13:49 schreef Ville Syrjälä:
> On Fri, Oct 27, 2017 at 01:39:00PM +0200, Maarten Lankhorst wrote:
>> Op 19-10-17 om 15:37 schreef Ville Syrjala:
>>> From: Ville Syrjälä
>>>
>>> Pass an old crtc state to intel_ddi_post_disable() from the MST code.
>>>
>>> Note that this crtc state wo
== Series Details ==
Series: drm/i915: Fallback to reserve forcewake if primary ack missing (rev2)
URL : https://patchwork.freedesktop.org/series/32694/
State : success
== Summary ==
Series 32694v2 drm/i915: Fallback to reserve forcewake if primary ack missing
https://patchwork.freedesktop.org
Quoting Mika Kuoppala (2017-10-27 15:04:21)
> There is a possibility on gen9 hardware to miss the forcewake ack
> message. The recommended workaround is to use another free
> bit and toggle it until original bit is successfully acknowledged.
>
> Some future gen9 revs might or might not fix the und
I don't know whether anyone noticed that sseu_status appears to be
broken on BXT :
cat /sys/kernel/debug/dri/0/i915_sseu_status
SSEU Device Info
Available Slice Mask: 0001
Available Slice Total: 1
Available Subslice Total: 2
Available Slice0 Subslice Mask: 0006
Available EU Total: 12
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Reject unknown syncobj flags
(rev2)
URL : https://patchwork.freedesktop.org/series/32755/
State : failure
== Summary ==
Series 32755v2 series starting with [v2,1/3] drm/i915: Reject unknown syncobj
flags
https://patchwork.f
== Series Details ==
Series: drm/i915: Fix BXT lane latenccy optimal setting with MST
URL : https://patchwork.freedesktop.org/series/32756/
State : failure
== Summary ==
Series 32756v1 drm/i915: Fix BXT lane latenccy optimal setting with MST
https://patchwork.freedesktop.org/api/1.0/series/327
== Series Details ==
Series: drm/i915: Fix BXT lane latenccy optimal setting with MST
URL : https://patchwork.freedesktop.org/series/32756/
State : failure
== Summary ==
Series 32756v1 drm/i915: Fix BXT lane latenccy optimal setting with MST
https://patchwork.freedesktop.org/api/1.0/series/327
== Series Details ==
Series: series starting with [1/4] drm: Enable pr_debug() for drm_printer
URL : https://patchwork.freedesktop.org/series/32750/
State : warning
== Summary ==
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-A:
pass -> DMES
== Series Details ==
Series: drm/i915: Improve DP downstream HPD handling (rev2)
URL : https://patchwork.freedesktop.org/series/32714/
State : success
== Summary ==
Test kms_busy:
Subgroup extended-modeset-hang-oldfb-with-reset-render-B:
pass -> DMESG-WARN (shard-
Hi all,
Here is a series to enable perf support on Cannonlake. It requires
exposing some more information to userspace, for a couple of reasons :
1) Cannonlake introduces asymetric slices (i.e. not the same number
of subslices for each slice)
2) Depending on the parts, the frequency
We can enable GT3 as well as GT2.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_oa_cflgt3.c | 109 ++
drivers/gpu/drm/i915/i915_oa_cflgt3.h | 34 ++
We were missing some registers and also can name one for which we only had
the offset.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 14 ++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/
This name was added with the whitelisting of registers for building up OA
configs. It is contained in a range gen8 whitelist :
addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg
Hence why the name isn't used anywhere.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_reg.h |
We use to have this fixed per generation, but starting with CNL userspace
cannot tell just off the PCI ID. Let's make this information available. This
is particularly useful for performance monitoring where much of the
normalization work is done using those timestamps (this include pipeline
statist
With the introduction of asymetric slices in CNL, we cannot rely on the
previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of
querying the Gen's GPU topology that doesn't aggregate numbers.
This is essential for monitoring parts of the GPU with the OA unit, because
counters nee
Now that we have this stored in the device info, we can drop it from perf
part of the driver.
Note that this requires to init perf after we've computed the frequency,
hence why we move i915_perf_init() from i915_driver_init_early() to after
intel_device_info_runtime_init().
Signed-off-by: Lionel
Gen8/9 aren't very different and we can merge some of this code.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 48 +---
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm
This adds new registers to the whitelist to configs emitted from userspace.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_oa_cnl.c | 121 +
drivers/gpu/drm/i915/i915_oa_cnl.h | 34 +++
driv
Now that we have that information in topology fields, let's just reused it.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu
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