On 9/25/2017 3:31 PM, Joonas Lahtinen wrote:
On Fri, 2017-09-22 at 20:16 +0530, Sagar Arun Kamble wrote:
On 9/22/2017 5:34 PM, Joonas Lahtinen wrote:
On Fri, 2017-09-22 at 15:37 +0530, Sagar Arun Kamble wrote:
With GuC v9, new type of Default/critical logging in GuC to enable
capturing minim
Hi,
[ bringing a private discussion back to the list ]
> The dma-buf's life cycle is handled by user mode and tracked by
> kernel.
> The returned fd in struct vfio_device_query_gfx_plane can be a new
> fd or an old fd of a re-exported dma-buf. Host user mode can check
> the
> value of fd and to
Prepared intel_auth_huc to separate HuC specific functionality
from GuC send action. Created new header intel_huc.h to group
HuC specific declarations.
v2: Changed argument preparation for AUTHENTICATE_HUC.
s/intel_auth_huc/intel_huc_auth. Deferred creation of intel_huc.h
to later patch.
v3: Reba
Add Plane Degamma as a blob property and plane
degamma size as a range property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c| 12
drivers/gpu/drm/drm_atomic_helper.c |6 ++
drivers/gpu/drm/drm_mode_config.c | 14 ++
include/drm/drm_m
This patch series adds properties for plane color features. It adds
properties for degamma used to linearize data, CSC used for gamut
conversion, and gamma used to again non-linearize data as per panel
supported color space. These can be utilize by user space to convert
planes from one format to an
Add plane gamma as blob property and size as a
range property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c|8
drivers/gpu/drm/drm_atomic_helper.c |3 +++
drivers/gpu/drm/drm_mode_config.c | 14 ++
include/drm/drm_mode_config.h | 11
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_plane.c | 48 ++
include/drm/drm_color_mgmt.h |5 +
2 files changed, 53 insertions(+)
Add a blob property for plane CSC usage.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c| 10 ++
drivers/gpu/drm/drm_atomic_helper.c |3 +++
drivers/gpu/drm/drm_mode_config.c |7 +++
include/drm/drm_mode_config.h |6 ++
include/drm/drm_pl
Define a helper function to set legacy gamma table
size for planes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_color_mgmt.c | 41 ++
include/drm/drm_color_mgmt.h |3 +++
include/drm/drm_plane.h |4
3 files changed, 48 insert
Enable and initilaize plane color features.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h |8
drivers/gpu/drm/i915/intel_color.c | 14 ++
drivers/gpu/drm/i915/intel_display.c |4
drivers/gpu/drm/i915/intel_drv.h |9 +
dr
On Tue, Sep 19, 2017 at 11:11:44PM +0530, Sagar Arun Kamble wrote:
> This function gives the status of RC6, whether disabled or if
> enabled then which state. intel_enable_rc6 will be used for
> enabling RC6 in the next patch.
>
> Cc: Chris Wilson
> Cc: Imre Deak
> Signed-off-by: Sagar Arun Kamb
On Mon, Sep 25, 2017 at 07:47:17PM +0100, Matthew Auld wrote:
> Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
> moves us away from the shmemfs shm_mnt, and gives us the much needed
> flexibility to do things like set our own mount options, namely huge=
> which should allow
On Mon, Sep 25, 2017 at 11:23:26AM +0300, Jani Nikula wrote:
> On Sat, 23 Sep 2017, vathsala nagaraju wrote:
> > Add defines for dpcd register 2009 (synchronization latency
> > in sink).
> >
> > Cc: Rodrigo Vivi
> > CC: Puthikorn Voravootivat
> > Reviewed-by: Rodrigo Vivi
> > Signed-off-by: Vat
On Mon, 25 Sep 2017, Vidya Srinivas wrote:
> From: Uma Shankar
>
> For certain platforms on certain encoders, timings are driven
> from port instead of pipe. Thus, we can't rely on pipe scanline
> registers to get the timing information. Some cases scanline
> register read will not be functional.
== Series Details ==
Series: series starting with [v9,1/1] drm/i915/huc: Reorganize HuC
authentication
URL : https://patchwork.freedesktop.org/series/30874/
State : success
== Summary ==
Series 30874v1 series starting with [v9,1/1] drm/i915/huc: Reorganize HuC
authentication
https://patchwor
On Mon, 2017-09-25 at 14:29 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/3] drm/i915: Make I915_PARAMS_FOR_EACH
> macro more flexible
> URL : https://patchwork.freedesktop.org/series/30833/
> State : success
Series is now merged, thanks for the patches
It also wants to delete drm-rerere/nightly.conf when that hasn't been
touched in a while. Prevent that in the future.
Chris Wilson hit that snag, which then seems to have percolated to
some other committers.
Cc: Chris Wilson
Cc: Joonas Lahtinen
Acked-by: Joonas Lahtinen
Signed-off-by: Daniel V
Since the introduction of debugfs/i915_drop_caches, we have offered the
ability to wait upon all outstanding batches. This is more efficient and
less error prone (one example is the use of context priorities, we have
to idle at the lowest in order not to jump over any low priority tasks
we want to
On Tue, 2017-09-26 at 12:47 +0530, Sagar Arun Kamble wrote:
> Prepared intel_auth_huc to separate HuC specific functionality
> from GuC send action. Created new header intel_huc.h to group
> HuC specific declarations.
>
> v2: Changed argument preparation for AUTHENTICATE_HUC.
> s/intel_auth_huc/in
Quoting Sagar Arun Kamble (2017-09-26 08:17:16)
> Prepared intel_auth_huc to separate HuC specific functionality
> from GuC send action. Created new header intel_huc.h to group
> HuC specific declarations.
>
> v2: Changed argument preparation for AUTHENTICATE_HUC.
> s/intel_auth_huc/intel_huc_auth
On Tue, 2017-09-26 at 08:25 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v9,1/1] drm/i915/huc: Reorganize HuC
> authentication
> URL : https://patchwork.freedesktop.org/series/30874/
> State : success
This has been merged, thanks for the patch and reviews.
DP v1.3 spec reserved DPCD TRAINING_AUX_RD_INTERVAL (Eh)
bit7 to indicate Extended Receiver Capability. A DPRX with DPCD
Rev. 1.4 (or higher) must have an Extended Receiver Capability field.
Driver have to clear bit7 when retrieve interval value and avoid to
wait for needless delay.
Cc: Jani N
Quoting Daniel Vetter (2017-09-26 09:41:37)
> It also wants to delete drm-rerere/nightly.conf when that hasn't been
> touched in a while. Prevent that in the future.
>
> Chris Wilson hit that snag, which then seems to have percolated to
> some other committers.
>
> Cc: Chris Wilson
> Cc: Joonas
== Series Details ==
Series: Add Plane Color Properties
URL : https://patchwork.freedesktop.org/series/30875/
State : success
== Summary ==
Series 30875v1 Add Plane Color Properties
https://patchwork.freedesktop.org/api/1.0/series/30875/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgr
Michal wants to limit machines that can do preemption, which means that
we no longer can assume that if we have a scheduler for execbuf, that
implies we have preemption.
v2: Try a capability mask instead
Signed-off-by: Chris Wilson
---
tests/gem_exec_schedule.c | 45
Quoting Chris Wilson (2017-09-26 10:32:40)
> Michal wants to limit machines that can do preemption, which means that
> we no longer can assume that if we have a scheduler for execbuf, that
> implies we have preemption.
>
> v2: Try a capability mask instead
>
> Signed-off-by: Chris Wilson
> ---
>
On Tue, 26 Sep 2017, "Lee, Shawn C" wrote:
> DP v1.3 spec reserved DPCD TRAINING_AUX_RD_INTERVAL (Eh)
> bit7 to indicate Extended Receiver Capability. A DPRX with DPCD
> Rev. 1.4 (or higher) must have an Extended Receiver Capability field.
> Driver have to clear bit7 when retrieve interval val
Take advantage of optimised memset64() instead of open coding it to
prefill the GTT pages.
Signed-off-by: Chris Wilson
---
Needs backmerge from 4.14-rc1, but it's tantalisingly close.
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/d
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
v3 : (Rodrigo)
- move macro EDP_PSR2_FRAME_BEFORE_SU
Add defines for dpcd register 2009 (synchronization latency
in sink).
v2:
- add spec version (Daniel)
- use register name as is in spec,only drop excess
from end (jani)
- add the full register contents (jani)
Cc: Rodrigo Vivi
CC: Puthikorn Voravootivat
Reviewed-by: Rodrigo Vivi
Signed-of
Hey,
Uma Shankar schreef op di 26-09-2017 om 13:32 [+0530]:
> Define a helper function to set legacy gamma table
> size for planes.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/drm_color_mgmt.c | 41
> ++
> include/drm/drm_color_mgmt.h |3
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Lankhorst, Maarten
>Sent: Tuesday, September 26, 2017 3:36 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
>dri-de...@lists.freedesktop.org
>Cc: Syrjala, Ville
>Subject: Re: [RFC v
On Tue, Sep 26, 2017 at 10:02:02AM +0100, Chris Wilson wrote:
> Since the introduction of debugfs/i915_drop_caches, we have offered the
> ability to wait upon all outstanding batches. This is more efficient and
> less error prone (one example is the use of context priorities, we have
> to idle at t
Quoting Wang, Zhi A (2017-09-26 07:20:00)
> Thanks for the explanation 2). :)
>
> I'm thinking about the rough design of preemption in GVT-g since host is
> moving to support preemption.
>
> 1) Global MMIO save/restore, which is covered by context status notifier.
>
> 2) Support host preemptio
Shankar, Uma schreef op di 26-09-2017 om 15:41 [+0530]:
> > -Original Message-
> > From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On
> > Behalf Of
> > Lankhorst, Maarten
> > Sent: Tuesday, September 26, 2017 3:36 PM
> > To: Shankar, Uma ; intel-gfx@lists.freedeskt
> > op.o
Let the listener know that the context we just scheduled out was not
complete, and will be scheduled back in at a later point.
Signed-off-by: Chris Wilson
Cc: "Zhenyu Wang"
Cc: "Wang, Zhi A"
Cc: Michał Winiarski
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +
When cancelling requests, also send the notification to any listeners
(gvt) that the request is no longer scheduler on hw. They may require to
keep the in/out exactly balanced, and so the reuse after the reset may
confuse the listener.
Fixes: 221ab9719bf3 ("drm/i915/execlists: Unwind incomplete re
Chris Wilson writes:
> When cancelling requests, also send the notification to any listeners
> (gvt) that the request is no longer scheduler on hw. They may require to
s/scheduler/scheduled.
lgtm
-Mika
> keep the in/out exactly balanced, and so the reuse after the reset may
> confuse the liste
>-Original Message-
>From: Lankhorst, Maarten
>Sent: Tuesday, September 26, 2017 3:45 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
>dri-de...@lists.freedesktop.org
>Cc: Syrjala, Ville
>Subject: Re: [RFC v1 5/6] drm: Define helper to set legacy gamma table size
>
>Shankar, Uma
On 26/09/2017 10:53, Chris Wilson wrote:
Take advantage of optimised memset64() instead of open coding it to
prefill the GTT pages.
Signed-off-by: Chris Wilson
---
Needs backmerge from 4.14-rc1, but it's tantalisingly close.
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +---
1 file changed,
Quoting Tvrtko Ursulin (2017-09-26 11:30:50)
>
> On 26/09/2017 10:53, Chris Wilson wrote:
> > Take advantage of optimised memset64() instead of open coding it to
> > prefill the GTT pages.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > Needs backmerge from 4.14-rc1, but it's tantalisingly close
Thanks for the patch! :)
I got a question: Will the re-scheduling of the request be handled by i915? Or
the client has to re-submit the request by itself after it got preempted? :)
Currently, we will call i915_wait_request() to wait the request. I guess the
preemption will not wake up the i915_
Quoting Wang, Zhi A (2017-09-26 11:42:48)
> Thanks for the patch! :)
>
> I got a question: Will the re-scheduling of the request be handled by i915?
> Or the client has to re-submit the request by itself after it got preempted?
> :)
It remains in the execlist queue, so it will be rescheduled at
On 25/09/2017 16:22, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-09-25 16:14:56)
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
lib/Makefile.sources | 2 ++
overlay/perf.c => lib/igt_perf.c | 2 +-
overlay/perf.h => lib/igt_perf.h | 2 ++
overlay/Makefile.am
On 25/09/2017 16:31, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-09-25 16:14:59)
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
lib/igt_perf.h | 93 ++--
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 4 +--
On 25 September 2017 at 21:26, Chris Wilson wrote:
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Tvrtko Ursulin (2017-09-26 11:52:28)
>
> On 25/09/2017 16:22, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-09-25 16:14:56)
> >> From: Tvrtko Ursulin
> >>
> >> Signed-off-by: Tvrtko Ursulin
> >> ---
> >> lib/Makefile.sources | 2 ++
> >> overlay/perf.c => lib/igt_pe
Quoting Tvrtko Ursulin (2017-09-26 11:56:24)
>
> On 25/09/2017 16:31, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-09-25 16:14:59)
> >> From: Tvrtko Ursulin
> >>
> >> Signed-off-by: Tvrtko Ursulin
> >> ---
> >> diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
> >> index 812f47d5aced..6
On Tue, Sep 26, 2017 at 01:32:52PM +0530, Uma Shankar wrote:
> This patch series adds properties for plane color features. It adds
> properties for degamma used to linearize data, CSC used for gamut
> conversion, and gamma used to again non-linearize data as per panel
> supported color space. These
== Series Details ==
Series: drm/dp: Avoid needless delay while link training
URL : https://patchwork.freedesktop.org/series/30891/
State : success
== Summary ==
Series 30891v1 drm/dp: Avoid needless delay while link training
https://patchwork.freedesktop.org/api/1.0/series/30891/revisions/1/m
On 25/09/2017 17:21, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-09-25 16:15:00)
From: Tvrtko Ursulin
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based eng
On 25/09/2017 17:44, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-09-25 16:15:01)
From: Tvrtko Ursulin
Add busy and busy-avg balancers which make balancing
decisions by looking at engine busyness via the i915 PMU.
"And thus are able to make decisions on the actual instantaneous load of
On Mon, Sep 11, 2017 at 03:03:40PM +0300, Arkadiusz Hiler wrote:
> On Fri, Sep 08, 2017 at 05:14:46PM +0200, Daniel Vetter wrote:
> > Run ./meson.sh once, then you have
> >
> > $ make
> >
> > and
> >
> > $ make test
> >
> > available in the normal src root.
> >
> > v2:
> >
> > Add
> >
> > $
Quoting Tvrtko Ursulin (2017-09-26 12:19:35)
>
> On 25/09/2017 17:21, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-09-25 16:15:00)
> >> +#define assert_within_epsilon(x, ref, tolerance) \
> >> + igt_assert_f((double)(x) <= (1.0 + tolerance) * (double)ref && \
> >> +
Matthew Auld writes:
> When SW enables the use of 2M/1G pages, it must disable the GTT cache.
>
> v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
>
> v3: explicitly check that the system does support 2M/1G pages
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc:
Suggested by Chris Wilson.
v2: Fix typo in the error msg (Chris).
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-by: Daniel Vetter
---
dim | 6 ++
1 file changed, 6 insertions(+)
diff --git a/dim b/dim
index db11d3f1cc68..69109a4f8666 100755
--- a/dim
+++ b/dim
@@ -220,6 +220,12 @@ if [
Requested by Jani.
To do this properly we need to again push the reading of nightly.conf
to be after the basic sanity checks, like it was before
commit 12976ee32ae2cb97c7384ef6afde5f9076fc7d99
Author: Jani Nikula
Date: Fri Oct 28 12:40:46 2016 +0300
dim: switch to using remote agnostic in
On Tue, Sep 19, 2017 at 02:56:17PM -0700, Kristian Høgsberg wrote:
> On Mon, Aug 28, 2017 at 3:17 PM, Daniel Vetter wrote:
> > On Mon, Aug 28, 2017 at 04:22:16PM +0530, Vidya Srinivas wrote:
> >> This patch series is adding NV12 support for Broxton display after
> >> rebasing on latest drm-intel-n
Quoting Tvrtko Ursulin (2017-09-26 12:27:33)
>
> On 25/09/2017 17:44, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-09-25 16:15:01)
> >> From: Tvrtko Ursulin
> >>
> >> Add busy and busy-avg balancers which make balancing
> >> decisions by looking at engine busyness via the i915 PMU.
> >
>
On Mon, Sep 18, 2017 at 12:12:50PM +0200, Maarten Lankhorst wrote:
> Commit b44d5c0c105a ("drm/i915: Always wait for flip_done, v2.") removed
> the call to wait_for_vblanks and replaced it with flip_done.
>
> Unfortunately legacy_cursor_update was unset too late, and the
> replacement call drm_ato
On Tue, 26 Sep 2017, Daniel Vetter wrote:
> Requested by Jani.
No, I didn't mean to request this. I meant, in patch 1, just do the
if [[ "${#drm_tip_repos[@]}" = "0" ]] || [[ "${#drm_tip_config[@]}" = "0" ]];
then
bit instead. That in itself will ensure the integration config is around
and con
On Thu, Sep 21, 2017 at 06:27:28AM -0700, Rodrigo Vivi wrote:
> On Thu, Sep 21, 2017 at 11:12:52AM +, Jani Nikula wrote:
> > On Wed, 20 Sep 2017, Rodrigo Vivi wrote:
> > > It seems Patchwork or SMTP servers are messing some patches
> > > and changing the original git's author name on git per "
On Tue, 2017-09-26 at 13:45 +0200, Daniel Vetter wrote:
> Suggested by Chris Wilson.
>
> v2: Fix typo in the error msg (Chris).
>
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Signed-off-by: Daniel Vetter
Jani suggested that this is bit late already, but I don't see why we
couldn't do both check
On Mon, Sep 25, 2017 at 02:48:41PM +0300, Jani Nikula wrote:
> On Mon, 25 Sep 2017, Petri Latvala wrote:
> > [[ a != b ]] is a bashism. As it's just comparing $1 to an empty
> > string, use -n with a normal [ ].
> >
> > /bin/sh is dash in CI.
>
> There's probably /bin/bash around anyway, but I'm
On Tue, 2017-09-26 at 10:32 +0100, Chris Wilson wrote:
> Michal wants to limit machines that can do preemption, which means that
> we no longer can assume that if we have a scheduler for execbuf, that
> implies we have preemption.
>
> v2: Try a capability mask instead
>
> Signed-off-by: Chris Wil
Quoting Joonas Lahtinen (2017-09-26 13:14:39)
> On Tue, 2017-09-26 at 10:32 +0100, Chris Wilson wrote:
> > Michal wants to limit machines that can do preemption, which means that
> > we no longer can assume that if we have a scheduler for execbuf, that
> > implies we have preemption.
> >
> > v2: T
== Series Details ==
Series: drm/i915: Use memset64() to prefill the GTT page
URL : https://patchwork.freedesktop.org/series/30892/
State : success
== Summary ==
Series 30892v1 drm/i915: Use memset64() to prefill the GTT page
https://patchwork.freedesktop.org/api/1.0/series/30892/revisions/1/m
Matthew Auld writes:
> Before we can enable 64K pages through the IPS bit, we must first enable
> it through MMIO, otherwise the page-walker will simply ignore it.
>
> v2: add comment mentioning that 64K is BDW+
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> ---
>
On Tue, Sep 26, 2017 at 02:01:46PM +0200, Daniel Vetter wrote:
> On Mon, Sep 25, 2017 at 02:48:41PM +0300, Jani Nikula wrote:
> > On Mon, 25 Sep 2017, Petri Latvala wrote:
> > > [[ a != b ]] is a bashism. As it's just comparing $1 to an empty
> > > string, use -n with a normal [ ].
> > >
> > > /bi
On 25/09/2017 18:37, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-09-25 16:15:38)
From: Tvrtko Ursulin
From: Chris Wilson
From: Tvrtko Ursulin
From: Dmitry Rogozhkin
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspac
On 25/09/2017 18:43, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-09-25 16:15:41)
From: Tvrtko Ursulin
Track total time requests have been executing on the hardware.
We add new kernel API to allow software tracking of time GPU
engines are spending executing requests.
Both per-engine and
On 25/09/2017 18:48, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-09-25 16:15:42)
From: Tvrtko Ursulin
We can use engine busy stats instead of the MMIO sampling timer
for better efficiency.
As minimum this saves period * num_engines / sec mmio reads,
and in a better case, when only engin
Suggested by Chris Wilson and Jani Nikula.
To do this properly we need to again push the reading of nightly.conf
to be after the basic sanity checks, like it was before
commit 12976ee32ae2cb97c7384ef6afde5f9076fc7d99
Author: Jani Nikula
Date: Fri Oct 28 12:40:46 2016 +0300
dim: switch to
On 25/09/2017 18:56, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-09-25 16:15:43)
From: Tvrtko Ursulin
This reduces the cost of the software engine busyness tracking
to a single no-op instruction when there are no listeners.
v2: Rebase and some comments.
v3: Rebase.
v4: Checkpatch fixes.
== Series Details ==
Series: series starting with [1/2] drm/dp: Add defines for latency in sink
URL : https://patchwork.freedesktop.org/series/30893/
State : success
== Summary ==
Series 30893v1 series starting with [1/2] drm/dp: Add defines for latency in
sink
https://patchwork.freedesktop.o
Chris Wilson writes:
> If we see the seqno stop progressing, we abandon the test for fear that
> the GPU died following the reset. However, during test teardown we still
> wait for the GPU to idle before continuing, but we have already
> confirmed that the GPU is dead. Furthermore, since we are i
== Series Details ==
Series: Add Plane Color Properties
URL : https://patchwork.freedesktop.org/series/30875/
State : success
== Summary ==
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-C-planes:
skip -> PASS (shard-hsw)
Subgroup p
Quoting Tvrtko Ursulin (2017-09-26 13:28:03)
> On 25/09/2017 18:37, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-09-25 16:15:38)
> >> + for_each_engine(engine, dev_priv, id) {
> >> + u32 current_seqno = intel_engine_get_seqno(engine);
> >> + u32 last_seqno
Quoting Mika Kuoppala (2017-09-26 13:48:17)
> Chris Wilson writes:
>
> > If we see the seqno stop progressing, we abandon the test for fear that
> > the GPU died following the reset. However, during test teardown we still
> > wait for the GPU to idle before continuing, but we have already
> > con
In the future I want to allow tests to commit more properties,
but for this to work I have to fix all properties to work better
with atomic commit. Instead of special casing each
property make a bitmask for all property changed flags, and try to
commit all properties.
Signed-off-by: Maarten Lankho
This test was flipping the primary plane instead of the sprite plane.
Flip the correct plane to make the test pass properly.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102691
Signed-off-by: Maarten Lankhorst
---
tests/kms_rotation_crc.c | 23 +--
1 file changed, 1
Instead of having to special case each property when it's added,
I want to make sure that any test can add arbitrary properties without
having to add too much code. Some of the members I want to expose directly,
and I also add a way to set a blob as property for planes and pipes,
which will be usef
Most of these tests have no reason to look at those members,
so try other ways of getting the information.
Signed-off-by: Maarten Lankhorst
---
lib/igt_kms.h | 21
tests/kms_atomic_transition.c | 117 +-
tests/kms_busy.c
Rename kms_pipe_color to kms_color, and rename the invalid tests to
pipe-invalid.
To prepare for adding support for plane color management.
Signed-off-by: Maarten Lankhorst
---
tests/Makefile.sources | 2 +-
tests/{kms_pipe_color.c => kms_color.c} | 4 ++--
2 files changed, 3 i
In the future I want to allow tests to commit more properties,
but for this to work I have to fix all properties to work better
with atomic commit. Instead of special casing each
property make a bitmask for all property changed flags, and try to
commit all properties.
Signed-off-by: Maarten Lankho
In the future I want to allow tests to commit more properties,
but for this to work I have to fix all properties to work better
with atomic commit. Instead of special casing each
property make a bitmask for all property changed flags, and try to
commit all properties.
This has been the most involv
Quoting Tvrtko Ursulin (2017-09-26 13:28:03)
>
> On 25/09/2017 18:37, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
> > b/drivers/gpu/drm/i915/i915_gem_request.c
> > index 4eb1a76731b2..19b8b31afbbc 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_request.c
> > +++ b/
Prepared helper i915_gem_runtime_resume to recreate gem setup.
Returning status from i915_gem_runtime_suspend and i915_gem_resume.
This will be placeholder for handling any errors from uC suspend/resume
in upcoming patches. Restructured the suspend/resume routines w.r.t setup
creation and rollback
This patch moves GuC suspend/resume handlers to corresponding GEM handlers
and orders them properly in the runtime and system suspend/resume flows.
It also adds documentation for GEM suspend/resume handlers.
i915_gem_restore_fences is GEM resumption task hence it is moved to
i915_gem_resume from i9
Prepared generic helpers intel_uc_suspend, intel_uc_resume,
intel_uc_runtime_suspend, intel_uc_runtime_resume. These are
called from respective GEM functions.
v2: Rebase w.r.t removal of GuC code restructuring.
v3: Calling intel_uc_resume from i915_gem_resume post resuming
i915 gem setup. This is
With this patch we disable GuC submission in i915_drm_suspend path.
This will destroy the client which will be setup back again. We also
reuse the complete sanitization done via intel_uc_runtime_suspend in
this path. Post i915_drm_resume, this state is recreated by
intel_uc_init_hw hence we need no
Apart from configuring interrupts, we need to update the ggtt invalidate
interface and GuC communication on suspend/resume. This functionality
can be reused for other suspend and reset paths.
v2: Rebase w.r.t removal of GuC code restructuring.
v3: Removed GuC specific helpers as tasks other than
Before i915 reset, we need to disable GuC submission and suspend GuC
operations as it is recreated during intel_uc_init_hw. We can't reuse the
intel_uc_suspend functionality as reset path already holds struct_mutex.
v2: Rebase w.r.t removal of GuC code restructuring. Updated reset_prepare
function
We ensure that GuC is completely suspended and client is destroyed
in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw
should just take care of cleanup,
hence s/intel_uc_fini_hw/intel_uc_cleanup. Correspondingly
we also updated as s/i915_guc_submission_fini/i915_guc_submission_cl
Currently GPU is reset at the end of suspend via i915_gem_sanitize.
On resume, GuC will not be loaded until intel_uc_init_hw happens
during GEM resume flow but action to exit sleep wll be send to GuC
considering the FW load status. To make sure we don't invoke that
action update GuC FW load status
On Tue, 2017-09-26 at 09:52 +0200, Greg Kroah-Hartman wrote:
> On Mon, Sep 25, 2017 at 07:47:17PM +0100, Matthew Auld wrote:
> > Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
> > moves us away from the shmemfs shm_mnt, and gives us the much needed
> > flexibility to do thi
On Tue, 26 Sep 2017, Daniel Vetter wrote:
> On Thu, Sep 21, 2017 at 06:27:28AM -0700, Rodrigo Vivi wrote:
>> On Thu, Sep 21, 2017 at 11:12:52AM +, Jani Nikula wrote:
>> > On Wed, 20 Sep 2017, Rodrigo Vivi wrote:
>> > > It seems Patchwork or SMTP servers are messing some patches
>> > > and cha
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Notify context-out for
lost requests
URL : https://patchwork.freedesktop.org/series/30895/
State : success
== Summary ==
Series 30895v1 series starting with [1/2] drm/i915/execlists: Notify
context-out for lost reque
And I have forgot to amend the ordering of tags cc, s-o-b etc. Sorry for
the same.
On 9/26/2017 6:54 PM, Sagar Arun Kamble wrote:
Prepared helper i915_gem_runtime_resume to recreate gem setup.
Returning status from i915_gem_runtime_suspend and i915_gem_resume.
This will be placeholder for hand
Fixed patch 1 based on review inputs from Michal Winiarski.
Rebased all patches. Updated ordering of cc, s-o-b, r-b tags for all patches.
Sagar Arun Kamble (8):
drm/i915: Create GEM runtime resume helper and handle GEM
suspend/resume errors
drm/i915: Update GEM suspend/resume flows conside
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