== Series Details ==
Series: drm/i915/cnp: set min brightness from VBT
URL : https://patchwork.freedesktop.org/series/30256/
State : success
== Summary ==
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252
fdo#102252 https://bugs.freedesktop.o
Op 12-09-17 om 22:11 schreef Pandiyan, Dhinakaran:
>
>
> On Tue, 2017-09-12 at 19:08 +, Pandiyan, Dhinakaran wrote:
>> On Tue, 2017-09-12 at 19:17 +0300, Ville Syrjälä wrote:
>>> On Tue, Sep 12, 2017 at 07:11:32PM +0300, Ville Syrjälä wrote:
On Tue, Sep 05, 2017 at 06:26:34PM -0700, Dhinak
Op 12-09-17 om 15:56 schreef Emil Velikov:
> On 12 September 2017 at 14:37, Maarten Lankhorst
> wrote:
>> When we want to make drm_atomic_commit interruptible, there are a lot of
>> places that call the lock function, which we don't have control over.
>>
>> Rather than trying to convert every sing
On Tue, 05 Sep 2017, Mika Kahola wrote:
> The revert patch solved the issue
>
> *ERROR* Video mode command 0x0041 send failed.
>
> on my setup with APL+MIPI/DSI single link combo.
>
> Tested-by: Mika Kahola
Pushed to dinq, thanks for the patch and testing. Alas, I failed to add
your Tested-b
On Tue, 12 Sep 2017, "Chauhan, Madhav" wrote:
>> -Original Message-
>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>> Vidya Srinivas
>> Sent: Tuesday, September 5, 2017 3:15 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Srinivas, Vidya
>> Subject: [Int
On Fri, 01 Sep 2017, Mika Kahola wrote:
> Error message indicating that the same MIPI command is sent consecutively
> is perhaps too strongly said. Let's replace that as a debug message instead.
>
> Signed-off-by: Mika Kahola
Pushed to dinq, thanks for the patch.
BR,
Jani.
> ---
> drivers/gpu
> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, September 13, 2017 1:39 PM
> To: Chauhan, Madhav ; Srinivas, Vidya
> ; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] Revert "drm/i915/bxt: Disable device ready
> before shutdown command"
>
> On Tue, 12 Sep 20
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, September 12, 2017 8:36 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
>
>On Tue, Sep 12, 2017 at
Use crtc->active directly instead. This is still not completely
optimal and needs fixing, but it's about as good as using
intel_crtc_active.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 19 ---
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gp
Calculate watermarks for gen4 and lower atomically.
Changes since first version:
- Address review feedback in first patch.
- Rename sr/hpll.yyy to sr/hpll.yyy_wm.
- Clarify comment in calculate gen4 watermarks semiatomically.
Maarten Lankhorst (6):
drm/i915: Calculate gen3- watermarks semi-atom
With the atomic watermark calculations calculate intermediary watermark
values and update the watermarks atomically.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel_drv.h | 5 +-
drivers/gpu/drm/i915/intel_pm.c | 241 ++
The gen3 watermark calculations are converted to atomic,
but the wm update calls are still done through the legacy
functions.
This will make it easier to bisect things if they go wrong.
CI was having issues on the kms_cursor_legacy tests with too
much debug info printed out, in order to reduce th
The legacy watermark infrastructure is now unused, so remove it.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_atomic.c | 2 -
drivers/gpu/drm/i915/intel_display.c | 71 ++--
drivers/gpu/drm/i915/int
We're already calculating the watermarks correctly, now we have to
program them too.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/
Gen4 watermark is handled same as gen3-. Calculate
the optimal watermarks atomically first, and program
it in the legacy helper.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 141
1 file changed, 100 insertions(+), 41 deletions(-)
The private PAT management is to support PPAT entry manipulation. Two
APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
and intel_ppat_put.
intel_ppat_get will search for an existing PPAT entry which perfectly
matches the required PPAT value. If not, it will try to allocate
Only PPAT entries 0/2/3/4 are using. Remove extra PPAT entry allocation
during initialization.
v8:
- Move ppat_index() into i915_gem_gtt.c. (Chris)
- Change the name of ppat_bits_to_index to ppat_index.
Suggested-by: Joonas Lahtinen
Signed-off-by: Zhi Wang
Cc: Ben Widawsky
Cc: Rodrigo Vivi
C
Remove the "INDEX" suffix from PPAT marcos as they are bits actually, not
indexes.
Suggested-by: Chris Wilson
Signed-off-by: Zhi Wang
Cc: Ben Widawsky
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
drivers/gpu/drm/i915/i915_ge
Introduce two live tests of private PAT management:
igt_ppat_init - This test is to check if all the PPAT configurations are
written into HW.
igt_ppat_get - This test performs several sub-tests on intel_ppat_get()
and intel_ppat_put().
The "perfect match" test case will try to get a PPAT entry w
From: Tvrtko Ursulin
From: Chris Wilson
From: Tvrtko Ursulin
From: Dmitry Rogozhkin
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system,
From: Michel Thierry
Not only the context image consist of two parts (the PPHWSP, and the
logical context state), but we also allocate a header at the start of
for sharing data with GuC. Thus every lrc looks like this:
| [guc] | [hwsp] [logical state] |
|<- our header ->|<- context
The engine provides a mirror of the CSB in the HWSP. If we use the
cacheable reads from the HWSP, we can shave off a few mmio reads per
context-switch interrupt (which are quite frequent!). Just removing a
couple of mmio is not enough to actually reduce any latency, but a small
reduction in overall
At the time of commit 1f767e02d69f ("drm/i915: HWS must be in the
mappable region for g33"), drm_mm insertion would often default to
placing a new object high in the zone forcing us to specify that certain
HWSP must be bound within the low mappable region. Since then, drm_mm
has gained more finesse
From: Tvrtko Ursulin
From: Chris Wilson
From: Tvrtko Ursulin
From: Dmitry Rogozhkin
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system,
From: Michel Thierry
Using the HWSP ggtt_offset to get the lrca offset is only correct if the
HWSP happens to be before it (when we reuse the PPHWSP of the kernel
context as the engine HWSP). Instead of making this assumption, get the
lrca offset from the kernel_context engine state.
And while l
== Series Details ==
Series: drm/i915: Convert gen4- watermarks to atomic. (rev4)
URL : https://patchwork.freedesktop.org/series/23954/
State : success
== Summary ==
Series 23954v4 drm/i915: Convert gen4- watermarks to atomic.
https://patchwork.freedesktop.org/api/1.0/series/23954/revisions/4/
The engine also provides a mirror of the CSB write pointer in the HWSP,
but not of our read pointer. To take advantage of this we need to
remember where we read up to on the last interrupt and continue off from
there. This poses a problem following a reset, as we don't know where
the hw will start
From: Daniele Ceraolo Spurio
On gen8+ we're currently using the PPHWSP of the kernel ctx as the
global HWSP. However, when the kernel ctx gets submitted (e.g. from
__intel_autoenable_gt_powersave) the HW will use that page as both
HWSP and PPHWSP. This causes a conflict in the register arena of t
On Tue, 12 Sep 2017, Ville Syrjälä wrote:
> On Tue, Sep 12, 2017 at 03:28:09PM +, Michal Wajdeczko wrote:
>> Our global struct with params is named exactly the same way
>> as new preferred name for the drm_i915_private function parameter.
>
> Preferred by some, perhaps not by others.
>
> I sus
On 12/09/2017 23:01, Rogozhkin, Dmitry V wrote:
On Tue, 2017-09-12 at 15:54 +0100, Tvrtko Ursulin wrote:
On 12/09/2017 03:03, Rogozhkin, Dmitry V wrote:
Hi,
Just tried v3 series. perf-stat works fine. From the IGT tests which I wrote
for i915 PMU
(https://patchwork.freedesktop.org/series/293
On Tue, 12 Sep 2017, Chris Wilson wrote:
> Quoting Ville Syrjälä (2017-09-12 16:36:57)
>> > -module_param_named(modeset, i915.modeset, int, 0400);
>> > +module_param_named(modeset, i915_params.modeset, int, 0400);
>
> We could clear the bulk of this patch
>
> #define i915_param_named(name, T, perm
On Tue, Sep 12, 2017 at 01:57:07PM +0100, Tvrtko Ursulin wrote:
>
> On 12/09/2017 13:45, Tvrtko Ursulin wrote:
> >
> > On 12/09/2017 13:37, Chris Wilson wrote:
> > > The DMC typifies the worst example of firmware: it overrides system
> > > behaviour and is fubar. When no displays are active, the
== Series Details ==
Series: series starting with [v16,1/4] drm/i915: Introduce private PAT
management
URL : https://patchwork.freedesktop.org/series/30264/
State : success
== Summary ==
Series 30264v1 series starting with [v16,1/4] drm/i915: Introduce private PAT
management
https://patchwor
v3: Don't pipe the output of intel_l3_parity, parse it's output
directly. (Petri)
v2: Check support before executing test.
Skip test only if intel_l3_parity tool tells us to skip. (Petri)
bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101650
Cc: Petri Latvala
Signed-off-by: Abdie
Commit b44d5c0c105a ("drm/i915: Always wait for flip_done, v2.") removed
the call to wait_for_vblanks and replaced it with flip_done.
Unfortunately legacy_cursor_update was unset too late, and the
replacement call drm_atomic_helper_wait_for_flip_done() was
a noop. Make sure that its unset before s
On Tue, 12 Sep 2017, Dhinakaran Pandiyan wrote:
> There is just only one caller now, which already checks for
> intel_dp->is_mst. So, remove this and fix some braces while at it.
>
> Signed-off-by: Dhinakaran Pandiyan
> ---
> drivers/gpu/drm/i915/intel_dp.c | 85
> --
== Series Details ==
Series: i915 PMU and engine busy stats (rev4)
URL : https://patchwork.freedesktop.org/series/27488/
State : warning
== Summary ==
Series 27488v4 i915 PMU and engine busy stats
https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/4/mbox/
Test kms_flip:
On Wed, 13 Sep 2017, "Lee, Shawn C" wrote:
> Min brightness value from vbt was missing for CNP platform.
> This setting have to refer backlight ic spec to restrict
> min backlight output. Without this restriction, driver would
> allow to configure lower brightness value and violate
> backlight ic
Tested-by: Marta Löfstedt
> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Wednesday, September 13, 2017 12:26 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Maarten Lankhorst ; Daniel Vetter
> ; Jani Nikula ; Lofstedt,
> Marta
> Subject:
Quoting Oscar Mateo (2017-09-12 22:36:37)
> Spare some comments and other small style changes.
>
> Suggested-by: Joonas Lahtinen
> Signed-off-by: Oscar Mateo
Series Reviewed-by: Chris Wilson
and pushed, thanks.
-Chris
___
Intel-gfx mailing list
Intel
Quoting Oscar Mateo (2017-09-12 23:50:08)
>
>
> On 09/12/2017 02:49 PM, Chris Wilson wrote:
> > The context descriptor is stored inside the per-engine context state, as
> > we only need to compute it once and access it frequently. However,
> > currently only intel_lrc.c has easy access, but i915_
== Series Details ==
Series: series starting with [1/6] drm/i915/lrc: Clarify the format of the
context image
URL : https://patchwork.freedesktop.org/series/30269/
State : success
== Summary ==
Series 30269v1 series starting with [1/6] drm/i915/lrc: Clarify the format of
the context image
ht
On Wed, Sep 13, 2017 at 12:24:18PM +0300, Abdiel Janulgue wrote:
> v3: Don't pipe the output of intel_l3_parity, parse it's output
> directly. (Petri)
>
> v2: Check support before executing test.
> Skip test only if intel_l3_parity tool tells us to skip. (Petri)
>
> bugzilla: https://bugs
On 09/13/2017 01:10 PM, Petri Latvala wrote:
> On Wed, Sep 13, 2017 at 12:24:18PM +0300, Abdiel Janulgue wrote:
>> v3: Don't pipe the output of intel_l3_parity, parse it's output
>> directly. (Petri)
>>
>> v2: Check support before executing test.
>> Skip test only if intel_l3_parity tool
== Series Details ==
Series: drm/i915: Unset legacy_cursor_update early in intel_atomic_commit
URL : https://patchwork.freedesktop.org/series/30273/
State : success
== Summary ==
Series 30273v1 drm/i915: Unset legacy_cursor_update early in intel_atomic_commit
https://patchwork.freedesktop.org/
From: Tvrtko Ursulin
From: Chris Wilson
From: Tvrtko Ursulin
From: Dmitry Rogozhkin
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system,
From: Tvrtko Ursulin
If only a subset of events is enabled we can afford to suspend
the sampling timer when the GPU is idle and so save some cycles
and power.
v2: Rebase and limit timer even more.
v3: Rebase.
v4: Rebase.
v5: Skip action if perf PMU failed to register.
Signed-off-by: Tvrtko Ursu
On Wed, Sep 13, 2017 at 09:32:40AM +0200, Maarten Lankhorst wrote:
> Op 12-09-17 om 22:11 schreef Pandiyan, Dhinakaran:
> >
> >
> > On Tue, 2017-09-12 at 19:08 +, Pandiyan, Dhinakaran wrote:
> >> On Tue, 2017-09-12 at 19:17 +0300, Ville Syrjälä wrote:
> >>> On Tue, Sep 12, 2017 at 07:11:32PM +0
Quoting Chris Wilson (2017-09-12 16:51:40)
> Quoting Joonas Lahtinen (2017-09-12 16:44:10)
> > Allow specifying the kernel module configuration via environment
> > variables. This allows enumerating the subtests of the kselftest
> > wrappers from sysroot directory.
> >
> > IGT_KMOD_CONFIG_PATHS=""
Both gem_linear_blits and gem_tiled_blit do not request the full 48b
GTT layout for their objects, restricting themselves to 4G. The
underlying test that they trigger eviction is unaffected by this
restriction, so we can simply reduce their memory requirements to fill
the low 4G GTT space and so al
If we wedged one engine with unready requests to a second engine
(blocked by waiting on requests from the first, using a dma-fence),
check that we propagate the -EIO to those in-flight requests.
Signed-off-by: Chris Wilson
---
tests/gem_eio.c | 89
Some overlap with gem_exec_fence, but confirm that light for waiting on
a fence (both native and external), that a request queued is also
flagged as EIO upon wedging.
Signed-off-by: Chris Wilson
---
tests/gem_eio.c | 41 +
1 file changed, 41 insertions(+)
As our hangcheck may exceed 10s to declare the device wedged, we need to
hold the plugging fence indefinitely. This makes using vgem as our input
fence unusable, so resort to using sw_sync. At the same time, we can
then check that the async result is also -EIO.
Bugzilla: https://bugs.freedesktop.o
This patch gets rid of Android support, deleting all the hacks and
moving code around to the places it belong.
Android build is not really maintained properly and rots rather fast.
With recent push for Meson here and Android going for Soong it will only
accelerate.
It's a good time to drop the il
This reverts commit d7d3f4e87b827152f00bdf89a67871736672b492
and gets rid of the config option from the meson.build.
It was needed only for the Android support.
Signed-off-by: Arkadiusz Hiler
---
configure.ac | 6 +-
lib/igt_aux.c | 35 +++
meson.build |
== Series Details ==
Series: i915 PMU and engine busy stats (rev6)
URL : https://patchwork.freedesktop.org/series/27488/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK inc
Op 13-09-17 om 12:37 schreef Ville Syrjälä:
> On Wed, Sep 13, 2017 at 09:32:40AM +0200, Maarten Lankhorst wrote:
>> Op 12-09-17 om 22:11 schreef Pandiyan, Dhinakaran:
>>>
>>> On Tue, 2017-09-12 at 19:08 +, Pandiyan, Dhinakaran wrote:
On Tue, 2017-09-12 at 19:17 +0300, Ville Syrjälä wrote:
v2: Updated property enum names.
Signed-off-by: Sagar Arun Kamble
---
tests/intel_perf_dapc.c | 75 +
1 file changed, 75 insertions(+)
diff --git a/tests/intel_perf_dapc.c b/tests/intel_perf_dapc.c
index 2d76e6f..7a6effa 100644
--- a/tests/intel_p
v2: Updated property enum names.
Signed-off-by: Sagar Arun Kamble
---
tests/intel_perf_dapc.c | 76 +
1 file changed, 76 insertions(+)
diff --git a/tests/intel_perf_dapc.c b/tests/intel_perf_dapc.c
index 23d6ffe..ccc37b6 100644
--- a/tests/intel_p
v2: Updated property enum names. Defined TAG_MASK, set_tag and get_tag
for local use.
Signed-off-by: Sagar Arun Kamble
---
tests/intel_perf_dapc.c | 142
1 file changed, 142 insertions(+)
diff --git a/tests/intel_perf_dapc.c b/tests/intel_perf_da
This tests different performance metrics being streamed by i915 driver.
This feature in i915 also referred as Driver Assisted Performance
Capture (DAPC) provides userspace an ability to sample the OA reports
at execbuf boundaries and associate other metadata like CTX ID, PID, TAG
with each sample.
This subtest verifies that the CS perf samples contains
proper HW context ID as captured through CONTEXT_PARAM_HW_ID.
v2: Updated property enum names.
Signed-off-by: Sagar Arun Kamble
---
lib/ioctl_wrappers.h| 1 +
tests/intel_perf_dapc.c | 102
v2: Updated the check for RC6 register value.
Updated property enum names. Defined local_I915_PERF_MMIO_NUM_MAX
and local_drm_i915_perf_mmio_list for local use.
Signed-off-by: Sagar Arun Kamble
---
tests/intel_perf_dapc.c | 266
1 file changed, 26
This series implements set of testcases for verifying data sampled
through i915 perf/DAPC feature. It tests validity of association of
OA with correct engine/stream, ctx id, pid, tag, timestamps, mmio
samples w.r.t execbuf begin and end. It also adds a testcase to
verify concurrent operation of two
v2: Updated property enum names.
Signed-off-by: Sagar Arun Kamble
---
tests/intel_perf_dapc.c | 211
1 file changed, 211 insertions(+)
diff --git a/tests/intel_perf_dapc.c b/tests/intel_perf_dapc.c
index 8644505..acc027b 100644
--- a/tests/intel_
Signed-off-by: Sagar Arun Kamble
---
tests/intel_perf_dapc.c | 152 +---
1 file changed, 143 insertions(+), 9 deletions(-)
diff --git a/tests/intel_perf_dapc.c b/tests/intel_perf_dapc.c
index acc027b..5d935bf 100644
--- a/tests/intel_perf_dapc.c
+++ b/
As realised by commit 9e3d6223d209 ("math64, timers: Fix 32bit
mul_u64_u32_shr() and friends"), GCC does not always generate ideal code
for performing a 32b x 32b multiply returning a 64b result (i.e. where
we idiomatically use u64 result = (u64)x * (u32)x). This catches a
couple of instances in th
As realised by commit 9e3d6223d209 ("math64, timers: Fix 32bit
mul_u64_u32_shr() and friends"), GCC does not always generate ideal code
for performing a 32b x 32b multiply returning a 64b result (i.e. where
we idiomatically use u64 result = (u64)x * (u32)x).
Signed-off-by: Chris Wilson
---
drive
The sgt iterators cause an
drivers/gpu/drm/i915/i915_gpu_error.c:846 i915_error_object_create() warn:
statement has no effect 7
everywhere they are used. If we change the code slightly, we can achieve
the same increment without altering the output or raising a warning.
textdata bss
== Series Details ==
Series: igt/gem_linear_blits: Compute GTT size using 4G limit (rev2)
URL : https://patchwork.freedesktop.org/series/30216/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
b6ea8b204c8a18af7098326522e8acaffb19dd7a tests/tools_test: Make su
From: Michał Winiarski
Originally removed in:
c1adab970348 ("drm/i915/guc: Remove failed doorbell stat from debugfs")
f1448a62a103 ("drm/i915/guc: Remove last submission result from debugfs")
Were accidentaly restored in:
925344ccc91d ("BackMerge tag 'v4.12-rc5' into drm-next")
We can also remo
---
drivers/gpu/drm/i915/i915_debugfs.c| 4 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 61 ++
drivers/gpu/drm/i915/intel_uc.h| 1 -
3 files changed, 13 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers
From: Michał Winiarski
To create an upper bound on number of GuC workitems, we need to change
the way that requests are being submitted. Rather than submitting each
request as an individual workitem, we can do coalescing in a similar way
we're handlig execlist submission ports. We also need to st
From: Michał Winiarski
Also:
Revert "drm/i915/guc: Assert that we switch between known ggtt->invalidate
functions"
This reverts commit 04f7b24eccdfae680a36e9825fe0d61dcd5ed528.
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20170912132226.25629-1-michal.winia
== Series Details ==
Series: series starting with [1/2] drm/i915: Use mul_u32_u32() for 32b x 32b ->
64b result
URL : https://patchwork.freedesktop.org/series/30279/
State : failure
== Summary ==
Series 30279v1 series starting with [1/2] drm/i915: Use mul_u32_u32() for 32b x
32b -> 64b resul
== Series Details ==
Series: drm/i915: Convert gen4- watermarks to atomic. (rev4)
URL : https://patchwork.freedesktop.org/series/23954/
State : failure
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test kms_flip:
== Series Details ==
Series: drm/i915: Squelch smatch warning for statement with no effect
URL : https://patchwork.freedesktop.org/series/30280/
State : success
== Summary ==
Series 30280v1 drm/i915: Squelch smatch warning for statement with no effect
https://patchwork.freedesktop.org/api/1.0/
Pull the two subtests together into the same subtest group as the
fixtures were repeated for both and so we can consolidate down to one.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
tests/prime_busy.c | 81 ++
1 file changed, 33 insertion
On Wed, Sep 13, 2017 at 12:46:47PM +0200, Maarten Lankhorst wrote:
> Op 13-09-17 om 12:37 schreef Ville Syrjälä:
> > On Wed, Sep 13, 2017 at 09:32:40AM +0200, Maarten Lankhorst wrote:
> >> Op 12-09-17 om 22:11 schreef Pandiyan, Dhinakaran:
> >>>
> >>> On Tue, 2017-09-12 at 19:08 +, Pandiyan, Dh
On Wed, Sep 13, 2017 at 11:51:53AM +0100, Chris Wilson wrote:
> As realised by commit 9e3d6223d209 ("math64, timers: Fix 32bit
> mul_u64_u32_shr() and friends"), GCC does not always generate ideal code
> for performing a 32b x 32b multiply returning a 64b result (i.e. where
> we idiomatically use u
On Wed, Sep 13, 2017 at 11:51:54AM +0100, Chris Wilson wrote:
> As realised by commit 9e3d6223d209 ("math64, timers: Fix 32bit
> mul_u64_u32_shr() and friends"), GCC does not always generate ideal code
> for performing a 32b x 32b multiply returning a 64b result (i.e. where
> we idiomatically use u
Split INTEL_GEN_MASK out of IS_GEN macro, and make it usable
within static declarations (unlike compound statements).
v2:
- s/combound/compound/ (Tvrtko)
- Fix whitespace (yes, we need automatic checkpatch.pl)
Signed-off-by: Joonas Lahtinen
Cc: Jani Nikula
Cc: Chris Wilson
Reviewed-by: Jani Ni
Convert to use the freshly available made INTEL_GEN_MASK for easier
grepping and improve function readability and clarify the UABI
documentation.
No functional changes.
v2:
- Lift GEM_BUG_ONs and use is_power_of_2 (Chris)
- Retain -EINVAL on bad flags behavior (Chris)
v3:
- Extract flags with 'e
Op 13-09-17 om 13:48 schreef Ville Syrjälä:
> On Wed, Sep 13, 2017 at 12:46:47PM +0200, Maarten Lankhorst wrote:
>> Op 13-09-17 om 12:37 schreef Ville Syrjälä:
>>> On Wed, Sep 13, 2017 at 09:32:40AM +0200, Maarten Lankhorst wrote:
Op 12-09-17 om 22:11 schreef Pandiyan, Dhinakaran:
> On Tue
== Series Details ==
Series: series starting with [1/4] drm/i915/guc: Remove obsolete comments and
remove unused variable
URL : https://patchwork.freedesktop.org/series/30282/
State : failure
== Summary ==
Series 30282v1 series starting with [1/4] drm/i915/guc: Remove obsolete
comments and r
On Wed, 2017-09-13 at 16:44 +0800, Zhi Wang wrote:
> The private PAT management is to support PPAT entry manipulation. Two
> APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
> and intel_ppat_put.
>
> intel_ppat_get will search for an existing PPAT entry which perfectly
> m
== Series Details ==
Series: series starting with [v7,1/2] drm/i915: Introduce INTEL_GEN_MASK
URL : https://patchwork.freedesktop.org/series/30291/
State : success
== Summary ==
Series 30291v1 series starting with [v7,1/2] drm/i915: Introduce INTEL_GEN_MASK
https://patchwork.freedesktop.org/ap
From: Tvrtko Ursulin
This reduces the cost of the software engine busyness tracking
to a single no-op instruction when there are no listeners.
v2: Rebase and some comments.
v3: Rebase.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 54 +++--
dr
== Series Details ==
Series: series starting with [v2,1/3] igt/gem_eio: inflight wedged requires
long plugging
URL : https://patchwork.freedesktop.org/series/30275/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
b6ea8b204c8a18af7098326522e8acaffb19dd7a tes
== Series Details ==
Series: series starting with [v16,1/4] drm/i915: Introduce private PAT
management
URL : https://patchwork.freedesktop.org/series/30264/
State : success
== Summary ==
Test prime_self_import:
Subgroup reimport-vs-gem_close-race:
fail -> PASS
On Wed, 2017-09-13 at 11:37 +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2017-09-12 16:51:40)
> > Quoting Joonas Lahtinen (2017-09-12 16:44:10)
> > > Allow specifying the kernel module configuration via environment
> > > variables. This allows enumerating the subtests of the kselftest
> > > w
Quoting Patchwork (2017-09-13 12:39:46)
> == Series Details ==
>
> Series: drm/i915: Squelch smatch warning for statement with no effect
> URL : https://patchwork.freedesktop.org/series/30280/
> State : success
>
> == Summary ==
>
> Series 30280v1 drm/i915: Squelch smatch warning for statement
On Tue, Sep 12, 2017 at 04:57:25PM -0700, Dhinakaran Pandiyan wrote:
> drm_dp_mst_topology_mgr_resume() fails if there are dpcd failures, so
> there's no need to try that again in _check_mst_status()
That commit message somehow doesn't seem to match this patch. You're not
removing anything from _c
== Series Details ==
Series: i915 PMU and engine busy stats (rev7)
URL : https://patchwork.freedesktop.org/series/27488/
State : success
== Summary ==
Series 27488v7 i915 PMU and engine busy stats
https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/7/mbox/
Test chamelium:
On Tue, Sep 12, 2017 at 04:57:26PM -0700, Dhinakaran Pandiyan wrote:
> There is just only one caller now, which already checks for
> intel_dp->is_mst. So, remove this and fix some braces while at it.
Hmm. So this depends on the subtle detail that
drm_dp_mst_topology_mgr_resume() will "fail" if did
The engine provides a mirror of the CSB in the HWSP. If we use the
cacheable reads from the HWSP, we can shave off a few mmio reads per
context-switch interrupt (which are quite frequent!). Just removing a
couple of mmio is not enough to actually reduce any latency, but a small
reduction in overall
== Series Details ==
Series: series starting with [1/6] drm/i915/lrc: Clarify the format of the
context image
URL : https://patchwork.freedesktop.org/series/30269/
State : success
== Summary ==
Test kms_flip:
Subgroup wf_vblank-vs-modeset:
dmesg-warn -> PASS (sha
== Series Details ==
Series: series starting with [1/2] igt: Remove Android support
URL : https://patchwork.freedesktop.org/series/30276/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
c718ba805208e55d675defe9b2a66852e2ae038c lib/igt_kmod: Allow specifying
Quoting Patchwork (2017-09-13 12:22:43)
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Use mul_u32_u32() for 32b x 32b
> -> 64b result
> URL : https://patchwork.freedesktop.org/series/30279/
> State : failure
>
> == Summary ==
>
> Series 30279v1 series starting with [
Chris Wilson writes:
> The engine provides a mirror of the CSB in the HWSP. If we use the
> cacheable reads from the HWSP, we can shave off a few mmio reads per
> context-switch interrupt (which are quite frequent!). Just removing a
> couple of mmio is not enough to actually reduce any latency, b
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