On Mon, 14 Aug 2017, Manasi Navare wrote:
> On Fri, Aug 11, 2017 at 02:39:07PM +0300, Jani Nikula wrote:
>> Ever since we've parsed VBT child devices, starting from 6acab15a7b0d
>> ("drm/i915: use the HDMI DDI buffer translations from VBT"), we've
>> ignored the child device information if more th
Op 14-08-17 om 22:32 schreef Daniel Vetter:
> The goal of these subtests was just to delay a kms operation a little
> bit. The goal wasn't to
> - spin until the operation was completed. That results in a gpu hang,
> and gpu hangs need igt_hang for safety.
> - complete it before the operation. Tha
On Mon, Aug 14, 2017 at 10:21:51AM -0700, Clint Taylor wrote:
>
>
> On 08/14/2017 07:40 AM, Daniel Vetter wrote:
> > On Thu, Aug 10, 2017 at 10:50:19AM -0700, clinton.a.tay...@intel.com wrote:
> > > From: Clint Taylor
> > >
> > > Current 50ms max threshold timing for an EDID read is very close
== Series Details ==
Series: drm/i915/HUC: Load HuC on Cannonlake
URL : https://patchwork.freedesktop.org/series/28767/
State : success
== Summary ==
Series 28767v1 drm/i915/HUC: Load HuC on Cannonlake
https://patchwork.freedesktop.org/api/1.0/series/28767/revisions/1/mbox/
Test kms_flip:
On Mon, Aug 14, 2017 at 09:18:44PM +0100, Chris Wilson wrote:
> If a test fails or skips early, it may not clean up after itself. In
> lieu of having a framework for test deconstructors, hook
> igt_terminate_spin_batches() into exit_subtest() itself so that we don't
> allow a recursive batch from a
On Mon, 12 Jun 2017, Manasi Navare wrote:
> Can this be merged? It has a r-b from Jani Nikula.
Both pushed, sorry for the delay.
BR,
Jani.
>
>
> On Thu, Jun 08, 2017 at 01:41:02PM -0700, Manasi Navare wrote:
>> This function now takes the link rate and lane ocunt to be validated
>> as an argum
On Tue, Aug 15, 2017 at 10:05:42AM +0200, Daniel Vetter wrote:
> On Mon, Aug 14, 2017 at 09:50:01PM +0100, Chris Wilson wrote:
> > Quoting Daniel Vetter (2017-08-14 21:32:00)
> > > The goal of these subtests was just to delay a kms operation a little
> > > bit. The goal wasn't to
> > > - spin until
On Tue, 2017-04-18 at 19:07 +0900, Michel Dänzer wrote:
> From: Michel Dänzer
>
> This allows making the master screen's pixmap_dirty_list entries
> explicitly reflect that we're now tracking the root window instead of
> the screen pixmap, in order to allow Present page flipping on master
> outpu
== Series Details ==
Series: drm/i915: KW fix in intel_dsi_dcs_backlight.c (rev2)
URL : https://patchwork.freedesktop.org/series/28291/
State : success
== Summary ==
Series 28291v2 drm/i915: KW fix in intel_dsi_dcs_backlight.c
https://patchwork.freedesktop.org/api/1.0/series/28291/revisions/2/
On Mon, Aug 14, 2017 at 10:00:24PM +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2017-08-14 21:18:27)
> > Supplement dmesg with the function call graph to try and help identify
> > why the suspend failed. On the other hand, it may be very noisy and
> > perturb the system due to its overhead...
On Mon, Aug 14, 2017 at 09:18:35PM +0100, Chris Wilson wrote:
> If we tell the machine to reset but they are disallowed, we will leave
> the system in a wedged state, preventing the majority of subsequent
> tests.
> ---
> tests/drv_hangman.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --g
Quoting Daniel Vetter (2017-08-15 09:52:21)
> On Mon, Aug 14, 2017 at 09:18:35PM +0100, Chris Wilson wrote:
> > If we tell the machine to reset but they are disallowed, we will leave
> > the system in a wedged state, preventing the majority of subsequent
> > tests.
> > ---
> > tests/drv_hangman.c
Quoting Daniel Vetter (2017-08-15 09:01:55)
> On Mon, Aug 14, 2017 at 09:18:44PM +0100, Chris Wilson wrote:
> > If a test fails or skips early, it may not clean up after itself. In
> > lieu of having a framework for test deconstructors, hook
> > igt_terminate_spin_batches() into exit_subtest() itse
== Series Details ==
Series: drm/i915: Return -EPERM when i915_gem_mmap_ioctl handling prime objects
URL : https://patchwork.freedesktop.org/series/28784/
State : success
== Summary ==
Series 28784v1 drm/i915: Return -EPERM when i915_gem_mmap_ioctl handling prime
objects
https://patchwork.fre
These tests do not tell the kernel they can use the upper 48bits of
aperture space, and cause eviction on the low 4G just as effectively
exercising the evict code.
Signed-off-by: Chris Wilson
---
tests/gem_evict_alignment.c | 35 +--
tests/gem_evict_everything.c
Quoting Imre Deak (2017-08-14 16:15:29)
> GCC 4.4 can't cope with anonymous union initializers which seems to be a
> bug in that version (see the Reference) and is fixed since GCC version
> 4.6. A workaround which is also used elsewhere in the kernel for the
> same purpose is to wrap the initializa
On Tue, Aug 15, 2017 at 10:42 AM, Tina Zhang wrote:
> Prime objects have no backing filp to GEM mmap pages from. So, for Prime
> objects, such operation is not permitted.
EPERM is when you don't have enough permissions, but it's possible
(e.g. a feature requiring root, or drm master). -EINVAL is
Op 15-08-17 om 12:02 schreef Daniel Vetter:
> On Tue, Aug 15, 2017 at 11:57:06AM +0200, Maarten Lankhorst wrote:
>> The last part of drm_atomic_check_only is testing whether we need to
>> fail with -EINVAL when modeset is not allowed, but forgets to return
>> the value when atomic_check() fails fir
== Series Details ==
Series: drm/atomic: If the atomic check fails, return its value first
URL : https://patchwork.freedesktop.org/series/28790/
State : success
== Summary ==
Series 28790v1 drm/atomic: If the atomic check fails, return its value first
https://patchwork.freedesktop.org/api/1.0/
This silently failed for me, and I had no idea what's happening.
Signed-off-by: Daniel Vetter
---
dim | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/dim b/dim
index 85866488e0e0..48e076eba00e 100755
--- a/dim
+++ b/dim
@@ -503,7 +503,14 @@ function update
== Series Details ==
Series: igt/gem_evict_(alignment, everything): Limit to low 4G
URL : https://patchwork.freedesktop.org/series/28796/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
8d2ad9d4d4ba35e1ca8a4989347825fa8e8c0072 tests/kms_flip: fix spin_batch
On Thu, Aug 03, 2017 at 10:31:11AM -0700, Rodrigo Vivi wrote:
> On Thu, Aug 3, 2017 at 4:13 AM, David Weinehall
> wrote:
> > On Wed, Aug 02, 2017 at 12:24:33PM -0700, Rodrigo Vivi wrote:
> >> On Wed, Aug 2, 2017 at 10:34 AM, Praveen Paneri
> >> wrote:
> >> > This WA is required when decoupled fre
Quoting Daniel Vetter (2017-08-15 11:49:51)
> On Tue, Aug 15, 2017 at 10:42 AM, Tina Zhang wrote:
> > Prime objects have no backing filp to GEM mmap pages from. So, for Prime
> > objects, such operation is not permitted.
>
> EPERM is when you don't have enough permissions, but it's possible
> (e.
Introduce a new function to retiring all shadow PPGTTs of a vGPU.
The shadow PPPGTs of a vGPU need to be invalidated if a guest modifies the
virtual private PPAT since the mapping between the virtual PPAT indexes
and the shadow PPAT indexes will be re-built after a guest writes a new
virtual PPAT
This patchset introduces dynamic PPAT managment for GVT-g.
Since different VM can have different PPAT configurations, GVT-g needs
to map the virtual private PAT configuration into the physical private
PAT between different VMs.
More background of this patchset can be found at:
https://lists.freed
This patch introduces private PAT operations for GEN8.
The "get_pat_value" operation offers an API to get a PPAT entry from the
virtual or physical PPAT MMIO registers. Similar with the "get_pat_value",
the "set_pat_value" operation offers the API to write a PPAT entry back to
PPAT MMIO registers.
Translate virtual PPAT indexes into physical PPAT indexes, according to
the mapping between virtual PPAT indexes and physical PPAT indexes during
building a PPGTT shadow page table.
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/gvt/gtt.c | 23 +++
1 file changed, 23 insert
Introduce PPAT MMIO handlers. The mapping between virtual PPAT indexes
and physical PPAT indexes needs to be re-built after a guest write its
virtual PPAT configuration.
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/gvt/gtt.c | 26 ++
drivers/gpu/drm/i915/gvt/gtt.
On Tue, 2017-08-15 at 16:42 +0800, Tina Zhang wrote:
> Prime objects have no backing filp to GEM mmap pages from. So, for Prime
> objects, such operation is not permitted.
>
> v1:
> - Separate this patch from dma-buf patch set. (Joonas)
>
> Signed-off-by: Tina Zhang
> Cc: Chris Wilson
> Cc: Joo
== Series Details ==
Series: Introduce dynamic PPAT managment for GVT-g
URL : https://patchwork.freedesktop.org/series/28804/
State : success
== Summary ==
Series 28804v1 Introduce dynamic PPAT managment for GVT-g
https://patchwork.freedesktop.org/api/1.0/series/28804/revisions/1/mbox/
Test k
On Tue, Aug 15, 2017 at 3:18 PM, Chris Wilson wrote:
> Quoting Daniel Vetter (2017-08-15 11:49:51)
>> On Tue, Aug 15, 2017 at 10:42 AM, Tina Zhang wrote:
>> > Prime objects have no backing filp to GEM mmap pages from. So, for Prime
>> > objects, such operation is not permitted.
>>
>> EPERM is whe
On Fri, 2017-08-11 at 12:11 +0100, Chris Wilson wrote:
> Another month, another story in the cache coherency saga. This time, we
> come to the realisation that i915_gem_object_is_coherent() has been
> reporting whether we can read from the target without requiring a cache
> invalidate; but we were
On Tue, Jul 25, 2017 at 05:28:15PM +0800, Tina Zhang wrote:
> The RGB 64-bit 16:16:16:16 float pixel format is needed by windows
> guest VM. This patch is to introduce the format to drm.
>
> v1:
> Suggested by Ville to submit this patch to dri-devel.
>
> Signed-off-by: Xiaoguang Chen
> Signed-of
Quoting Joonas Lahtinen (2017-08-15 15:34:38)
> On Fri, 2017-08-11 at 12:11 +0100, Chris Wilson wrote:
> > Another month, another story in the cache coherency saga. This time, we
> > come to the realisation that i915_gem_object_is_coherent() has been
> > reporting whether we can read from the targe
On Sat, 2017-08-12 at 12:51 +0100, Chris Wilson wrote:
> In the next patch, we want to reduce the lock coverage within the
> shrinker, and one of the dangerous walks we have is over obj->vma_list.
> We are only walking the obj->vma_list in order to check whether it has
> been permanently pinned by
From: Jason Ekstrand
This commit adds support for waiting on or signaling DRM syncobjs as
part of execbuf. It does so by hijacking the currently unused cliprects
pointer to instead point to an array of i915_gem_exec_fence structs
which containe a DRM syncobj and a flags parameter which specifies
Quoting Joonas Lahtinen (2017-08-15 15:56:07)
> On Sat, 2017-08-12 at 12:51 +0100, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index b0738d2b2a7f..874562bd59ae 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/g
Quoting Michel Thierry (2017-08-14 15:13:59)
> On 8/8/2017 1:08 AM, Daniel Vetter wrote:
> > @@ -3458,12 +3462,14 @@ void intel_prepare_reset(struct drm_i915_private
> > *dev_priv)
> > !gpu_reset_clobbers_display(dev_priv))
> > return;
> >
> > - /* We have a modeset
== Series Details ==
Series: drm/i915: Add support for drm syncobjs
URL : https://patchwork.freedesktop.org/series/28811/
State : success
== Summary ==
Series 28811v1 drm/i915: Add support for drm syncobjs
https://patchwork.freedesktop.org/api/1.0/series/28811/revisions/1/mbox/
Test kms_flip:
Quoting Patchwork (2017-08-15 16:44:39)
> == Series Details ==
>
> Series: drm/i915: Add support for drm syncobjs
> URL : https://patchwork.freedesktop.org/series/28811/
> State : success
>
> == Summary ==
>
> Series 28811v1 drm/i915: Add support for drm syncobjs
> https://patchwork.freedeskto
In the next patch, we want to extend use of the global pin counter for
semi-permanent pinning of context/ring objects. Given that we plan to
extend the usage to encompass a disparate set of objects, we want a name
that reflects both and should entail less confusion.
Signed-off-by: Chris Wilson
--
== Series Details ==
Series: MAINTAINERS: drm/i915 has a new maintainer team
URL : https://patchwork.freedesktop.org/series/28814/
State : warning
== Summary ==
Series 28814v1 MAINTAINERS: drm/i915 has a new maintainer team
https://patchwork.freedesktop.org/api/1.0/series/28814/revisions/1/mbo
Quoting Joonas Lahtinen (2017-08-14 11:42:05)
> On Fri, 2017-08-11 at 11:57 +0100, Chris Wilson wrote:
> > The wait-ioctl is optionally supplied a timeout with nanosecond
> > precision in a s64 field. We use nsecs_to_jiffies64() to convert that
> > into the jiffies consumed by the scheduler, but in
== Series Details ==
Series: series starting with [1/6] drm/i915: Refactor testing obj->mm.pages
(rev3)
URL : https://patchwork.freedesktop.org/series/28709/
State : failure
== Summary ==
Series 28709v3 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/28709/revisio
On 07/05/2017 06:02 PM, Rodrigo Vivi wrote:
Let's inherit workarounds from previous platforms that
according to wa_database and BSpec are still valid for
Cannonlake.
v2: Add missed workarounds.
v3: Rebase
v4: Remove bad chunk that was added to rc6 disable. (Ander)
Also remove A0 W/a that
On 08/15/2017 12:58 AM, Daniel Vetter wrote:
On Mon, Aug 14, 2017 at 10:21:51AM -0700, Clint Taylor wrote:
On 08/14/2017 07:40 AM, Daniel Vetter wrote:
On Thu, Aug 10, 2017 at 10:50:19AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Current 50ms max threshold timing for an E
On 07/05/2017 06:02 PM, Rodrigo Vivi wrote:
WA to disable replay buffer destination buffer arbitration optimization.
Same Wa on previous platforms has a different name:
WaToEnableHwFixForPushConstHWBug
Signed-off-by: Rodrigo Vivi
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_
On 07/05/2017 06:02 PM, Rodrigo Vivi wrote:
This bit enables hardware that will change the approximation used for distances
calculations for AA wide lines so that they are rendered more accurately.
The default value for this bit leaves the legacy behavior. There is no good
reason to not enable
We can't mix 64K and 4K pte's in the same page-table, so for now we
align 64K objects to 2M to avoid any potential mixing. This is
potentially wasteful but in reality shouldn't be too bad since this only
applies to the virtual address space of a 48b PPGTT.
v2: don't separate logically connected op
Support inserting 2M pages into the 48b PPGTT.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gt
For the 48b PPGTT try to align the vma start address to the required
page size boundary to guarantee we use said page size in the gtt. If we
are dealing with multiple page sizes, we can't guarantee anything and
just align to the largest. For soft pinning and objects which need to be
tightly packed
Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
moves us away from the shmemfs shm_mnt, and gives us the much needed
flexibility to do things like set our own mount options, namely huge=
which should allow us to enable the use of transparent-huge-pages for
our shmem backed o
Before we can enable 64K pages through the IPS bit, we must first enable
it through MMIO, otherwise the page-walker will simply ignore it.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 11 +++
drivers/gpu/drm/i915/i915_reg.h | 3
Enable transparent-huge-pages through gemfs by mounting with
huge=within_size.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gemfs.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gemfs.c
b/driver
In preparation for huge gtt pages expose a page_size_mask as part of the
device info, to indicate the page sizes supported by the HW. Currently
only 4K is supported.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/g
Currently gvt gtt handling doesn't support huge page entries, so disable
for now.
v2: remove useless 48b PPGTT check
Suggested-by: Zhenyu Wang
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Zhenyu Wang
---
drivers/gpu/drm/i915/i915_gem.c | 8
1 file changed, 8
When SW enables the use of 2M/1G pages, it must disable the GTT cache.
v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
v3: explicitly check that the system does support 2M/1G pages
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i91
Now that we support multiple page sizes for the ppgtt, it would be
useful to track the real usage for debugging purposes.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c| 10 ++
drivers/gpu/drm/i915/i915_gem_object.h | 10 +++
For gen8+ platforms which support the 48b PPGTT, enable platform level
support for 2M pages. Also enable for mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 6 --
drivers/gpu/drm/i915/selftests/mock_gem_d
Try to mix sg page sizes for 4K, 64K and 2M pages.
v2: s/BIT(x) >> 12/BIT(x) >> PAGE_SHIFT/
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/selftests/scatterlist.c | 15 +++
1 file changed, 15 insertions(+)
dif
For gen8+ enable platforms which support the 48b PPGTT, enable support
for 1G pages. Also enable for mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 6 --
drivers/gpu/drm/i915/selftests/mock_gem_device.c
Support inserting 1G gtt pages into the 48b PPGTT.
v2: sanity check sg->length against page_size
v3: don't recalculate rem on each loop
whitespace breakup
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 78 +++
Good to know, mostly for debugging purposes.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 42 +
1 file changed, 38 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
v2: mock test page support configurations and add MI_STORE_DWORD test
v3: run all mockable huge page tests on all platforms via the mock_device
v4: add pin_update regression test
various improvements suggested by Chris
v4: fix issues reported by kbuild
test single sg spanning multiple pa
Quoting Matthew Auld (2017-08-15 19:11:58)
> static int i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
> {
> struct sg_table *pages;
> + unsigned int sg_mask = 0;
>
> GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
>
> @@ -2485,11 +2514,11 @@ static in
== Series Details ==
Series: huge gtt pages (rev6)
URL : https://patchwork.freedesktop.org/series/25118/
State : warning
== Summary ==
Series 25118v6 huge gtt pages
https://patchwork.freedesktop.org/api/1.0/series/25118/revisions/6/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kerne
Quoting Matthew Auld (2017-08-15 19:11:59)
> @@ -517,6 +527,8 @@ i915_vma_remove(struct i915_vma *vma)
> GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
> GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND));
>
> + vma->vm->clear_pages(vma);
> +
> dr
Quoting Matthew Auld (2017-08-15 19:12:02)
> + /* To support 64K PTE's we need to first enable the use of the
> +* Intermediate-Page-Size(IPS) bit of the PDE field via some magical
> +* mmio, otherwise the page-walker will simply ignore the IPS bit.
> This
> +* should
This patch fixes the DP AUX CH timeouts observed during CI runs causing
CI Failures on a specific PCI device. This issue was fixed previously
by adding a quirk but looks like we need to increase this delay even more
in order to get rid all the DP AUX CH timeouts.
Fixes: c99a259b4b5192ba ("drm/i915
Quoting Matthew Auld (2017-08-15 19:12:06)
> Before we can fully enable 64K pages, we need to first support a 64K
> scratch page if we intend to support the case where we have object sizes
> < 2M, since any scratch PTE must also point to a 64K region. Without
> this our 64K usage is limited to obj
== Series Details ==
Series: drm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX CH
timeouts
URL : https://patchwork.freedesktop.org/series/28824/
State : success
== Summary ==
Series 28824v1 drm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX
CH timeouts
https://patchw
Sending as RFC to get feedback on what would be the correct behaviour of
the driver and, therefore, if the test is valid.
We do a wait while holding the mutex if we are adding a request and figure
out that there is no more space in the ring buffer.
Is that considered a bug? In the current driver a
On Sat, 12 Aug 2017 12:34:37 +0100 Chris Wilson
wrote:
> Some shrinkers may only be able to free a bunch of objects at a time, and
> so free more than the requested nr_to_scan in one pass. Account for the
> extra freed objects against the total number of objects we intend to
> free, otherwise we
Quoting Antonio Argenziano (2017-08-15 22:44:21)
> Sending as RFC to get feedback on what would be the correct behaviour of
> the driver and, therefore, if the test is valid.
It's not a preemption specific bug. It is fair to say that any client
blocking any other client over a non-contended resour
Tests for the new flag were added in 3685dabb0ab25eb1.
Cc: Daniel Vetter
Cc: Chris Wilson
---
tests/gem_exec_params.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/gem_exec_params.c b/tests/gem_exec_params.c
index ba6d67c..5b72072 100644
--- a/tests/gem_exec_params
On Tue, Aug 15, 2017 at 4:14 AM, Oscar Mateo wrote:
>
>
> On 07/05/2017 06:02 PM, Rodrigo Vivi wrote:
>>
>> This bit enables hardware that will change the approximation used for
>> distances
>> calculations for AA wide lines so that they are rendered more accurately.
>>
>> The default value for th
== Series Details ==
Series: tests/gem_exec_params: Update the invalid-flag subtest for FENCE_ARRAY
URL : https://patchwork.freedesktop.org/series/28831/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
8d2ad9d4d4ba35e1ca8a4989347825fa8e8c0072 tests/kms_flip:
Quoting Andrew Morton (2017-08-15 23:30:10)
> On Sat, 12 Aug 2017 12:34:37 +0100 Chris Wilson
> wrote:
>
> > Some shrinkers may only be able to free a bunch of objects at a time, and
> > so free more than the requested nr_to_scan in one pass. Account for the
> > extra freed objects against the t
For the set of execbuf flags who by definition are based on whether or
not the kernel supports that feature, the ultimate arbiter of whether or
not the kernel accepts the flag is the kernel. The negative tests were
second guessing the kernel and not checking behaviour. Indeed, the tests
failed quit
On Tue, Aug 15, 2017 at 3:54 AM, Oscar Mateo wrote:
>
>
> On 07/05/2017 06:02 PM, Rodrigo Vivi wrote:
>>
>> Let's inherit workarounds from previous platforms that
>> according to wa_database and BSpec are still valid for
>> Cannonlake.
>>
>> v2: Add missed workarounds.
>> v3: Rebase
>> v4: Remove
WA to disable replay buffer destination buffer arbitration optimization.
Same Wa on previous platforms has a different name:
WaToEnableHwFixForPushConstHWBug
Signed-off-by: Rodrigo Vivi
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_engine_cs.c | 4
1 file changed, 4 insertion
Let's inherit workarounds from previous platforms that
according to wa_database and BSpec are still valid for
Cannonlake.
v2: Add missed workarounds.
v3: Rebase
v4: Remove bad chunk that was added to rc6 disable. (Ander)
Also remove A0 W/a that are not needed anymore.
v5: Rebase on top of CFL.
Quoting Antonio Argenziano (2017-08-15 22:44:21)
> Sending as RFC to get feedback on what would be the correct behaviour of
> the driver and, therefore, if the test is valid.
>
> We do a wait while holding the mutex if we are adding a request and figure
> out that there is no more space in the rin
== Series Details ==
Series: series starting with [1/4] drm/i915/cnl: Introduce initial Cannonlake
Workarounds.
URL : https://patchwork.freedesktop.org/series/28837/
State : success
== Summary ==
Series 28837v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/28837
On Tue, Aug 15, 2017 at 9:58 AM, Jim Bride wrote:
> On Wed, Aug 09, 2017 at 01:40:00PM -0700, Jim Bride wrote:
>> According to the eDP spec, when the count field in TEST_SINK_MISC
>> increments then the six bytes of sink CRC information in the DPCD
>> should be valid. Unfortunately, this doesn't
Merged to dinq.
On Tue, Aug 15, 2017 at 4:55 PM, Patchwork
wrote:
> == Series Details ==
>
> Series: drm/i915/cnl: Setup PAT Index.
> URL : https://patchwork.freedesktop.org/series/28838/
> State : success
>
> == Summary ==
>
> Series 28838v1 drm/i915/cnl: Setup PAT Index.
> https://patchwork.
== Series Details ==
Series: drm/i915: Expose a debugfs to acquire the BKL^Wstruct_mutex
URL : https://patchwork.freedesktop.org/series/28839/
State : success
== Summary ==
Series 28839v1 drm/i915: Expose a debugfs to acquire the BKL^Wstruct_mutex
https://patchwork.freedesktop.org/api/1.0/seri
This patch is doing nover except reordering functions to highlight
changes in the next patch.
Change-Id: I0cd298780503ae8f6f8035b86c59fc8b5191356b
Signed-off-by: Dmitry Rogozhkin
Cc: Tvrtko Ursulin
Cc: Peter Zijlstra
---
drivers/gpu/drm/i915/i915_pmu.c | 180 ---
These patches depend on the RFC patches enabling i915 PMU from Tvrtko:
https://patchwork.freedesktop.org/series/27488/
Thus, CI failure to build them is expected. I think that my patches should
be squeashed in Tvrtko's one actually.
The first patch simply reorders functions and does nothing now
When LSPCON support was extended to CNL
one part was missed on lspcon_init.
So, instead of adding check per platform on lspcon_init
let's use HAS_LSPCON that is already there for that
purpose.
Fixes: ff15947e0f02 ("drm/i915/cnl: LSPCON support is gen9+")
Cc: Shashank Sharma
Cc: Paulo Zanoni
Sig
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Tuesday, August 15, 2017 10:50 PM
> To: Zhang, Tina
> Cc: intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; ville.syrj...@
> -Original Message-
> From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
> Behalf Of Chris Wilson
> Sent: Tuesday, August 15, 2017 11:02 PM
> To: Daniel Vetter
> Cc: intel-gfx ; intel-gvt-dev d...@lists.freedesktop.org>; Zhang, Tina
> Subject: Re: [Intel-gfx]
On 2017.08.16 05:31:14 +0800, Zhi Wang wrote:
> Introduce PPAT MMIO handlers. The mapping between virtual PPAT indexes
> and physical PPAT indexes needs to be re-built after a guest write its
> virtual PPAT configuration.
>
> Signed-off-by: Zhi Wang
> ---
> drivers/gpu/drm/i915/gvt/gtt.c |
Yes. They will be removed after this feature checked-in. The discussion
before is at least host should provide all collections of cache
attribute so we will have a partial match.
On 08/16/17 13:18, Zhenyu Wang wrote:
On 2017.08.16 05:31:14 +0800, Zhi Wang wrote:
Introduce PPAT MMIO handlers.
patch looks good to me,
Reviewed-by: Mahesh Kumar
On Saturday 12 August 2017 05:08 AM, Rodrigo Vivi wrote:
comment. Code matches recent spec.
v3: Rebase on top of latest skl code using new fp16.16 and
fixing a logic issue. Auto rebase bot has apparently
made some bad decisions that
-Original Message-
From: Zhenyu Wang [mailto:zhen...@linux.intel.com]
Sent: Wednesday, August 16, 2017 2:13 PM
To: Wang, Zhi A
Cc: intel-gfx@lists.freedesktop.org; joonas.lahti...@linux.intel.com;
intel-gvt-...@lists.freedesktop.org; ch...@chris-wilson.co.uk
Subject: Re: [RFC 6/7] drm/
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