These tables are used on voltage wswing sequence initialization
on Cannonlake.
It is a complete new format now in use by the voltage swing team,
not following any other standard in use by any other platform.
Also the registers are different as well. So let's redefine
the translation table for Cann
There is no platform specific change needed for LSPCON
support on Cannonlake. So let's make it gen9+.
Cc: Shashank Sharma
Signed-off-by: Rodrigo Vivi
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
This is an important part of the DDI initalization as well as
for changing the voltage during DisplayPort link training.
This new sequence for Cannonlake is more like Broxton style
but still with different registers, different table and
different steps.
v2: Do not write to DW4_GRP to avoid overwr
This are the registers and bits needed for the voltage swing
sequence on Cannonlake.
v2: Remove CL_DW5 that was wrongly defined.
v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
Change DW2 swing sel upper and lower macros to do the
bit selection instead of definint a table that doesn'
As Geminilake scalers Cannonlake also don't need and don't have
the "high quality" mode programming.
Cc: Ander Conselvan de Oliveira
Signed-off-by: Rodrigo Vivi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_atomic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Ville Syrjälä
Add support for changing the cdclk frequency on CNL. Again, quite
similar to BXT, but there are some annoying differences which means
trying to share more code might not be feasible:
* PLL ratio now lives in the PLL enable register
* pcode came from SKL, not from BXT
We suppo
One of the steps for PLL (un)initialization is to (un)map
the correspondent DDI that is actually using that PLL.
So, let's do this step following the places already stablished
and used so far, although spec put this as part of PLL
initialization sequences.
v2: Use proper prefix on bits names as s
Since we have HAS_CSR tied to the platform definition
let's use this instead of checking per platform.
One less thing to worry when adding support to new platforms.
Signed-off-by: Rodrigo Vivi
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+)
Also new registers can have different mmio offsets
per different lane per port.
v2: Use _PICK as PORT3 instead of creating a new
macro with if per port.
v3: Use _PICK directly on MMIO_PORT6. While MMIO_PORT
isn't flexible enough let's continue with MMIO_PORT6
as we have MMIO_PORT3.
Cc
From: Clint Taylor
vswing programming sequence step 2 requires the Loadgen_select bit to
be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and
lane width. Implemented the change that was marked as FIXME in the
driver.
v2: (Rodrigo) checkpatch fixes.
Signed-off-by: Clint Taylor
\o/
Reviewed-by: Rodrigo Vivi
On Thu, Jun 8, 2017 at 4:48 AM, Ander Conselvan de Oliveira
wrote:
> Geminilake is now included in CI, making it part of the pre-merge
> criteria. The support should be in good enough shape, so let's remove
> the alpha_support flag.
>
> Signed-off-by: Ander Conselv
== Series Details ==
Series: series starting with [01/17] drm/i915/cnl: Implement
.get_display_clock_speed() for CNL
URL : https://patchwork.freedesktop.org/series/25511/
State : success
== Summary ==
Series 25511v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/
From: "Kahola, Mika"
Enable wrpll computation for Cannonlake platform to support
pll's required for HDMI output. The patch contains the following features
- compute Cannonlake port clock programming
dividers P, Q, and K.
- compute PLL parameters for Cannonlake. These parameters
set the value
Matches pseudo code in BSpec.
Reviewed-by: Clint Taylor
On 06/08/2017 04:03 PM, Rodrigo Vivi wrote:
From: "Kahola, Mika"
Enable wrpll computation for Cannonlake platform to support
pll's required for HDMI output. The patch contains the following features
- compute Cannonlake port clock pro
Add PCI Ids for U Skus of Coffeelake.
v2: Use intel_coffeelake_gt3_info, in accordance to-
Rodrigo's patch:
v3: rebased
v3: Remove unused INTEL_CFL_IDS(Rodrigo).
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 7 +++
Add PCI Ids for H Sku by following the BSpec.
v2: Remove unused INTEL_CFL_IDS.(Rodrigo).
v3: Add missing IDs(Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 5 +
2 files changed, 6 insertions(+)
diff --g
Add PCI Ids for S Sku following the BSpec.
v2: Remove the unused INTEL_CFL_IDS.(Rodrigo)
v3: Add missing IDs(Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 8
2 files changed, 9 insertions(+)
diff
On Thu, Jun 08, 2017 at 03:03:17PM -0700, Rodrigo Vivi wrote:
> Also new registers can have different mmio offsets
> per different lane per port.
>
> v2: Use _PICK as PORT3 instead of creating a new
> macro with if per port.
> v3: Use _PICK directly on MMIO_PORT6. While MMIO_PORT
> isn't f
Coffee Lake reuses Kabylake's HUC firmware.
v2: Change Coffeelake to Coffee Lake
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/inte
Reviewed-by: Rodrigo Vivi
On Thu, 2017-06-08 at 16:41 -0700, Anusha Srivatsa wrote:
> Add PCI Ids for H Sku by following the BSpec.
>
> v2: Remove unused INTEL_CFL_IDS.(Rodrigo).
> v3: Add missing IDs(Rodrigo)
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i91
Coffee Lake reuses Kabylake's GuC.
v2: Change Coffeelake to Coffee Lake
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/d
On Thu, 2017-06-08 at 16:41 -0700, Anusha Srivatsa wrote:
> Add PCI Ids for S Sku following the BSpec.
>
> v2: Remove the unused INTEL_CFL_IDS.(Rodrigo)
> v3: Add missing IDs(Rodrigo)
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> includ
Reviewed-by: Rodrigo Vivi
On Thu, 2017-06-08 at 16:41 -0700, Anusha Srivatsa wrote:
> Add PCI Ids for U Skus of Coffeelake.
>
> v2: Use intel_coffeelake_gt3_info, in accordance to-
> Rodrigo's patch:
>
> v3: rebased
>
> v3: Remove unused INTEL_CFL_IDS(Rodrigo).
>
> Cc: Rodrigo Vivi
> Signed
On Thu, 2017-06-08 at 16:53 -0700, Manasi Navare wrote:
> On Thu, Jun 08, 2017 at 03:03:17PM -0700, Rodrigo Vivi wrote:
> > Also new registers can have different mmio offsets
> > per different lane per port.
> >
> > v2: Use _PICK as PORT3 instead of creating a new
> > macro with if per port.
>
== Series Details ==
Series: series starting with [1/3] drm/i915/cfl: Add Coffee Lake PCI IDs for S
Skus.
URL : https://patchwork.freedesktop.org/series/25516/
State : success
== Summary ==
Series 25516v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25516/revis
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Load GuC on Coffee Lake
URL : https://patchwork.freedesktop.org/series/25517/
State : success
== Summary ==
Series 25517v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25517/revisions/1/mbox/
Hi Dave,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/i915/intel_engine_cs.c
between commit:
ef6c4d75e353 ("drm/i915: fix warning for unused variable")
from the drm-intel-fixes tree and commit:
a8e9a419c337 ("drm/i915: Lie and treat all engines as idle if
Enable the guest i915 full ppgtt functionality when host can provide this
capability. vgt_caps is introduced to guest i915 driver to get the vgpu
capabilities from the device model. VGT_CPAS_FULL_PPGTT is one of the
capabilities type to let guest i915 dirver know that the guest i915 full
ppgtt is s
== Series Details ==
Series: drm/i915: Enable guest i915 full ppgtt functionality (rev3)
URL : https://patchwork.freedesktop.org/series/24774/
State : success
== Summary ==
Series 24774v3 drm/i915: Enable guest i915 full ppgtt functionality
https://patchwork.freedesktop.org/api/1.0/series/2477
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/kvmgt.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 1ae0b40..3c6a02b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
++
v7->v8:
1) refine framebuffer decoder code
2) fix a bug in decoding primary plane
v6->v7:
1) release dma-buf related allocations in dma-buf's associated release
function.
2) refine ioctl interface for querying plane info or create dma-buf
3) refine framebuffer decoder code
4) the patch series is b
OpRegion is needed to support display related operation for
intel vgpu.
A vfio device region is added to intel vgpu to deliver the
host OpRegion information to user space so user space can
construct the OpRegion for vgpu.
Signed-off-by: Bing Niu
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/dr
decode frambuffer attributes of primary, cursor and sprite plane
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/Makefile | 3 +-
drivers/gpu/drm/i915/gvt/display.c| 2 +-
drivers/gpu/drm/i915/gvt/display.h| 2 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 425 ++
Here we defined a new ioctl to create a fd for a vfio device based on
the input type. Now only one type is supported that is a dma-buf
management fd.
Two ioctls are defined for the dma-buf management fd: query the vfio
vgpu's plane information and create a dma-buf for a plane.
Signed-off-by: Xiaog
dmabuf for GVT-g can be exported to users who can use the dmabuf to show
the desktop of vm which use intel vgpu.
Currently we provide query and create new dmabuf operations.
Users of dmabuf can cache some created dmabufs and related information
such as the framebuffer's address, size, tiling mode
User space should create the management fd for the dma-buf operation first.
Then user can query the plane information and create dma-buf if necessary
using the management fd.
Signed-off-by: Xiaoguang Chen
Tested-by: Kechen Lu
---
drivers/gpu/drm/i915/gvt/dmabuf.c| 37 -
drivers/gpu
== Series Details ==
Series: drm/i915/gvt: dma-buf support for GVT-g (rev8)
URL : https://patchwork.freedesktop.org/series/23686/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CH
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