== Series Details ==
Series: drm/i915: Unify GT* and GT3 definitions (rev3)
URL : https://patchwork.freedesktop.org/series/25299/
State : success
== Summary ==
Series 25299v3 drm/i915: Unify GT* and GT3 definitions
https://patchwork.freedesktop.org/api/1.0/series/25299/revisions/3/mbox/
Test
== Series Details ==
Series: drm/i915: Remove unecessary PORT3 definition. (rev2)
URL : https://patchwork.freedesktop.org/series/25313/
State : success
== Summary ==
Series 25313v2 drm/i915: Remove unecessary PORT3 definition.
https://patchwork.freedesktop.org/api/1.0/series/25313/revisions/2/
== Series Details ==
Series: series starting with [1/5] drm/i915/cfl: Introduce Coffee Lake platform
definition.
URL : https://patchwork.freedesktop.org/series/25352/
State : success
== Summary ==
Series 25352v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/2535
Here we defined a new ioctl to create a fd for a vfio device based on
the input type. Now only one type is supported that is a dma-buf
management fd.
Two ioctls are defined for the dma-buf management fd: query the vfio
vgpu's plane information and create a dma-buf for a plane.
Signed-off-by: Xiaog
v6->v7:
1) release dma-buf related allocations in dma-buf's associated release
function.
2) refine ioctl interface for querying plane info or create dma-buf
3) refine framebuffer decoder code
4) the patch series is based on 4.12.0-rc1
v5->v6:
1) align the dma-buf life cycle with the vfio device.
2
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/kvmgt.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 1ae0b40..3c6a02b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
++
decode frambuffer attributes of primary, cursor and sprite plane
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/Makefile | 3 +-
drivers/gpu/drm/i915/gvt/display.c| 2 +-
drivers/gpu/drm/i915/gvt/display.h| 2 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 439 ++
dmabuf for GVT-g can be exported to users who can use the dmabuf to show
the desktop of vm which use intel vgpu.
Currently we provide query and create new dmabuf operations.
Users of dmabuf can cache some created dmabufs and related information
such as the framebuffer's address, size, tiling mode
User space should create the management fd for the dma-buf operation first.
Then user can query the plane information and create dma-buf if necessary
using the management fd.
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/drm/i915/gvt/dmabuf.c| 37 -
drivers/gpu/drm/i915/gvt/dmabuf.h
OpRegion is needed to support display related operation for
intel vgpu.
A vfio device region is added to intel vgpu to deliver the
host OpRegion information to user space so user space can
construct the OpRegion for vgpu.
Signed-off-by: Bing Niu
Signed-off-by: Xiaoguang Chen
---
drivers/gpu/dr
== Series Details ==
Series: series starting with [01/11] drm/i915/cnl: Introduce Cannonlake
platform defition.
URL : https://patchwork.freedesktop.org/series/25355/
State : success
== Summary ==
Series 25355v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25355
On Tue, 2017-06-06 at 14:23 +0100, Chris Wilson wrote:
> Quoting Mika Kahola (2017-06-06 13:33:14)
> >
> > On Tue, 2017-06-06 at 15:27 +0300, Ville Syrjälä wrote:
> > >
> > > On Tue, Jun 06, 2017 at 03:20:46PM +0300, Mika Kahola wrote:
> > > >
> > > >
> > > > It has been noticed by our CI BAT t
== Series Details ==
Series: series starting with [1/3] drm/i915/cfl: Add Coffee Lake PCI IDs for U
Sku.
URL : https://patchwork.freedesktop.org/series/25364/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK inclu
== Series Details ==
Series: Adding NV12 support for SKL display
URL : https://patchwork.freedesktop.org/series/25377/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK inclu
== Series Details ==
Series: drm/i915/gvt: dma-buf support for GVT-g (rev7)
URL : https://patchwork.freedesktop.org/series/23686/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CH
On Tue, 06 Jun 2017, Imre Deak wrote:
> On Tue, Jun 06, 2017 at 05:58:43PM +0300, Bloomfield, Jon wrote:
>> > -Original Message-
>> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
>> > Of Imre Deak
>> > Sent: Tuesday, June 6, 2017 5:34 AM
>> > To: Jani Nikula
> -Original Message-
> From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
> Behalf Of Xiaoguang Chen
> Sent: Wednesday, June 7, 2017 3:45 PM
> To: alex.william...@redhat.com; kra...@redhat.com; ch...@chris-wilson.co.uk;
> intel-gfx@lists.freedesktop.org; linux-ker
Currently, BXT_PP is hardcoded with value '0'.
It practically disabled eDP backlight on MRB (BXT) platform.
This patch will tell which BXT_PP registers (there are two set of PP_CONTROL in
the spec)
to be used as defined in VBT (Video Bios Timing table) and this will enabled eDP
backlight controll
On 2017.06.05 16:40:09 +0300, Joonas Lahtinen wrote:
>
> On ma, 2017-06-05 at 11:00 +0800, Zhenyu Wang wrote:
> > Current it's strictly checked if PVINFO version matches 1.0
> > for GVT-g i915 guest which doesn't help for compatibility at
> > all and forces GVT-g host can't extend PVINFO easily wi
== Series Details ==
Series: drm/i915/bxt: Enable VBT based BL control for DP (rev3)
URL : https://patchwork.freedesktop.org/series/25323/
State : failure
== Summary ==
Series 25323v3 drm/i915/bxt: Enable VBT based BL control for DP
https://patchwork.freedesktop.org/api/1.0/series/25323/revisi
On 2017.06.05 14:55:41 +0800, Tina Zhang wrote:
> Enable the guest i915 full ppgtt functionality when host can provide this
> capability. vgt_caps is introduced to guest i915 driver to get the vgpu
> capabilities from the device model. VGT_CPAS_FULL_PPGTT is one of the
> capabilities type to let gu
On Wed, 2017-06-07 at 06:25 +, Williams, Dan J wrote:
> On Mon, 2017-06-05 at 23:22 +0200, Christoph Hellwig wrote:
> > On Mon, Jun 05, 2017 at 08:10:42PM +0300, Andy Shevchenko wrote:
> > >
> > > I hope Christoph can replace old version of this series with new
> > > one in
> > > his uuid bran
In previous GEN default Interlace mode enabled is IF-ID mode, but IF-ID
mode has many limitations in SKL. This mode doesn't support y-tiling,
90-270 rotation is not supported & YUV-420 planar source pixel formats
are not supported with above mode.
This patch make changes to use PF-ID Interlace mod
On Wed, Jun 07, 2017 at 12:37:51PM +0300, Andy Shevchenko wrote:
> It think we may fold it.
Yes, I'll fold it and delcare the tree stable late tonight my time.
> Besides that we might need the following fix as well.
Yeah. Another reasone why buffer.pointer should be a void pointer.
On Wed, Jun 07, 2017 at 06:25:46AM +, Williams, Dan J wrote:
> With one compile fix below the 'acpi' branch works for me. Please feel
> free to add:
The mail seems to contain garbage that can't be applied, but I just
applied the changes manually.
___
On 05/06/2017 11:26, Chris Wilson wrote:
Originally we would enable and disable the breadcrumb interrupt
immediately on demand. This was slow enough to have a large impact
(>30%) on tasks that hopped between engines. However, by using a shadow
to keep the irq alive for an extra interrupt (see co
Quoting Mika Kahola (2017-06-07 09:00:10)
> On Tue, 2017-06-06 at 14:23 +0100, Chris Wilson wrote:
> > Quoting Mika Kahola (2017-06-06 13:33:14)
> > >
> > > On Tue, 2017-06-06 at 15:27 +0300, Ville Syrjälä wrote:
> > > >
> > > > On Tue, Jun 06, 2017 at 03:20:46PM +0300, Mika Kahola wrote:
> > > >
This patch series is adding NV12 support for Skylake display after
rebasing on latest drm-intel-nightly. Initial series of the patches
can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Feature has been currently tested with custom linux based test tool
IGT te
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
Link: https://patchwork.kernel.org/patch/6426161/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Si
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
Link: https://patchwork.kernel.org/patch/6426201/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/g
From: Ville Syrjälä
SKL+ display engine can scan out certain kinds of compressed surfaces
produced by the render engine. This involved telling the display engine
the location of the color control surfae (CCS) which describes which
parts of the main surface are compressed and which are not. The lo
From: Ville Syrjälä
SKL+ display engine can scan out certain kinds of compressed surfaces
produced by the render engine. This involved telling the display engine
the location of the color control surfae (CCS) which describes
which parts of the main surface are compressed and which are not. The
lo
From: Chandra Konduru
This patch updates scaler max limit support for NV12
Link: https://patchwork.kernel.org/patch/6426191/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 26 ++
dri
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
Link: https://patchwork.kernel.org/patch/6426221/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Ma
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function and
made it available for both primary and sprite planes
v2:
-Use intel_ prefix for format_is_yuv (Ville)
Link: https://patchwork.kernel.org/patch/6426181/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed
This reverts commit 7c8703fb02b248c2bcf9756bba8812bcfe7ed5d3.
If we expect it to fail until we find a solution, let the hw fail and
continue to track the known failure in CI/bugs.
Cc: Martin Peres
---
tests/kms_cursor_legacy.c | 18 +-
1 file changed, 1 insertion(+), 17 deletion
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
Link: https://patchwork.kernel.org/patch/6426211/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_sprite.c | 24
Hi Vidya,
I guess you didn't see my submission of this series a couple of weeks
ago, which included some fixes.
On 7 June 2017 at 11:41, Vidya Srinivas wrote:
> Link: https://patchwork.kernel.org/patch/9637253/
The Patchwork link can be dropped when submitting by mail.
> +static const struct dr
On Wed, 2017-06-07 at 11:24 +0100, Chris Wilson wrote:
> Quoting Mika Kahola (2017-06-07 09:00:10)
> >
> > On Tue, 2017-06-06 at 14:23 +0100, Chris Wilson wrote:
> > >
> > > Quoting Mika Kahola (2017-06-06 13:33:14)
> > > >
> > > >
> > > > On Tue, 2017-06-06 at 15:27 +0300, Ville Syrjälä wrote:
== Series Details ==
Series: drm/i915/skl+: enable PF_ID interlace mode in SKL
URL : https://patchwork.freedesktop.org/series/25397/
State : success
== Summary ==
Series 25397v1 drm/i915/skl+: enable PF_ID interlace mode in SKL
https://patchwork.freedesktop.org/api/1.0/series/25397/revisions/1
Hi Vidya,
On 7 June 2017 at 11:41, Vidya Srinivas wrote:
> + case I915_FORMAT_MOD_Y_TILED_CCS:
> + if (plane == 1)
> + return 128;
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN2(dev_priv) || HAS_
On Tue, Jun 06, 2017 at 02:56:23PM -0700, Rodrigo Vivi wrote:
> When addressing Imre's comments I noticed:
>
> error: ‘cnl_set_cdclk’ defined but not used [-Werror=unused-function]
> static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
> ^
> cc1: all warnings being treated as
On 07/06/17 13:34, Chris Wilson wrote:
This reverts commit 7c8703fb02b248c2bcf9756bba8812bcfe7ed5d3.
If we expect it to fail until we find a solution, let the hw fail and
continue to track the known failure in CI/bugs.
Cc: Martin Peres
I agree, the kernel/HW is broken.
However, this fix is
== Series Details ==
Series: drm/i915/bxt: Enable VBT based BL control for DP (rev3)
URL : https://patchwork.freedesktop.org/series/25323/
State : success
== Summary ==
Series 25323v3 drm/i915/bxt: Enable VBT based BL control for DP
https://patchwork.freedesktop.org/api/1.0/series/25323/revisi
On Wed, Jun 07, 2017 at 01:59:05PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 06, 2017 at 02:56:23PM -0700, Rodrigo Vivi wrote:
> > When addressing Imre's comments I noticed:
> >
> > error: ‘cnl_set_cdclk’ defined but not used [-Werror=unused-function]
> > static void cnl_set_cdclk(struct drm_i915_
On 31/05/17 17:45, Martin Peres wrote:
On 31/05/17 16:55, Chris Wilson wrote:
On Wed, May 31, 2017 at 04:44:41PM +0300, Martin Peres wrote:
On 31/05/17 15:42, Chris Wilson wrote:
On Wed, May 31, 2017 at 01:40:00PM +0300, Martin Peres wrote:
On 26/05/17 14:48, Chris Wilson wrote:
If we do a sh
Quoting Martin Peres (2017-06-07 12:13:24)
> How about this: When the modeset call fails, check if the link-status is
> BAD. If not, return a FAIL. If so, force a full re-probe, pick the
> highest available mode and try again. Do this until a mode applies. If
> no modes are left, just SKIP the t
From: Chandra Konduru
This patch updates scaler max limit support for NV12
Link: https://patchwork.kernel.org/patch/6426191/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 26 ++
dri
From: Ville Syrjälä
SKL+ display engine can scan out certain kinds of compressed surfaces
produced by the render engine. This involved telling the display engine
the location of the color control surfae (CCS) which describes
which parts of the main surface are compressed and which are not. The
lo
This patch series is adding NV12 support for Skylake display after
rebasing on latest drm-intel-nightly. Initial series of the patches
can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Feature has been currently tested with custom linux based test tool
IGT te
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
Link: https://patchwork.kernel.org/patch/6426161/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Si
From: Ville Syrjälä
SKL+ display engine can scan out certain kinds of compressed surfaces
produced by the render engine. This involved telling the display engine
the location of the color control surfae (CCS) which describes which
parts of the main surface are compressed and which are not. The lo
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
Link: https://patchwork.kernel.org/patch/6426201/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/g
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function and
made it available for both primary and sprite planes
v2:
-Use intel_ prefix for format_is_yuv (Ville)
Link: https://patchwork.kernel.org/patch/6426181/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
Link: https://patchwork.kernel.org/patch/6426211/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_sprite.c | 24
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
Link: https://patchwork.kernel.org/patch/6426221/
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Ma
Hi Vidya,
On 7 June 2017 at 12:40, Vidya Srinivas wrote:
> +static const struct drm_format_info ccs_formats[] = {
> + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2, .cpp =
> { 4, 1, }, .hsub = 16, .vsub = 8, },
> + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_pl
On 07/06/17 14:33, Chris Wilson wrote:
Quoting Martin Peres (2017-06-07 12:13:24)
How about this: When the modeset call fails, check if the link-status is
BAD. If not, return a FAIL. If so, force a full re-probe, pick the
highest available mode and try again. Do this until a mode applies. If
no
Martin, the kms_flip test already skips when we have entered the "no modes
available" state.
I talked with Petri a bit about this and we sort of agree that IGT should only
skip tests on an "expected" lack of HW/SW requirements. IGT should not skip on
bad states that has been created by the test
On Wed, Jun 07, 2017 at 12:44:47PM +0100, Daniel Stone wrote:
> Hi Vidya,
>
> On 7 June 2017 at 12:40, Vidya Srinivas wrote:
> > +static const struct drm_format_info ccs_formats[] = {
> > + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2, .cpp
> > = { 4, 1, }, .hsub = 16, .vs
On Mon, 15 May 2017, Jani Nikula wrote:
> The following commits have been marked as Cc: stable or fixing something
> in v4.12-rc1 or earlier, but failed to cherry-pick to
> drm-intel-fixes. Please see if they are worth backporting, and please do
> so if they are.
Update:
d96a7d2adb04 ("drm/i915:
> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Wednesday, June 7, 2017 1:16 AM
> To: Deak, Imre ; Bloomfield, Jon
>
> Cc: intel-gfx@lists.freedesktop.org; Mustaffa, Mustamin B
>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/bxt: Enable VBT based BL con
On Wed, Jun 7, 2017 at 4:09 AM, Ville Syrjälä
wrote:
> On Wed, Jun 07, 2017 at 01:59:05PM +0300, Ville Syrjälä wrote:
>> On Tue, Jun 06, 2017 at 02:56:23PM -0700, Rodrigo Vivi wrote:
>> > When addressing Imre's comments I noticed:
>> >
>> > error: ‘cnl_set_cdclk’ defined but not used [-Werror=unus
Hi,
On 7 June 2017 at 13:53, Ville Syrjälä wrote:
> On Wed, Jun 07, 2017 at 12:44:47PM +0100, Daniel Stone wrote:
>> /*
>> * We don't require any
>> * CCS block size alignment of the fb under the assumption that the
>> * hardware will handle things correctly of only a single pixel
>> * gets t
Replaced custom load implementation with lib counterpart.
Signed-off-by: Radoslaw Szwichtenberg
Cc: Chris Wilson
Cc: Arkadiusz Hiler
---
tests/pm_rps.c | 80 --
1 file changed, 16 insertions(+), 64 deletions(-)
diff --git a/tests/pm_rps.
Patches merged to dinq.
Thanks for patches and reviews.
On Tue, Jun 6, 2017 at 1:30 PM, Rodrigo Vivi wrote:
> The workaround added in
> commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
> equests left on by DMC/KVMR")
> needs to be applied on Cannonlake as well.
>
> So let's assume
patch merged to dinq with the fixed spelling.
Thanks for the review
On Tue, Jun 6, 2017 at 11:14 AM, Manasi Navare
wrote:
> Just a very tiny nitpick about correction in the
> spelling of "unnecessary" in the title.
>
> Other than that
>
> Reviewed-by: Manasi Navare
>
> On Tue, Jun 06, 2017 at 09
patch merged to dinq
thanks for all comments and reviews
On Tue, Jun 6, 2017 at 2:58 PM, Srivatsa, Anusha
wrote:
>
>
>>-Original Message-
>>From: Vivi, Rodrigo
>>Sent: Tuesday, June 6, 2017 9:06 AM
>>To: intel-gfx@lists.freedesktop.org
>>Cc: Vivi, Rodrigo ; Chris Wilson >wilson.co.uk>; Sr
On Wed, Jun 07, 2017 at 03:24:58PM +0100, Daniel Stone wrote:
> Hi,
>
> On 7 June 2017 at 13:53, Ville Syrjälä wrote:
> > On Wed, Jun 07, 2017 at 12:44:47PM +0100, Daniel Stone wrote:
> >> /*
> >> * We don't require any
> >> * CCS block size alignment of the fb under the assumption that the
> >
Hi,
On 7 June 2017 at 16:33, Ville Syrjälä wrote:
> On Wed, Jun 07, 2017 at 03:24:58PM +0100, Daniel Stone wrote:
>> On 7 June 2017 at 13:53, Ville Syrjälä wrote:
>> > Anyways, I'll have to revisit the the offsets[] thing because people
>> > didn't like my original linear offset idea, and it doe
On Wed, Jun 07, 2017 at 04:48:06PM +0100, Daniel Stone wrote:
> Hi,
>
> On 7 June 2017 at 16:33, Ville Syrjälä wrote:
> > On Wed, Jun 07, 2017 at 03:24:58PM +0100, Daniel Stone wrote:
> >> On 7 June 2017 at 13:53, Ville Syrjälä
> >> wrote:
> >> > Anyways, I'll have to revisit the the offsets[]
Hi,
On 7 June 2017 at 17:28, Ville Syrjälä wrote:
> On Wed, Jun 07, 2017 at 04:48:06PM +0100, Daniel Stone wrote:
>> It does, and I have correct CCS output (tested by displaying frames
>> either as Y_CCS, or as plain Y; correct display with the former and
>> visibly showing an incomplete primary
On Tue, 2017-06-06 at 12:19 -0700, Rodrigo Vivi wrote:
> So let's force it on the virtual detection.
>
> Also it is still the only silicon for now on this PCH,
> so WARN otherwise.
>
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4
>
From: Clint Taylor
RGB565 Pixel format planes can now be rotated at 90 and 270 degrees
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/
On Wed, Jun 07, 2017 at 10:45:25AM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> RGB565 Pixel format planes can now be rotated at 90 and 270 degrees
"now" == since when?
>
> Signed-off-by: Clint Taylor
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 11 ---
>
== Series Details ==
Series: drm/i915/glk: RGB565 planes now allow 90/270 rotation
URL : https://patchwork.freedesktop.org/series/25417/
State : success
== Summary ==
Series 25417v1 drm/i915/glk: RGB565 planes now allow 90/270 rotation
https://patchwork.freedesktop.org/api/1.0/series/25417/rev
On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> All here is pretty much like Kabylake.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915
Add PCI Ids for U Skus of Coffeelake.
v2: Use intel_coffeelake_gt3_info, in accordance to-
Rodrigo's patch:
https://patchwork.freedesktop.org/patch/160148/
v3: Renove unused INTEL_CFL_IDS(Rodrigo).
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
incl
Add PCI Ids for H Sku by following the BSpec.
v2: Remove unused INTEL_CFL_IDS.(Rodrigo).
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_
Add PCI Ids for S Sku following the BSpec.
v2: Remove the unused INTEL_CFL_IDS.(Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915
== Series Details ==
Series: series starting with [1/3] drm/i915/cfl: Add Coffee Lake PCI IDs for S
Skus.
URL : https://patchwork.freedesktop.org/series/25419/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK incl
Coffeelake reuses Kabylake's HUC firmware.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index f5eb18d0e..6145fa0 100644
Coffeelake reuses Kabylake's GuC.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i9
On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> The whole Display engine for Coffee Lake is pretty much
> identical to the Kabylake. For this reason let's reuse
> all display related production workardounds here even though
Are these all the display workarounds we have or is this patch ju
On 06/07/2017 10:55 AM, Ville Syrjälä wrote:
On Wed, Jun 07, 2017 at 10:45:25AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
RGB565 Pixel format planes can now be rotated at 90 and 270 degrees
"now" == since when?
GLK, I will update the commit message to be more specific.
Daniel Vetter writes:
> On Mon, Apr 10, 2017 at 06:24:32PM -0700, Eric Anholt wrote:
>> This successfully catches vc4's lack of dmabuf fencing.
>>
>> Signed-off-by: Eric Anholt
>> ---
>>
>> Has anyone looked into shared infrastructure for tests to do
>> KMS/dmabuf/etc. things with a generic "g
Quoting Chris Wilson (2017-05-04 12:55:08)
> Replace the large comment about requiring the powerwell for
> intel_uncore_arm_unclaimed_mmio_detection() by moving the arming of the
> mmio error detection into the powerwell held for modesetting. Thereby
> also accomplishing the goal of only arming the
Hi Rodrigo,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc4 next-20170607]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnl
Hi Anusha,
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.12-rc4 next-20170607]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Anusha-Srivatsa/drm-i915-cfl
Hi Anusha,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc4 next-20170607]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Anusha-Srivatsa/drm-i915-cfl-Add
Hi Rodrigo,
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.12-rc4 next-20170607]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnl
On Wed, 2017-06-07 at 11:24 -0700, Anusha Srivatsa wrote:
> Add PCI Ids for S Sku following the BSpec.
>
> v2: Remove the unused INTEL_CFL_IDS.(Rodrigo)
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h | 4 ++
On Wed, 2017-06-07 at 11:24 -0700, Anusha Srivatsa wrote:
> Add PCI Ids for H Sku by following the BSpec.
>
> v2: Remove unused INTEL_CFL_IDS.(Rodrigo).
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h | 3 ++
Reviewed-by: Rodrigo Vivi
On Wed, 2017-06-07 at 11:24 -0700, Anusha Srivatsa wrote:
> Add PCI Ids for U Skus of Coffeelake.
>
> v2: Use intel_coffeelake_gt3_info, in accordance to-
> Rodrigo's patch:
> https://patchwork.freedesktop.org/patch/160148/
>
> v3: Renove unused INTEL_CFL_IDS(Rodrigo).
With this approach we need to have in mind that any new kbl firmware
version needs to be validated on both kbl and cfl by our QA before
publishing.
However the differences are really minimal if not 0. So publishing 2
identical files with different names maybe doesn't make any sense and
wouldn't sa
Same comments I put on GuC patch are valid here...
Reviewed-by: Rodrigo Vivi
On Wed, 2017-06-07 at 11:43 -0700, Anusha Srivatsa wrote:
> Coffeelake reuses Kabylake's HUC firmware.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_huc.c | 2 +-
> 1 file
On Wed, 2017-06-07 at 18:44 +, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> > The whole Display engine for Coffee Lake is pretty much
> > identical to the Kabylake. For this reason let's reuse
> > all display related production workardounds here even th
On Wed, 2017-06-07 at 18:04 +, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> > All here is pretty much like Kabylake.
> >
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
> > 1 file
On Wed, 2017-06-07 at 21:52 +, Vivi, Rodrigo wrote:
> On Wed, 2017-06-07 at 18:44 +, Pandiyan, Dhinakaran wrote:
> > On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> > > The whole Display engine for Coffee Lake is pretty much
> > > identical to the Kabylake. For this reason let's re
On Wed, 2017-06-07 at 21:53 +, Vivi, Rodrigo wrote:
> On Wed, 2017-06-07 at 18:04 +, Pandiyan, Dhinakaran wrote:
> > On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> > > All here is pretty much like Kabylake.
> > >
> > > Cc: Dhinakaran Pandiyan
> > > Signed-off-by: Rodrigo Vivi
>
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