On ke, 2017-05-31 at 00:21 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/guc: Fix doorbell id selection
> URL : https://patchwork.freedesktop.org/series/25076/
> State : success
Merged. Thanks for the patch and review.
Regards, Joonas
--
Joonas Lahtinen
Open Source Techn
On ti, 2017-05-30 at 17:19 -0700, Daniele Ceraolo Spurio wrote:
>
> On 30/05/17 17:05, Michel Thierry wrote:
> >
> > We are passing parameters in the wrong order to find next zero bit, and
> > when it doesn't find anything it returns size (offset in the code), which
> > is always zero.
> >
> > F
On some systems there can be a race condition in which no crtc state is
added to the first atomic commit. This results in all crtc's having a
null DDB allocation, causing a FIFO underrun on any update until the
first modeset.
Reported-by: Maarten Lankhorst
Inspired-by: Mahesh Kumar
Signed-off-by
On Mon, May 29, 2017 at 12:36:54PM -0700, Stefan Agner wrote:
> On 2017-05-24 07:51, Daniel Vetter wrote:
> > drm_irq.c contains both the irq helper library (optional) and the
> > vblank support (optional, but part of the modeset uapi, and doesn't
> > require the use of the irq helpers at all.
> >
On 2017.05.21 00:15:27 -0700, Nick Desaulniers wrote:
> This flag is already set in the top level Makefile of the kernel.
>
> Also, by having set CONFIG_DRM_I915_GVT, thereby appending -Wall to
> ccflags, you undo all the -Wno-* cflags previously set in the Make
> variable KBUILD_CFLAGS.
>
> For
When we started following the backlight minimum brightness in
6dda730e55f4 ("drm/i915: respect the VBT minimum backlight brightness")
we overlooked the brightness invert quirk. Even if we invert the
brightness, we need to take the min limit into account. We probably
missed this because the invert h
In the conversion to drop drm_modeset_lock_all and the magic implicit
context I failed to realize that _resume starts out with a pile of
state copies, but not with the locks. And hence drm_atomic_commit
won't grab these for us.
v2: Add locking checks in helpers to make sure we catch this in the
fu
On Tue, May 30, 2017 at 09:03:34AM +0900, Inki Dae wrote:
> Hi Daniel,
>
> 2017년 05월 24일 23:51에 Daniel Vetter 이(가) 쓴 글:
> > Only in the load failure path, where the hardware is quiet anyway.
> >
> > Cc: Inki Dae
> > Cc: Joonyoung Shim
> > Cc: Seung-Woo Kim
> > Cc: Kyungmin Park
> > Signed-off
== Series Details ==
Series: drm/i915: fix backlight invert for non-zero minimum brightness
URL : https://patchwork.freedesktop.org/series/25085/
State : success
== Summary ==
Series 25085v1 drm/i915: fix backlight invert for non-zero minimum brightness
https://patchwork.freedesktop.org/api/1.
On Mon, May 29, 2017 at 01:07:40PM +0200, Philipp Zabel wrote:
> Hi Daniel,
>
> On Wed, 2017-05-24 at 16:51 +0200, Daniel Vetter wrote:
> > It's only done in the driver load error path, where vblanks don't need
> > to be quiescent anyway. And that's all drm_vblank_cleanup does, since
> > the core
On Tue, May 30, 2017 at 02:17:04PM -0700, Stefan Agner wrote:
> On 2017-05-26 00:00, Daniel Vetter wrote:
> > On Thu, May 25, 2017 at 10:18 AM, Stefan Agner wrote:
> >> On 2017-05-24 07:51, Daniel Vetter wrote:
> >>> Again cleanup before irq disabling doesn't really stop the races,
> >>> so just d
On Wed, 2017-05-31 at 02:29 +, Chen, Xiaoguang wrote:
> Hi Gerd,
>
> It is based on 4.12.0-rc1
Applies, good.
But then fails to build:
error: ‘struct vfio_vgpu_dmabuf_info’ has no member named ‘resv’
gvt/kvmgt.c:611:11: note: in expansion of macro ‘offsetofend’
minsz = offsetofend(struct
Hi,
> From: Benjamin Tissoires [mailto:benjamin.tissoi...@redhat.com]
> Subject: Re: [RFC PATCH v3 5/5] ACPI: button: Always notify kernel space
> using _LID returning value
>
> Hi Lv,
>
> On May 27 2017 or thereabouts, Lv Zheng wrote:
> > Both nouveau and i915, the only 2 kernel space lid noti
Hi Gerd,
I found this problem once I sent the patches :(
I checked the uapi definitions and found it is usually called pad to do the
aligning. So I changed the 'resv' to 'pad' in the patch but forgot to update it
in the last patch and did not test after the "small" change. Next time I will
tes
I spotted a markup issue, plus adding the descriptions in drm_driver.
Plus a few more links while at it.
I'm still mildly unhappy with the split between fops and ioctls, but I
still think having the ioctls in the uapi chapter makes more sense. Oh
well ...
v2: Rebase.
v3: Move misplace hunk to th
Pull a (much shorter) overview into drm_irq.c, and instead put the
callback documentation into in-line comments in drm_drv.h.
v2: Move the include stanzas back to the split-up patch (Stefan).
Cc: Stefan Agner
Reviewed-by: Stefan Agner
Signed-off-by: Daniel Vetter
---
Documentation/gpu/drm-int
pwm_info helps in encapsulating the PWM period_ns values and will form
basis of adding new pwm devices which can then be genrically used by
initializing proper pwm_info structure in the backlight setup call.
v2: Rebase on latest code. Add BZ details
Bugzilla: https://bugs.freedesktop.org/show_bug
Hi All,
Its been long since I have been sitting on these after I had received Tested-by
for the same by Lluís for atleast the backlight working fine. The related bugs
are -
https://bugs.freedesktop.org/show_bug.cgi?id=96571
https://bugs.freedesktop.org/show_bug.cgi?id=90075
Rebased the code on
v2: Add bugzilla links
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96571
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90075
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.com
Tested-by: Lluís Batlle i Rossell
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_p
v2: Rebase on latest code and correct the device name in
lookup table (viric)
Remove lookup table on driver remove
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96571
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90075
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.co
On Wed, May 31, 2017 at 11:33:55AM +0300, Jani Nikula wrote:
> When we started following the backlight minimum brightness in
> 6dda730e55f4 ("drm/i915: respect the VBT minimum backlight brightness")
> we overlooked the brightness invert quirk. Even if we invert the
> brightness, we need to take the
On Mon, May 22, 2017 at 12:55:14PM +0100, Chris Wilson wrote:
> Older gen use a physical address for the hardware status page, for which
> we use cache-coherent writes. As the writes are into the cpu cache, we use
> a normal WB mapped page to read the HWS, used for our seqno tracking.
>
> Anecdota
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 24
include/drm/drm_connector.h |2 ++
2 files changed, 26 insertions(+)
diff --git a/driver
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_connector.c |7 +++
include/drm/drm_connector.h | 11 +++
include/drm/drm_mode_config.h
This patch series enables HDR support in drm.
It basically defines HDR metadata structures,
property to pass content (after blending) metadata from user space
compositors to driver.
Dynamic Range and Mastering infoframe creation and sending.
ToDo:
1. We need to get the color framework in plac
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 25 +
drivers/video/hdmi.c
Attach HDR metadata property to connector object.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 41267ff..d8b53d0 100644
--- a/drivers/gpu/drm/i
HDR source metadata set and get property implemented in this
patch. The blob data is received from userspace and saved in
connector state, the same is returned as blob in get property
call to userspace.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c| 15 +++
dr
Add bit field and macro for extended tag in CEA block. Also,
declare macros for HDR metadata block.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 2e55
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 58
1 file changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers
On Tue, May 30, 2017 at 04:01:40PM -0400, Harry Wentland wrote:
> AMD GPUs can have 6 CRTCs.
>
> This requires us to allocate the combinations on the heap.
>
> Signed-off-by: Harry Wentland
I think just dynamically allocating stuff directly and dropping the
#define would be even neater ... GetR
Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
Signed-off-by: Uma Shankar
---
include/drm/drm_plane.h |3 +++
1 fil
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
Sign
On Wed, May 31, 2017 at 03:40:48PM +0530, Uma Shankar wrote:
> This patch series enables HDR support in drm.
> It basically defines HDR metadata structures,
> property to pass content (after blending) metadata from user space
> compositors to driver.
>
> Dynamic Range and Mastering infoframe cre
From: Daniel Vetter
Date: Tue, 30 May 2017 22:15:42 +0200
> If the e1000e maintainer wants to coalesce or not return statements
> this simple way, that's imo on him to change the color as needed.
That's not how things work.
If the maintainer wants you to style things a certain way, either you
d
== Series Details ==
Series: drm: Fix locking in drm_atomic_helper_resume (rev2)
URL : https://patchwork.freedesktop.org/series/25018/
State : success
== Summary ==
Series 25018v2 drm: Fix locking in drm_atomic_helper_resume
https://patchwork.freedesktop.org/api/1.0/series/25018/revisions/2/mb
== Series Details ==
Series: drm: more doc work&cleanup, mostly vblank related (rev4)
URL : https://patchwork.freedesktop.org/series/24877/
State : success
== Summary ==
Series 24877v4 drm: more doc work&cleanup, mostly vblank related
https://patchwork.freedesktop.org/api/1.0/series/24877/revi
Print DID not VID on the DID error path. Looks like a copy-paste error
from the VID error path. Clarify and clean up error logging, making them
distinguishable from each other, while at it.
Reported-by: Petru Mihancea
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101243
Signed-off-by: Ja
== Series Details ==
Series: Reviving the PWM_LPSS patches yet again
URL : https://patchwork.freedesktop.org/series/25090/
State : success
== Summary ==
Series 25090v1 Reviving the PWM_LPSS patches yet again
https://patchwork.freedesktop.org/api/1.0/series/25090/revisions/1/mbox/
Test gem_exe
From: Tvrtko Ursulin
Most of the subtest were failing on my SKL GT2 and on the
various CI systems as well. Try to fix that by different
tweaks per subtests:
performance:
We cannot say how big the performance drop will be once the
fences are contented, just that there will be one, so modify
the
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer
URL : https://patchwork.freedesktop.org/series/25091/
State : success
== Summary ==
Series 25091v1 Add HDR Metadata Parsing and handling in DRM layer
https://patchwork.freedesktop.org/api/1.0/series/25091/revisions
Hi,
On Wednesday 31 May 2017 01:26 PM, Maarten Lankhorst wrote:
On some systems there can be a race condition in which no crtc state is
added to the first atomic commit. This results in all crtc's having a
null DDB allocation, causing a FIFO underrun on any update until the
first modeset.
Repo
On 26/05/17 14:48, Chris Wilson wrote:
If we do a shallow probe of the connector and it reports the link failed
previous (link-status != GOOD), force a full probe of the connector to
give the kernel a chance to validate the mode list.
Sounds good, but will this make the tests SKIP if no modes a
== Series Details ==
Series: drm/i915/dvo: fix debug logging on unknown DID
URL : https://patchwork.freedesktop.org/series/25093/
State : failure
== Summary ==
Series 25093v1 drm/i915/dvo: fix debug logging on unknown DID
https://patchwork.freedesktop.org/api/1.0/series/25093/revisions/1/mbox/
Hi Daniel,
On Wed, May 24, 2017 at 04:51:51PM +0200, Daniel Vetter wrote:
> IRQs are properly shut down, so it almost works as race-free shutdown.
> Except the irq is stopped after the vblank stuff, so boom anyway.
> Proper way would be to call drm_atomic_helper_shutdown before any of
> the kms th
Op 31-05-17 om 12:42 schreef Mahesh Kumar:
> Hi,
>
>
> On Wednesday 31 May 2017 01:26 PM, Maarten Lankhorst wrote:
>> On some systems there can be a race condition in which no crtc state is
>> added to the first atomic commit. This results in all crtc's having a
>> null DDB allocation, causing a FI
On Wed, May 31, 2017 at 12:57 PM, Liviu Dudau wrote:
> On Wed, May 24, 2017 at 04:51:51PM +0200, Daniel Vetter wrote:
>> IRQs are properly shut down, so it almost works as race-free shutdown.
>> Except the irq is stopped after the vblank stuff, so boom anyway.
>> Proper way would be to call drm_at
On Wed, May 31, 2017 at 01:03:34PM +0200, Daniel Vetter wrote:
> On Wed, May 31, 2017 at 12:57 PM, Liviu Dudau wrote:
> > On Wed, May 24, 2017 at 04:51:51PM +0200, Daniel Vetter wrote:
> >> IRQs are properly shut down, so it almost works as race-free shutdown.
> >> Except the irq is stopped after
On Sat, 2017-05-27 at 16:38 +0800, Xiaoguang Chen wrote:
> + if (plane_id == PLANE_PRIMARY) {
Should be DRM_PLANE_TYPE_PRIMARY (likewise for the cursor).
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailm
Hello,
I went through the gem_* tests from intel-gpu-tools and categorized
them into roughly categories "X | X robustness | X performance" ready
to be added to the feat_profile.json.
Lets open a discussion which ones should go where. I tried to place a
single test to under only one category and I
From: Chris Wilson
When we query the available eu on each subslice, we currently only
report the max. It would also be useful to report the minimum found as
well.
When we set RPCS (power gating over the EU), we can also specify both
the min and max number of eu to configure on each slice; curren
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration pe
Hi,
A quick update with a couple of fixes in patch 13 & 14.
No changes in the other patches.
Cheers,
Chris Wilson (3):
drm/i915: Record both min/max eu_per_subslice in sseu_dev_info
drm/i915: Program RPCS for Broadwell
drm/i915: Record the sseu configuration per-context & engine
Lionel La
From: Chris Wilson
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may
From: Robert Bragg
Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
share (more-or-less) the same OA unit design.
Of particular note in comparison to Haswell: some OA unit HW config
state has become per-context state and as a consequence it is somewhat
more complicated to ma
From: Robert Bragg
Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic
render metrics on Broadwell, Cherryview, Skylake and Broxton. These are
auto generated from an XML description of metric sets, currently
maintained in gputop, ref:
https://github.com/rib/gputop
> gputop
Add OA support for Geminilake (pretty much identical to Broxton), and
also add the associated OA configurations.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile |3 +-
drivers/gpu/drm/i915/i915_oa_glk.c | 2602 +++
Gen8+ might have mux configurations per slices/subslices. Depending on
whether slices/subslices have been fused off, only part of the
configuration needs to be applied. This change reworks the mux
configurations query mechanism to allow more than one set of registers
to be programmed.
v2: s/n_mux_
Dynamic slices/subslices shutdown will effectivelly loose the NOA
configuration uploaded in the slices/subslices. When i915 perf is in
use, we therefore need to reprogram it.
v2: Make sure we handle configs with more register writes than the max
MI_LOAD_REGISTER_IMM can do (Lionel)
Signed-off
This adds the ability for userspace to request that the kernel track &
record sseu configuration changes. These changes are inserted into the
perf stream so that userspace can interpret the OA reports using the
configuration applied at the time the OA reports where generated.
v2: Handle timestamps
From: Robert Bragg
An oa_exponent_to_ns() utility and per-gen timebase constants where
recently removed when updating the tail pointer race condition WA, and
this restores those so we can update the _PROP_OA_EXPONENT validation
done in read_properties_unlocked() to not assume we have a 12.5MHz
ti
From: Robert Bragg
In earlier iterations of the i915-perf driver we had a number of
callbacks/hooks from other parts of the i915 driver to e.g. notify us
when a legacy context was pinned and these could run asynchronously with
respect to the stream file operations and might also run in atomic
con
Add macros to detect GT2/GT3 skus so we can apply the proper OA
configuration later.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915
On Tue, May 30, 2017 at 09:56:56PM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 5/30/2017 9:48 PM, Ville Syrjälä wrote:
> > On Tue, May 30, 2017 at 05:43:41PM +0530, Shashank Sharma wrote:
> >> CEA-861-F specs defines new video modes to be used with
> >> HDMI 2.0 EDIDs. The VIC
On Tue, May 30, 2017 at 10:00:12PM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 5/30/2017 9:43 PM, Ville Syrjälä wrote:
> > On Tue, May 30, 2017 at 05:43:40PM +0530, Shashank Sharma wrote:
> >> HDMI 1.4b support the CEA video modes as per range of CEA-861-D (VIC 1-64).
> >> For
On Wed, May 31, 2017 at 01:40:00PM +0300, Martin Peres wrote:
> On 26/05/17 14:48, Chris Wilson wrote:
> >If we do a shallow probe of the connector and it reports the link failed
> >previous (link-status != GOOD), force a full probe of the connector to
> >give the kernel a chance to validate the mo
On Wed, May 31, 2017 at 11:28:07AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Most of the subtest were failing on my SKL GT2 and on the
> various CI systems as well. Try to fix that by different
> tweaks per subtests:
>
> performance:
>
> We cannot say how big the performance drop
On Tue, May 30, 2017 at 10:18:19PM +0530, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 5/30/2017 10:06 PM, Ville Syrjälä wrote:
> > On Tue, May 30, 2017 at 05:43:44PM +0530, Shashank Sharma wrote:
> >> HDMI displays can support various output types, based on
> >> the color space and s
On Wed, May 31, 2017 at 03:23:12PM +0300, Joonas Lahtinen wrote:
> Hello,
>
> I went through the gem_* tests from intel-gpu-tools and categorized
> them into roughly categories "X | X robustness | X performance" ready
> to be added to the feat_profile.json.
>
> Lets open a discussion which ones s
Regards
Shashank
On 5/31/2017 6:16 PM, Ville Syrjälä wrote:
On Tue, May 30, 2017 at 10:18:19PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 5/30/2017 10:06 PM, Ville Syrjälä wrote:
On Tue, May 30, 2017 at 05:43:44PM +0530, Shashank Sharma wrote:
HDMI displays can support various ou
On 31/05/2017 13:45, Chris Wilson wrote:
On Wed, May 31, 2017 at 11:28:07AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Most of the subtest were failing on my SKL GT2 and on the
various CI systems as well. Try to fix that by different
tweaks per subtests:
performance:
We cannot say ho
On 31/05/17 15:42, Chris Wilson wrote:
On Wed, May 31, 2017 at 01:40:00PM +0300, Martin Peres wrote:
On 26/05/17 14:48, Chris Wilson wrote:
If we do a shallow probe of the connector and it reports the link failed
previous (link-status != GOOD), force a full probe of the connector to
give the ke
On ke, 2017-05-31 at 13:58 +0100, Chris Wilson wrote:
> On Wed, May 31, 2017 at 03:23:12PM +0300, Joonas Lahtinen wrote:
> >
> > Hello,
> >
> > I went through the gem_* tests from intel-gpu-tools and categorized
> > them into roughly categories "X | X robustness | X performance" ready
> > to be a
Chris Wilson writes:
> If the device is asleep (no GT wakeref), we know the GPU is already idle.
> If we add an early return, we can avoid touching registers and checking
> hw state outside of the assumed GT wakelock. This prevents causing such
> errors whilst debugging:
>
> [ 2613.401647] RPM wa
Chris Wilson writes:
> As another precaution when testing whether the CS engine is actually
> idle, also inspect the ring's HEAD/TAIL registers, which should be equal
> when there are no commands left to execute by the GPU.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gp
Chris Wilson writes:
> Allow intel_engine_is_idle() to be called outside of the GT wakeref by
> acquiring the device runtime pm for ourselves. This allows the function
> to act as check after we assume the engine is idle and we release the GT
> wakeref held whilst we have requests.
>
> [ 2613.401
On 2017-05-31 05:37 AM, Daniel Vetter wrote:
On Tue, May 30, 2017 at 04:01:40PM -0400, Harry Wentland wrote:
AMD GPUs can have 6 CRTCs.
This requires us to allocate the combinations on the heap.
Signed-off-by: Harry Wentland
I think just dynamically allocating stuff directly and dropping th
On Wed, May 31, 2017 at 04:44:41PM +0300, Martin Peres wrote:
> On 31/05/17 15:42, Chris Wilson wrote:
> >On Wed, May 31, 2017 at 01:40:00PM +0300, Martin Peres wrote:
> >>On 26/05/17 14:48, Chris Wilson wrote:
> >>>If we do a shallow probe of the connector and it reports the link failed
> >>>previ
On Tue, May 30, 2017 at 03:33:41PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > As another precaution when testing whether the CS engine is actually
> > idle, also inspect the ring's HEAD/TAIL registers, which should be equal
> > when there are no commands left to execute by the GPU.
Chris Wilson writes:
> On Tue, May 30, 2017 at 03:33:41PM +0300, Mika Kuoppala wrote:
>> Chris Wilson writes:
>>
>> > As another precaution when testing whether the CS engine is actually
>> > idle, also inspect the ring's HEAD/TAIL registers, which should be equal
>> > when there are no command
On Wed, May 31, 2017 at 04:45:16PM +0300, Joonas Lahtinen wrote:
> On ke, 2017-05-31 at 13:58 +0100, Chris Wilson wrote:
> > On Wed, May 31, 2017 at 03:23:12PM +0300, Joonas Lahtinen wrote:
> > >
> > > Hello,
> > >
> > > I went through the gem_* tests from intel-gpu-tools and categorized
> > > th
On Wed, May 03, 2017 at 11:41:29AM +0300, Imre Deak wrote:
> On Tue, May 02, 2017 at 03:27:04PM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [v4,1/2] PCI / PM: Add needs_resume flag to
> > avoid suspend complete optimization
> > URL : https://patchwork.f
On Thu, May 25, 2017 at 11:25:54AM +0100, Tvrtko Ursulin wrote:
>
> On 25/05/2017 08:40, Lukasz Fiedorowicz wrote:
> > gem_execbuf_wr was duplicated in multiple places.
> > Moving everything to lib/
> >
> > Signed-off-by: Lukasz Fiedorowicz
> > ---
> > benchmarks/gem_busy.c| 16
On 31/05/17 16:55, Chris Wilson wrote:
On Wed, May 31, 2017 at 04:44:41PM +0300, Martin Peres wrote:
On 31/05/17 15:42, Chris Wilson wrote:
On Wed, May 31, 2017 at 01:40:00PM +0300, Martin Peres wrote:
On 26/05/17 14:48, Chris Wilson wrote:
If we do a shallow probe of the connector and it rep
Hi Dave, this series, based on v4.12-rc3, starts a DP sink/branch device
specific quirk database, and uses it to handle conflicting requirements
on the DP Mvid/Nvid main stream attributes by different sinks.
v4.12 has a Mvid/Nvid fix for a common USB Type-C DP adapter (the
DA200), which unfortuna
From: Daniel Vetter
Date: Wed, 31 May 2017 08:10:45 +0200
> On Wed, May 31, 2017 at 7:54 AM, Daniel Vetter wrote:
>> On Wed, May 31, 2017 at 1:06 AM, Dave Airlie wrote:
>>> On 31 May 2017 at 08:10, David Miller wrote:
From: Daniel Vetter
Date: Tue, 30 May 2017 22:15:42 +0200
>>
Sometimes it would be most enlightening to debug systems by replacing
the VBT to be used. For example, in the referenced bug the BIOS provides
different VBT depending on the boot mode (UEFI vs. legacy). It would be
interesting to try the failing boot mode with the VBT from the working
boot, and see
== Series Details ==
Series: drm/i915/opregion: let user specify override VBT via firmware load
URL : https://patchwork.freedesktop.org/series/25105/
State : success
== Summary ==
Series 25105v1 drm/i915/opregion: let user specify override VBT via firmware
load
https://patchwork.freedesktop.o
Regards
Shashank
On 5/31/2017 6:09 PM, Ville Syrjälä wrote:
On Tue, May 30, 2017 at 09:56:56PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 5/30/2017 9:48 PM, Ville Syrjälä wrote:
On Tue, May 30, 2017 at 05:43:41PM +0530, Shashank Sharma wrote:
CEA-861-F specs defines new video mod
Regards
Shashank
On 5/31/2017 6:11 PM, Ville Syrjälä wrote:
On Tue, May 30, 2017 at 10:00:12PM +0530, Sharma, Shashank wrote:
Regards
Shashank
On 5/30/2017 9:43 PM, Ville Syrjälä wrote:
On Tue, May 30, 2017 at 05:43:40PM +0530, Shashank Sharma wrote:
HDMI 1.4b support the CEA video modes
On some systems there can be a race condition in which no crtc state is
added to the first atomic commit. This results in all crtc's having a
null DDB allocation, causing a FIFO underrun on any update until the
first modeset.
Changes since v1:
- Do not take the connection_mutex, this is already do
On Wed, 31 May 2017, David Miller wrote:
> And we can't understand why respinning with the requested change is
> less work than making several postings such as this one.
When our CI hits tons of non-drm issues every merge window, I imagine
our developers can start to get a little frustrated tryin
From: Chris Wilson
An error during suspend (e100e_pm_suspend),
[ 429.994338] ACPI : EC: event blocked
[ 429.994633] e1000e: EEE TX LPI TIMER: 0011
[ 430.955451] pci_pm_suspend(): e1000e_pm_suspend+0x0/0x30 [e1000e] returns -2
[ 430.955454] dpm_run_callback(): pci_pm_suspend+0x0/0x140 ret
On 05/18/2017 05:41 PM, Michal Wajdeczko wrote:
On Fri, May 05, 2017 at 01:23:17PM +, Oscar Mateo wrote:
The decission to enable GuC loading shouldn't be left to the user.
Provided the HW supports the GuC, there are only two reasons to load it:
- The user has requested GuC submission.
-
On Wed, May 31, 2017 at 5:08 PM, David Miller wrote:
> From: Daniel Vetter
> Date: Wed, 31 May 2017 08:10:45 +0200
>
>> On Wed, May 31, 2017 at 7:54 AM, Daniel Vetter
>> wrote:
>>> On Wed, May 31, 2017 at 1:06 AM, Dave Airlie wrote:
On 31 May 2017 at 08:10, David Miller wrote:
> From
On Wed, May 24, 2017 at 04:51:51PM +0200, Daniel Vetter wrote:
> IRQs are properly shut down, so it almost works as race-free shutdown.
> Except the irq is stopped after the vblank stuff, so boom anyway.
> Proper way would be to call drm_atomic_helper_shutdown before any of
> the kms things gets st
On Wed, May 31, 2017 at 1:22 PM, Liviu Dudau wrote:
> On Wed, May 31, 2017 at 01:03:34PM +0200, Daniel Vetter wrote:
>> On Wed, May 31, 2017 at 12:57 PM, Liviu Dudau wrote:
>> > On Wed, May 24, 2017 at 04:51:51PM +0200, Daniel Vetter wrote:
>> >> IRQs are properly shut down, so it almost works as
Hi Shobhit,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc3 next-20170531]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Shobhit-Kumar/drm-i915
On Wed, May 31, 2017 at 06:41:05PM +0200, Daniel Vetter wrote:
> On Wed, May 31, 2017 at 1:22 PM, Liviu Dudau wrote:
> > On Wed, May 31, 2017 at 01:03:34PM +0200, Daniel Vetter wrote:
> >> On Wed, May 31, 2017 at 12:57 PM, Liviu Dudau wrote:
> >> > On Wed, May 24, 2017 at 04:51:51PM +0200, Daniel
The IGT test suite aims at testing the functionalities of the i915
graphics driver. Because of an increasing effort to move development and
validation to the early stages in the development of new platforms, it
is necessary to provide some form of coverage for scenarios where the
driver assumes the
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