Split out BXT and CNP's setup_backlight(),enable_backlight(),
disable_backlight() and hz_to_pwm() into
two separate functions instead of reusing BXT function.
Reuse set_backlight() and get_backlight() since they have
no reference to the utility pin.
v2: Reuse BXT functions with controller 0 inste
All here is pretty much like Kabylake, expect the PCH.
This patch exclude the addition of DMC, GuC and most workardounds since
they might have changes/updates.
v2: Take advantage of IS_GEN9_BC minimizing the needed plumbing.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_ddi.c | 6
RAWCLK_FREQ register has changed for platforms with CNP+.
[29:26] This field provides the denominator for the fractional
part of the microsecond counter divider. The numerator
is fixed at 1. Program this field to the denominator of
the fractional portion of reference frequ
From the DMC perspective the same firmware is used on
both platforms. We haven't recieved any separated release
specifically for Coffee Lake so let's just re-use what
is already there for Kabylake.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel
Coffee Lake inherit most of Kabylake production
workardounds.
Only difference identified so far is:
- WaDisableLSQCROPERFforOCL is marked as SIWA_NEVER
Cc: Dhinakaran Pandiyan
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c| 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c
So let's force it on the virtual detection.
Also it is still the only silicon for now on this PCH,
so WARN otherwise.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i9
Coffee Lake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.
It is Gen9 graphics based platform on top of CNP PCH.
Let's start by adding the platform definition based on previous
platforms but yet as preliminary_hw_support.
On following patches we will start adding PCI IDs
As for BXT, PP_DIVISOR was removed from CNP PCH and power
cycle delay has been moved to PP_CONTROL.
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/dr
From: Anusha Srivatsa
Follow the spec and add the PCI Ids.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
---
include/drm/i915_pciids.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
ind
Most of south engine display that is in PCH is still the
same as SPT and KBP, except for this key differences:
- Backlight: Backlight programming changed in CNP PCH.
- Panel Power: Sligh programming changed in CNP PCH.
- GMBUS and GPIO: The pin mapping has changed in CNP PCH.
All of these changes
== Series Details ==
Series: series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH.
URL : https://patchwork.freedesktop.org/series/25070/
State : success
== Summary ==
Series 25070v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25070/revisions/1/m
On 31 May 2017 at 08:10, David Miller wrote:
> From: Daniel Vetter
> Date: Tue, 30 May 2017 22:15:42 +0200
>
>> If the e1000e maintainer wants to coalesce or not return statements
>> this simple way, that's imo on him to change the color as needed.
>
> That's not how things work.
>
> If the maint
On 05/30/2017 02:29 PM, Hans Verkuil wrote:
On 05/30/2017 10:32 PM, Clint Taylor wrote:
On 05/30/2017 09:54 AM, Hans Verkuil wrote:
On 05/30/2017 06:49 PM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Ha
On 05/26/2017 12:18 AM, Daniel Vetter wrote:
On Thu, May 25, 2017 at 05:06:25PM +0200, Hans Verkuil wrote:
From: Hans Verkuil
This adds support for the DisplayPort CEC-Tunneling-over-AUX
feature that is part of the DisplayPort 1.3 standard.
Unfortunately, not all DisplayPort/USB-C to HDMI a
We are passing parameters in the wrong order to find next zero bit, and
when it doesn't find anything it returns size (offset in the code), which
is always zero.
For reference the function is defined as:
find_next_bit( *addr, size, offset )
The incorrect parameter order was added by commit abddff
On 30/05/17 17:05, Michel Thierry wrote:
We are passing parameters in the wrong order to find next zero bit, and
when it doesn't find anything it returns size (offset in the code), which
is always zero.
For reference the function is defined as:
find_next_bit( *addr, size, offset )
The incorre
== Series Details ==
Series: drm/i915/guc: Fix doorbell id selection
URL : https://patchwork.freedesktop.org/series/25076/
State : success
== Summary ==
Series 25076v1 drm/i915/guc: Fix doorbell id selection
https://patchwork.freedesktop.org/api/1.0/series/25076/revisions/1/mbox/
Test gem_exe
Hi Shashank,
[auto build test WARNING on drm/drm-next]
[also build test WARNING on next-20170530]
[cannot apply to v4.12-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Shashank-Sharma/HDMI
> -Original Message-
> From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
> Sent: Tuesday, May 30, 2017 4:38 PM
> To: Zhang, Tina ; intel-gfx@lists.freedesktop.org
> Cc: zhen...@linux.intel.com; intel-gvt-...@lists.freedesktop.org
> Subject: Re: [PATCH v3] drm/i915: Enable gues
Hi Gerd,
It is based on 4.12.0-rc1
>-Original Message-
>From: Gerd Hoffmann [mailto:kra...@redhat.com]
>Sent: Tuesday, May 30, 2017 6:24 PM
>To: Chen, Xiaoguang ;
>alex.william...@redhat.com; ch...@chris-wilson.co.uk; intel-
>g...@lists.freedesktop.org; linux-ker...@vger.kernel.org;
>zhen
I915_GEM_GET_APERTURE ioctl is used to probe aperture size from userspace.
In gvt environment, each vm only use the ballooned part of aperture, so we
should return the correct available aperture size exclude the reserved part
by balloon.
v2: add 'reserved' in struct i915_address_space to record th
On 2017.05.30 11:37:50 +0300, Joonas Lahtinen wrote:
> On ma, 2017-05-22 at 16:19 +0800, Tina Zhang wrote:
> > Enable the guest i915 full ppgtt functionality when host can provide this
> > capability. vgt_caps is introduced to guest i915 driver to get the vgpu
> > capabilities from the device model
== Series Details ==
Series: drm/i915: return the correct usable aperture size under gvt environment
(rev2)
URL : https://patchwork.freedesktop.org/series/24933/
State : success
== Summary ==
Series 24933v2 drm/i915: return the correct usable aperture size under gvt
environment
https://patch
-Original Message-
From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
Sent: Monday, May 29, 2017 4:29 PM
To: Wang, Quanxian ; intel-gfx@lists.freedesktop.org
Cc: Yang, Libin
Subject: RE: [PATCH] Defined NM doesn't work on KBL and uses automatic N/M.
On Fri, 26 May 2017, "Wang, Qua
The patch looks good overall, it would have been easier to merge if
you'd sent this as the first patch in this version. Some comments
inline.
On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> Read desired PWM frequency from panel vbt and calculate the
> value for divider in DPCD
On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> This patch adds option to enable dynamic backlight for eDP
> panel that supports this feature via DPCD register and
> set minimum / maximum brightness to 0% and 100% of the
> normal brightness.
>
> Signed-off-by: Puthikorn Voravoot
On 2017.05.27 16:38:48 +0800, Xiaoguang Chen wrote:
> OpRegion is needed to support display related operation for
> intel vgpu.
>
> A vfio device region is added to intel vgpu to deliver the
> host OpRegion information to user space so user space can
> construct the OpRegion for vgpu.
>
> Signed-
On 2017.05.27 16:38:49 +0800, Xiaoguang Chen wrote:
> decode frambuffer attributes of primary, cursor and sprite plane
>
> Signed-off-by: Xiaoguang Chen
> ---
> drivers/gpu/drm/i915/gvt/Makefile | 3 +-
> drivers/gpu/drm/i915/gvt/display.c| 2 +-
> drivers/gpu/drm/i915/gvt/display.h
On Wed, May 31, 2017 at 1:06 AM, Dave Airlie wrote:
> On 31 May 2017 at 08:10, David Miller wrote:
>> From: Daniel Vetter
>> Date: Tue, 30 May 2017 22:15:42 +0200
>>
>>> If the e1000e maintainer wants to coalesce or not return statements
>>> this simple way, that's imo on him to change the color
Hi Rodrigo,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc3 next-20170530]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnp
On Wed, May 31, 2017 at 7:54 AM, Daniel Vetter wrote:
> On Wed, May 31, 2017 at 1:06 AM, Dave Airlie wrote:
>> On 31 May 2017 at 08:10, David Miller wrote:
>>> From: Daniel Vetter
>>> Date: Tue, 30 May 2017 22:15:42 +0200
>>>
If the e1000e maintainer wants to coalesce or not return stateme
Hi,
memory bandwidth WA is not applicable for GEN10 but below WA is needed
for CNL-A.
-Mahesh
On Saturday 27 May 2017 04:53 AM, Rodrigo Vivi wrote:
Based on patch submited to intel-gfx:
"drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+"
and subsequential tests on CNL, it seems that
Hi,
>-Original Message-
>From: Gerd Hoffmann [mailto:kra...@redhat.com]
>Sent: Monday, May 29, 2017 3:20 PM
>To: Chen, Xiaoguang ;
>alex.william...@redhat.com; ch...@chris-wilson.co.uk; intel-
>g...@lists.freedesktop.org; linux-ker...@vger.kernel.org;
>zhen...@linux.intel.com; Lv, Zhiyuan
Hi
>-Original Message-
>From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
>Behalf Of Zhenyu Wang
>Sent: Wednesday, May 31, 2017 12:47 PM
>To: Chen, Xiaoguang
>Cc: Tian, Kevin ; intel-gfx@lists.freedesktop.org; linux-
>ker...@vger.kernel.org; zhen...@linux.intel.
On 2017.05.31 06:22:28 +, Chen, Xiaoguang wrote:
> >> @@ -467,6 +555,15 @@ static int intel_vgpu_create(struct kobject *kobj,
> >struct mdev_device *mdev)
> >>vgpu->vdev.mdev = mdev;
> >>mdev_set_drvdata(mdev, vgpu);
> >>
> >> + ret = intel_vgpu_reg_init_opregion(vgpu);
> >> + if (ret
On 05/31/2017 01:25 AM, Clint Taylor wrote:
On 05/30/2017 02:29 PM, Hans Verkuil wrote:
On 05/30/2017 10:32 PM, Clint Taylor wrote:
On 05/30/2017 09:54 AM, Hans Verkuil wrote:
On 05/30/2017 06:49 PM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM
On 05/31/2017 01:57 AM, Clint Taylor wrote:
On 05/26/2017 12:18 AM, Daniel Vetter wrote:
On Thu, May 25, 2017 at 05:06:25PM +0200, Hans Verkuil wrote:
From: Hans Verkuil
This adds support for the DisplayPort CEC-Tunneling-over-AUX
feature that is part of the DisplayPort 1.3 standard.
Unfor
>-Original Message-
>From: Zhenyu Wang [mailto:zhen...@linux.intel.com]
>Sent: Wednesday, May 31, 2017 1:12 PM
>To: Chen, Xiaoguang
>Cc: alex.william...@redhat.com; kra...@redhat.com; ch...@chris-wilson.co.uk;
>intel-gfx@lists.freedesktop.org; linux-ker...@vger.kernel.org;
>zhen...@linux
>-Original Message-
>From: Zhenyu Wang [mailto:zhen...@linux.intel.com]
>Sent: Wednesday, May 31, 2017 2:30 PM
>To: Chen, Xiaoguang
>Cc: Tian, Kevin ; intel-gfx@lists.freedesktop.org; linux-
>ker...@vger.kernel.org; ch...@chris-wilson.co.uk; alex.william...@redhat.com;
>kra...@redhat.com
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