== Series Details ==
Series: Gen8+ engine-reset (rev8)
URL : https://patchwork.freedesktop.org/series/21868/
State : success
== Summary ==
Series 21868v8 Gen8+ engine-reset
https://patchwork.freedesktop.org/api/1.0/series/21868/revisions/8/mbox/
Test gem_exec_flush:
Subgroup basic-bat
On Wed, May 17, 2017 at 05:28:30PM +0530, Mahesh Kumar wrote:
> From: "Kumar, Mahesh"
>
> This patch implements new DDB allocation algorithm as per HW team
> recommendation. This algo takecare of scenario where we allocate less DDB
> for the planes with lower relative pixel rate, but they require
On Wed, May 17, 2017 at 05:28:29PM +0530, Mahesh Kumar wrote:
> From: "Kumar, Mahesh"
>
> This patch make changes to use linetime latency if allocated
> DDB size during plane watermark calculation is not available.
> linetime is the time, display engine takes to fetch one line worth of
> pixels w
On 05/17/2017 07:25 AM, Jani Nikula wrote:
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or just otherwise require special treatment. Start a common
quirk database the drivers can query b
On Wed, May 17, 2017 at 11:29:13PM +0200, Nicolai Stange wrote:
> Hi,
>
> my system (always) locks up when booting a next-20170515 kernel.
>
> No oops. Sending magic sysrqs over serial doesn't cause any reaction.
>
> Last few console messages before death are:
>
> [7.089221] Console: swit
On Wed, May 17, 2017 at 05:28:19PM +0530, Mahesh Kumar wrote:
> This series implements new DDB allocation algorithm to solve the cases,
> where we have sufficient DDB available to enable multiple planes, But
> due to the current algorithm not dividing it properly among planes, we
> end-up failing t
Hey all,
It has come to my attention that there is a pretty serious bug in i915
on Broadwell for 4.10 and 4.11 released kernels, this means it has
probably been in the intel-next tree for at least 4 if not 6 months,
and gone unnoticed. How does something like this get into Linus tree,
and remain i
On 17-05-17 13:31:44, Daniel Vetter wrote:
On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
On 17-05-03 17:08:27, Daniel Vetter wrote:
> On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
> > +struct drm_format_modifier_blob {
> > +#define FORMAT_BLOB_CURRENT 1
> > +
On 17-05-17 11:17:57, Liviu Dudau wrote:
On Tue, May 16, 2017 at 02:31:24PM -0700, Ben Widawsky wrote:
This is the plumbing for supporting fb modifiers on planes. Modifiers
have already been introduced to some extent, but this series will extend
this to allow querying modifiers per plane. Based
On Wed, May 17, 2017 at 8:00 PM, Ben Widawsky wrote:
> On 17-05-17 13:31:44, Daniel Vetter wrote:
>>
>> On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
>>>
>>> On 17-05-03 17:08:27, Daniel Vetter wrote:
>>> > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
>>> > > +stru
On Wed, May 17, 2017 at 8:38 PM, Rob Clark wrote:
> On Wed, May 17, 2017 at 8:00 PM, Ben Widawsky wrote:
>> On 17-05-17 13:31:44, Daniel Vetter wrote:
>>>
>>> On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
On 17-05-03 17:08:27, Daniel Vetter wrote:
> On Tue, May 02,
On 17-05-17 01:06:16, Emil Velikov wrote:
Hi Ben,
On 16 May 2017 at 22:31, Ben Widawsky wrote:
Updated blob layout (Rob, Daniel, Kristian, xerpi)
v2:
* Removed __packed, and alignment (.+)
* Fix indent in drm_format_modifier fields (Liviu)
* Remove duplicated modifier > 64 check (Liviu)
* Cha
On Thu, Apr 06, 2017 at 12:15:33PM -0700, Rodrigo Vivi wrote:
> This are the registers and bits needed for the voltage swing
> sequence on Cannonlake.
>
> v2: Remove CL_DW5 that was wrongly defined.
> v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
> Change DW2 swing sel upper and lower
On Thu, Apr 06, 2017 at 12:15:34PM -0700, Rodrigo Vivi wrote:
> These tables are used on voltage wswing sequence initialization
> on Cannonlake.
>
> It is a complete new format now in use by the voltage swing team,
> not following any other standard in use by any other platform.
> Also the registe
On Thu, Apr 06, 2017 at 12:15:35PM -0700, Rodrigo Vivi wrote:
> This is an important part of the DDI initalization as well as
> for changing the voltage during DisplayPort link training.
>
> This new sequence for Cannonlake is more like Broxton style
> but still with different registers, different
On 17/05/17 13:52, Chris Wilson wrote:
On Wed, May 17, 2017 at 01:41:34PM -0700, Michel Thierry wrote:
@@ -2827,21 +2829,35 @@ int i915_gem_reset_prepare_engine(struct
intel_engine_cs *engine)
if (engine_stalled(engine)) {
request = i915_gem_find_active_request(engine);
On Thu, Apr 06, 2017 at 12:15:36PM -0700, Rodrigo Vivi wrote:
> From: Clint Taylor
>
> vswing programming sequence step 2 requires the Loadgen_select bit to
> be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and
> lane width. Implemented the change that was marked as FIXME in th
On 17-05-17 01:20:50, Emil Velikov wrote:
Hi Ben,
A couple of small questions/suggestions that I hope you find useful.
Please don't block any of this work based on my comments.
On 16 May 2017 at 22:31, Ben Widawsky wrote:
+static bool intel_primary_plane_format_mod_supported(struct drm_plane
Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ defines to the UAPI
as a convenience.
Ideally the DRM_ROTATE_ and DRM_REFLECT_ property ids are looked up
through the atomic API, but realizing that userspace is likely to take
shortcuts and assume that the enum values are what is sent over the
wire.
As
> -Original Message-
> From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
> Behalf Of Joonas Lahtinen
> Sent: Monday, May 15, 2017 6:50 PM
> To: Zhang, Tina ; intel-gvt-...@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PAT
Hi,
On Thursday 18 May 2017 02:44 AM, Matt Roper wrote:
On Wed, May 17, 2017 at 05:28:30PM +0530, Mahesh Kumar wrote:
From: "Kumar, Mahesh"
This patch implements new DDB allocation algorithm as per HW team
recommendation. This algo takecare of scenario where we allocate less DDB
for the plan
On Wed, May 17, 2017 at 05:25:14PM +0300, Jani Nikula wrote:
> Switch to using the common DP helpers instead of using our own.
>
> Signed-off-by: Jani Nikula
Forgot to remove struct intel_dp_desc, otherwise lgtm.
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_dp.c | 37
>
On Wed, May 17, 2017 at 05:25:16PM +0300, Jani Nikula wrote:
> The Analogix 7737 DP to HDMI converter requires reduced M and N values
> when to operate correctly at HBR2. Detect this IC by its OUI value of
> 0x0022B9 via the DPCD quirk list.
Commit message is a bit confusing since this sounds like
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