[Intel-gfx] [PATCH] [RFC i-g-t] Test Design to verify mipi enable/disable sequence.

2017-01-07 Thread Yadav Jyoti
From: Jenkins Val Signed-off-by: Jyoti Yadav --- tests/Makefile.am | 3 +- tests/Makefile.sources | 1 + tests/mipi_sequence_verification.c | 201 + 3 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 tests/m

[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-07 Thread vathsala nagaraju
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed. Enable bit 12 for programmable header packet. Enable bit 15 for Y cordinate support. v2: (Rodrigo) - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc v3:(Rodrigo) - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of

Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-07 Thread Chris Wilson
On Sat, Jan 07, 2017 at 11:42:04PM +0530, vathsala nagaraju wrote: > As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 > must be programmed. > Enable bit 12 for programmable header packet. > Enable bit 15 for Y cordinate support. > > v2: (Rodrigo) > - move CHICKEN_TRANS_EDP bit set logic right after setu

[Intel-gfx] [PATCH] drm/i915: Remove WaDisableLSQCROPERFforOCL KBL workaround.

2017-01-07 Thread Francisco Jerez
The WaDisableLSQCROPERFforOCL workaround has the side effect of disabling an L3SQ optimization that has huge performance implications and is unlikely to be necessary for the correct functioning of usual graphic workloads. Userspace is free to re-enable the workaround on demand, and is generally in