Re: [Intel-gfx] [PATCH v2 1/2] drm: Wrap the check for atomic_commit implementation

Hi Dhinakaran, [auto build test ERROR on drm/drm-next] [also build test ERROR on next-20161222] [cannot apply to v4.9] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Dhinakaran-Pandiyan/drm

Re: [Intel-gfx] [PATCH v3] drm/i915: Check HAS_PCH_NOP when install or reset dispaly IRQ

On Thu, 22 Dec 2016, "Wang, Elaine" wrote: > Hi Jani, Ville, > > Any comment about the "PCH_NOP" vs "num_pipes == 0"? > > Thanks, > Elaine >> On Thu, 15 Dec 2016, Ville Syrjälä wrote: >> > On Mon, Dec 12, 2016 at 02:57:44PM +0800, Wang Elaine wrote: >> >> From: Elaine Wang >> >> >> >> Some platf

[Intel-gfx] [git pull] GVT-g fixes for 4.10

Hi, This is currently GVT-g driver fixes for 4.10-rc2. Thanks. --- The following changes since commit 0f484e42baaf5a38fc79e99b917caa5431651fb1: Merge tag 'kvmgt-vfio-mdev-for-v4.10-rc1' of git://github.com/01org/gvt-linux (2016-12-17 16:47:31 -0800) are available in the git repository at:

Re: [Intel-gfx] [PATCH v3] drm/i915: Check HAS_PCH_NOP when install or reset dispaly IRQ

> > On Thu, 22 Dec 2016, "Wang, Elaine" wrote: > > Hi Jani, Ville, > > > > Any comment about the "PCH_NOP" vs "num_pipes == 0"? > > > > Thanks, > > Elaine > >> On Thu, 15 Dec 2016, Ville Syrjälä wrote: > >> > On Mon, Dec 12, 2016 at 02:57:44PM +0800, Wang Elaine wrote: > >> >> From: Elaine Wan

Re: [Intel-gfx] [PATCH v2 1/2] drm: Wrap the check for atomic_commit implementation

On Wed, 2016-12-21 at 12:12 -0800, Dhinakaran Pandiyan wrote: > This check is useful for drivers that do not have DRIVER_ATOMIC set but > have atomic modesetting internally implemented. Wrap the check into a > function since this is used in many places and as a bonus, the function > name helps to d

[Intel-gfx] drm_mm fixes, take 4?

Some code beautification applied to lib/prime_numbers (and a couple of spelling mistakes that Joonas had noticed but I forgot to apply). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/inte

[Intel-gfx] [PATCH v4 01/38] drm/i915: Use the MRU stack search after evicting

When we evict from the GTT to make room for an object, the hole we create is put onto the MRU stack inside the drm_mm range manager. On the next search pass, we can speed up a PIN_HIGH allocation by referencing that stack for the new hole. v2: Pull together the 3 identical implements (ahem, a coup

[Intel-gfx] [PATCH v4 17/38] drm: kselftest for drm_mm and color adjustment

Check that after applying the driver's color adjustment, fitting of the node and its alignment are still correct. v2: s/no_color_touching/separate_adjacent_colors/ Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm

[Intel-gfx] [PATCH v4 16/38] drm: kselftest for drm_mm and top-down allocation

Check that if we request top-down allocation from drm_mm_insert_node() we receive the next available hole from the top. v2: Flip sign on conditional assert. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selfte

[Intel-gfx] [PATCH v4 08/38] drm: kselftest for drm_mm_debug()

Simple test to just exercise calling the debug dumper on the drm_mm. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selftests/test-drm_mm.c | 35 2 files changed, 36 insertions(+

[Intel-gfx] [PATCH v4 06/38] drm: Add some kselftests for the DRM range manager (struct drm_mm)

First we introduce a smattering of infrastructure for writing selftests. The idea is that we have a test module that exercises a particular portion of the exported API, and that module provides a set of tests that can either be run as an ensemble via kselftest or individually via an igt harness (in

[Intel-gfx] [PATCH v4 28/38] drm: Unconditionally do the range check in drm_mm_scan_add_block()

Doing the check is trivial (low cost in comparison to overall eviction) and helps simplify the code. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 53 +++ drivers/gpu/drm/i915/i915_gem_evict.c | 10 ++- i

[Intel-gfx] [PATCH v4 32/38] drm: Simplify drm_mm scan-list manipulation

Since we mandate a strict reverse-order of drm_mm_scan_remove_block() after drm_mm_scan_add_block() we can further simplify the list manipulations when generating the temporary scan-hole. v2: Highlight the games being played with the lists to track the scan holes without allocation. Signed-off-by

[Intel-gfx] [PATCH v4 15/38] drm: kselftest for drm_mm and range restricted eviction

Check that we add arbitrary blocks to a restrited eviction scanner in order to find the first minimal hole that matches our request. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selftests/test-drm_mm.c |

[Intel-gfx] [PATCH v4 21/38] drm: Promote drm_mm alignment to u64

In places (e.g. i915.ko), the alignment is exported to userspace as u64 and there now exists hardware for which we can indeed utilize a u64 alignment. As such, we need to keep 64bit integers throughout when handling alignment. Testcase: igt/drm_mm/align64 Testcase: igt/gem_exec_alignment Signed-of

[Intel-gfx] [PATCH v4 27/38] drm: Rename prev_node to hole in drm_mm_scan_add_block()

Acknowledging that we were building up the hole was more useful to me when reading the code, than knowing the relationship between this node and the previous node. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 16 1 file changed, 8 inse

[Intel-gfx] [PATCH v4 07/38] drm: kselftest for drm_mm_init()

Simple first test to just exercise initialisation of struct drm_mm. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selftests/test-drm_mm.c | 114 +++ 2 files changed, 115 insertions(

[Intel-gfx] [PATCH v4 38/38] drm: kselftest for drm_mm and bottom-up allocation

Check that if we request bottom-up allocation from drm_mm_insert_node() we receive the next available hole from the bottom. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selftests/test-drm_mm.c | 100 +

[Intel-gfx] [PATCH v4 34/38] drm: Wrap drm_mm_node.hole_follows

Insulate users from changes to the internal hole tracking within struct drm_mm_node by using an accessor for hole_follows. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c| 12 ++-- drivers/gpu/drm/i915/i915_vma.c | 4 ++-- d

[Intel-gfx] [PATCH v4 03/38] drm: Compile time enabling for asserts in drm_mm

Use CONFIG_DRM_DEBUG_MM to conditionally enable the internal and validation checking using BUG_ON. Ideally these paths should all be exercised by CI selftests (with the asserts enabled). Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 45 +

[Intel-gfx] [PATCH v4 10/38] drm: kselftest for drm_mm_insert_node()

Exercise drm_mm_insert_node(), check that we can't overfill a range and that the lists are correct after reserving/removing. v2: Extract helpers for the repeated tests v3: Iterate over all allocation flags Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/d

[Intel-gfx] [PATCH v4 09/38] drm: kselftest for drm_mm_reserve_node()

Exercise drm_mm_reserve_node(), check that we can't reserve an already occupied range and that the lists are correct after reserving/removing. v2: Check for invalid node reservation. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1

[Intel-gfx] [PATCH v4 12/38] drm: kselftest for drm_mm_insert_node_in_range()

Exercise drm_mm_insert_node_in_range(), check that we only allocate from the specified range. v2: Use all allocation flags v3: Don't pass in invalid ranges - these will be asserted later. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h

[Intel-gfx] [PATCH v4 14/38] drm: kselftest for drm_mm and eviction

Check that we add arbitrary blocks to the eviction scanner in order to find the first minimal hole that matches our request. v2: Refactor out some common eviction code for later Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + d

[Intel-gfx] [PATCH v4 19/38] drm: kselftest for drm_mm and restricted color eviction

Check that after applying the driver's color adjustment, restricted eviction scanning finds a suitable hole. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selftests/test-drm_mm.c | 116

[Intel-gfx] [PATCH v4 11/38] drm: kselftest for drm_mm_replace_node()

Reuse drm_mm_insert_node() with a temporary node to exercise drm_mm_replace_node(). We use the previous test in order to exercise the various lists following replacement. v2: Check that we copy across the important (user) details of the node. The internal details (such as lists and hole tracking)

[Intel-gfx] [PATCH v4 18/38] drm: kselftest for drm_mm and color eviction

Check that after applying the driver's color adjustment, eviction scanning finds a suitable hole. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selftests/test-drm_mm.c | 156 +++ 2

[Intel-gfx] [PATCH v4 35/38] drm: Apply range restriction after color adjustment when allocation

mm->color_adjust() compares the hole with its neighbouring nodes. They only abutt before we restrict the hole, so we have to apply color_adjust before we apply the range restriction. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 16 ++-- 1 f

[Intel-gfx] [PATCH v4 04/38] lib: Add a simple prime number generator

Prime numbers are interesting for testing components that use multiplies and divides, such as testing DRM's struct drm_mm alignment computations. v2: Move to lib/, add selftest v3: Fix initial constants (exclude 0/1 from being primes) v4: More RCU markup to keep 0day/sparse happy v5: Fix RCU unwin

[Intel-gfx] [PATCH v4 02/38] drm: Use drm_mm_nodes() as shorthand for the list of nodes under struct drm_mm

Fairly commonly we want to inspect the node list on the struct drm_mm, which is buried within an embedded node. Bring it to the surface with a bit of syntatic sugar. Note this was intended to be split from commit ad579002c8ec ("drm: Add drm_mm_for_each_node_safe()") before being applied, but my ti

[Intel-gfx] [PATCH v4 24/38] drm: Simplify drm_mm_clean()

Since commit ea7b1dd44867 ("drm: mm: track free areas implicitly"), to test whether there are any nodes allocated within the range manager, we merely have to ask whether the node_list is empty. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 19 +-

[Intel-gfx] [PATCH v4 05/38] drm: Add a simple generator of random permutations

When testing, we want a random but yet reproducible order in which to process elements. Here we create an array which is a random (using the Tausworthe PRNG) permutation of the order in which to execute. Note these are simple helpers intended to be merged upstream in lib/ v2: Tidier code by David

[Intel-gfx] [PATCH v4 20/38] drm/i915: Build DRM range manager selftests for CI

Build the struct drm_mm selftests so that we can trivially run them within our CI. "Enable debug, become developer." - Joonas Lahtinen Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu

[Intel-gfx] [PATCH v4 36/38] drm: Use drm_mm_insert_node_in_range_generic() for everyone

Remove a superfluous helper as drm_mm_insert_node is equivalent to insert_node_in_range with a range of [0, U64_MAX]. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 166 --- include/drm/drm_mm.h | 90 +

[Intel-gfx] [PATCH v4 25/38] drm: Add asserts to catch overflow in drm_mm_init() and drm_mm_init_scan()

A simple assert to ensure that we don't overflow start + size when initialising the drm_mm, or its scanner. In future, we may want to switch to tracking the value of ranges (rather than size) so that we can cover the full u64, for example like resource tracking. Signed-off-by: Chris Wilson Revie

[Intel-gfx] [PATCH v4 13/38] drm: kselftest for drm_mm and alignment

Check that we can request alignment to any power-of-two or prime using a plain drm_mm_node_insert(), and also handle a reasonable selection of primes. v2: Exercise all allocation flags Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/selftests/drm_mm_selftests.h |

[Intel-gfx] [PATCH v4 30/38] drm: Compute tight evictions for drm_mm_scan

Compute the minimal required hole during scan and only evict those nodes that overlap. This enables us to reduce the number of nodes we need to evict to the bare minimum. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c| 60 ++

[Intel-gfx] [PATCH v4 26/38] drm: Extract struct drm_mm_scan from struct drm_mm

The scan state occupies a large proportion of the struct drm_mm and is rarely used and only contains temporary state. That makes it suitable to moving to its struct and onto the stack of the callers. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c

[Intel-gfx] [PATCH v4 37/38] drm: Improve drm_mm search (and fix topdown allocation) with rbtrees

The drm_mm range manager claimed to support top-down insertion, but it was neither searching for the top-most hole that could fit the allocation request nor fitting the request to the hole correctly. In order to search the range efficiently, we create a secondary index for the holes using either t

[Intel-gfx] [PATCH v4 23/38] drm: Detect overflow in drm_mm_reserve_node()

Protect ourselves from a caller passing in node.start + node.size that will overflow and trick us into reserving that node. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/

[Intel-gfx] [PATCH v4 29/38] drm: Fix application of color vs range restriction when scanning drm_mm

The range restriction should be applied after the color adjustment, or else we may inadvertently apply the color adjustment to the restricted hole (and not against its neighbours). Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 15 +-- 1 file

[Intel-gfx] [PATCH v4 33/38] drm: Apply tight eviction scanning to color_adjust

Using mm->color_adjust makes the eviction scanner much tricker since we don't know the actual neighbours of the target hole until after it is created (after scanning is complete). To work out whether we need to evict the neighbours because they impact upon the hole, we have to then check the hole a

[Intel-gfx] [PATCH v4 31/38] drm: Optimise power-of-two alignments in drm_mm_scan_add_block()

For power-of-two alignments, we can avoid the 64bit divide and do a simple bitwise add instead. v2: s/alignment_mask/remainder_mask/ Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 9 - include/drm/drm_mm.h | 1 + 2 files changed, 9 insertion

[Intel-gfx] [PATCH v4 22/38] drm: Fix kerneldoc for drm_mm_scan_remove_block()

The nodes must be removed in the *reverse* order. This is correct in the overview, but backwards in the function description. Whilst here add Intel's copyright statement and tweak some formatting. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/drm_mm.c | 34 +++

Re: [Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the Global GTT for the GuC

On 12/22/2016 2:40 AM, Daniele Ceraolo Spurio wrote: On 21/12/16 06:11, Chris Wilson wrote: The GuC would like to own the upper portion of the GTT for itself, so exclude it from our drm_mm to prevent us using it. I had a quick chat with a GuC dev and he is pretty sure that GuC can't reser

[Intel-gfx] [PATCH v3 1/2] drm: Wrap the check for atomic_commit implementation

This check is useful for drivers that do not have DRIVER_ATOMIC set but have atomic modesetting internally implemented. Wrap the check into a function since this is used in many places and as a bonus, the function name helps to document what the check is for. v2: Change return type to bool (Ville)

Re: [Intel-gfx] [PATCH v3] drm/i915: Check HAS_PCH_NOP when install or reset dispaly IRQ

On Thu, 22 Dec 2016, "Wang, Elaine" wrote: >> >> On Thu, 22 Dec 2016, "Wang, Elaine" wrote: >> > Hi Jani, Ville, >> > >> > Any comment about the "PCH_NOP" vs "num_pipes == 0"? >> > >> > Thanks, >> > Elaine >> >> On Thu, 15 Dec 2016, Ville Syrjälä wrote: >> >> > On Mon, Dec 12, 2016 at 02:57:44P

[Intel-gfx] [PATCH v3 2/2] drm: Get atomic property value even if DRIVER_ATOMIC is not set

i915 does not set DRIVER_ATOMIC by default yet but uses atomic_check and atomic_commit. drm_object_property_get_value() does not read the correct value of atomic properties if DRIVER_ATOMIC is not set. Checking whether the driver uses atomic modeset is a better check instead as the property values

Re: [Intel-gfx] [PATCH v2 1/2] drm: Wrap the check for atomic_commit implementation

On Thu, Dec 22, 2016 at 10:36:01AM +0200, Ander Conselvan De Oliveira wrote: > On Wed, 2016-12-21 at 12:12 -0800, Dhinakaran Pandiyan wrote: > > This check is useful for drivers that do not have DRIVER_ATOMIC set but > > have atomic modesetting internally implemented. Wrap the check into a > > func

Re: [Intel-gfx] [PATCH v2 1/2] drm: Wrap the check for atomic_commit implementation

Done, hope I got it right this time. -DK -Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Thursday, December 22, 2016 12:52 AM To: Ander Conselvan De Oliveira Cc: Pandiyan, Dhinakaran ; intel-gfx@lists.freedesktop.org; Daniel Vette

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v4,01/38] drm/i915: Use the MRU stack search after evicting

== Series Details == Series: series starting with [v4,01/38] drm/i915: Use the MRU stack search after evicting URL : https://patchwork.freedesktop.org/series/17123/ State : warning == Summary == Series 17123v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/17123/

Re: [Intel-gfx] [PATCH v2] drm/i915/ddi: Rely on VBT DDI port info for eDP detection

On Wed, Dec 21, 2016 at 12:17:24PM +0200, Imre Deak wrote: > There is at least one APL based system using port A in DP mode > (connecting to an on-board DP->VGA adaptor). Atm we'll configure port A > unconditionally as eDP which is incorrect in this case. Fix this by > relying on the VBT DDI port '

Re: [Intel-gfx] [git pull] GVT-g fixes for 4.10

On Thu, 22 Dec 2016, Zhenyu Wang wrote: > Hi, > > This is currently GVT-g driver fixes for 4.10-rc2. I can't pull this at this time, because it's based on some commit in Linus' tree instead of some stable tag in Linus' tree or drm-next or drm-intel-next-fixes. Rule of thumb, never rebase on anyth

Re: [Intel-gfx] [PATCH] drm/i915: Force VDD off on the new power seqeuencer before starting to use it

On Tue, Dec 20, 2016 at 06:51:17PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Apparently some VLV BIOSen like to leave the VDD force bit enabled > even for power seqeuncers that aren't properly hooked up to any > port. That will result in a imbalance in the AUX power do

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v4,01/38] drm/i915: Use the MRU stack search after evicting

On Thu, 2016-12-22 at 09:15 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v4,01/38] drm/i915: Use the MRU stack search > after evicting > URL   : https://patchwork.freedesktop.org/series/17123/ > State : warning > > == Summary == > > Series 17123v1 Series with

Re: [Intel-gfx] [PATCH v4 04/38] lib: Add a simple prime number generator

On to, 2016-12-22 at 08:36 +, Chris Wilson wrote: > Prime numbers are interesting for testing components that use multiplies > and divides, such as testing DRM's struct drm_mm alignment computations. > > v2: Move to lib/, add selftest > v3: Fix initial constants (exclude 0/1 from being primes)

Re: [Intel-gfx] [PATCH v4 04/38] lib: Add a simple prime number generator

On Thu, Dec 22, 2016 at 11:52:45AM +0200, Joonas Lahtinen wrote: > On to, 2016-12-22 at 08:36 +, Chris Wilson wrote: > > Prime numbers are interesting for testing components that use multiplies > > and divides, such as testing DRM's struct drm_mm alignment computations. > > > > v2: Move to lib

Re: [Intel-gfx] [PATCH v3 1/3] drm: Create new structure for HDMI info

Hi Shashank, On 21-12-2016 15:29, Shashank Sharma wrote: [snip] > + > + /** > + * @edid_yuv420_dc_modes: bpc for deep color yuv420 encoding. > + * various sinks can support 10/12/16 bit per channel deep > + * color encoding. edid_yuv420_dc_modes = 0 means sink doesn't > +

Re: [Intel-gfx] [PATCH v3 2/3] drm: parse hf-vsdb

Hi Shashank, On 21-12-2016 15:29, Shashank Sharma wrote: > HDMI 2.0 / CEA-861-F specs define a new CEA extension data block, > called hdmi-forum vendor specific data block (HF-VSDB). This block > contains information about sink's support for HDMI 2.0 compliant > features. These features are: >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm: Wrap the check for atomic_commit implementation

== Series Details == Series: series starting with [v3,1/2] drm: Wrap the check for atomic_commit implementation URL : https://patchwork.freedesktop.org/series/17125/ State : success == Summary == Series 17125v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/17125

[Intel-gfx] [PULL] drm-intel-next-fixes

Hi Dave, last i915 fixes for the merge window before v4.10-rc1. Wishing you all the things people usually wish each other this time of the year. BR, Jani. The following changes since commit 7a9e10253e9e52451bbe80ddb2874368dbd240a3: drm/i915: Move priority bumping for flips earlier (2016-12-0

Re: [Intel-gfx] [PATCH v3 3/3] drm: clean cached display info

Hi Shashank, On 21-12-2016 15:29, Shashank Sharma wrote: > This patch adds a small helper function, which clears the cached > information about a hot-pluggable display, from connector. On event > This will run on event of a hot-unplug, keeping the connector's display > info up-to-date, avoiding a

[Intel-gfx] [PATCH] drm/i915: Use atomic page flip for intel again.

This reverts commit 527b6abe5fd2d2 (Revert "drm/i915: Use atomic commits for legacy page_flips") and reapplies commit ee042aa40b66d1. ("drm/i915: Use atomic commits for legacy page_flips") The reason for the revert was because legacy cursor updates were forced to wait for pending page flips and r

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Check num_pipes before initializing or calling display hooks

On Mon, 19 Dec 2016, Wang Elaine wrote: > From: Elaine Wang > > when num_pipes is zero, it indicates display doesn't exist, so there > is no need to initialize display hooks. And to avoid calling these > uninitialized display hooks, respect num_pipes at the beginning of > intel_modeset_init_hw an

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Check num_pipes before initializing audio component

On Mon, 19 Dec 2016, Wang Elaine wrote: > From: Elaine Wang > > when num_pipes is zero, it indicates there is no display and HDMI > audio doesn't exist. > > v2: Move the check from caller to callee for consistency. > > Cc: Chris Wilson > Cc: Joonas Lahtinen > Cc: Jani Nikula > Signed-off-by: E

[Intel-gfx] [PATCH 1/5] drm/i915: Assert that the partial VMA fits within the object

When creating a partial VMA assert that it first fits with the parent object, and that if it covers the whole of the parent a normal view was created instead. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_vma.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/

[Intel-gfx] [PATCH 3/5] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

It is only being used to clear a struct and set the type, after which it is overwritten. Since we no longer check the unset bits of the union, skipping the clear is permissible. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 --- drivers/gpu/drm/i915/i915_gem_gtt.h | 1

[Intel-gfx] [PATCH 2/5] drm/i915: Convert i915_ggtt_view to use an anonymous union

Save a lot of characters by making the union anonymous, with the side-effect of ignoring unset bits when comparing views. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 8 drivers/gpu/drm/i915/i915_gem_gtt.c | 9 - drivers/gpu/drm/i915/i915_gem_gtt.h

[Intel-gfx] [PATCH 4/5] drm/i915: Eliminate superfluous i915_ggtt_view_normal

Since commit 058d88c4330f ("drm/i915: Track pinned VMA"), there is only one user of i915_ggtt_view_normal rodate. Just treat NULL as no special view in pin_to_display() like everywhere else. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_ge

[Intel-gfx] [PATCH 5/5] drm/i915: Extact compute_partial_view()

In order to reuse the partial view for selftesting, extract the common function for computing the view. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 48 + 1 file changed, 29 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Assert that the partial VMA fits within the object

On to, 2016-12-22 at 10:56 +, Chris Wilson wrote: > When creating a partial VMA assert that it first fits with the parent > object, and that if it covers the whole of the parent a normal view was > created instead. > > Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen Regards, Joona

Re: [Intel-gfx] [PATCH 1/2] drm : adds Y-coordinate and Colorimetry Format

On Wed, 21 Dec 2016, vathsala nagaraju wrote: > PSR2 vsc revision number hb2( as per table 6-11)is updated to > 4 or 5 based on Y cordinate and Colorimetry Format as below > 04h = 3D stereo + PSR/PSR2 + Y-coordinate. > 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry > Form

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Eliminate superfluous i915_ggtt_view_normal

On to, 2016-12-22 at 10:56 +, Chris Wilson wrote: > Since commit 058d88c4330f ("drm/i915: Track pinned VMA"), there is only > one user of i915_ggtt_view_normal rodate. Just treat NULL as no special > view in pin_to_display() like everywhere else. > > Signed-off-by: Chris Wilson I had this qu

Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: program vsc header for psr2

On Wed, 21 Dec 2016, vathsala nagaraju wrote: > Function hsw_psr_setup handles vsc header setup for psr1 and > skl_psr_setup_vsc handles vsc header setup for psr2. > > Setup VSC header in function skl_psr_setup_vsc for psr2 support, > as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for ps

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Extact compute_partial_view()

Patch title, s/Extact/Extract/ On to, 2016-12-22 at 10:56 +, Chris Wilson wrote: > In order to reuse the partial view for selftesting, extract the common > function for computing the view. > > Signed-off-by: Chris Wilson With that; Reviewed-by: Joonas Lahtinen Regards, Joonas -- Joonas

Re: [Intel-gfx] [PATCH v3] drm/i915: Check HAS_PCH_NOP when install or reset dispaly IRQ

On Thu, Dec 22, 2016 at 10:52:29AM +0200, Jani Nikula wrote: > On Thu, 22 Dec 2016, "Wang, Elaine" wrote: > >> > >> On Thu, 22 Dec 2016, "Wang, Elaine" wrote: > >> > Hi Jani, Ville, > >> > > >> > Any comment about the "PCH_NOP" vs "num_pipes == 0"? > >> > > >> > Thanks, > >> > Elaine > >> >> On

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Eliminate superfluous i915_ggtt_view_rotated

On to, 2016-12-22 at 10:56 +, Chris Wilson wrote: > It is only being used to clear a struct and set the type, after which it > is overwritten. Since we no longer check the unset bits of the union, > skipping the clear is permissible. > > Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtin

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Convert i915_ggtt_view to use an anonymous union

On to, 2016-12-22 at 10:56 +, Chris Wilson wrote: > Save a lot of characters by making the union anonymous, with the > side-effect of ignoring unset bits when comparing views. > > Signed-off-by: Chris Wilson Daniel could A-b, as he specifically wanted all the bits initialized. > +++ b/dri

Re: [Intel-gfx] [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT

On Thu, 15 Dec 2016, Madhav Chauhan wrote: > From: Vincente Tsou > > The upper bits of the vsync width, vsync offset and hsync width > were not parsed form the VBT. Parse these fields in this patch. > > Signed-off-by: Madhav Chauhan > Signed-off-by: Vincente Tsou The author Signed-off-by shoul

Re: [Intel-gfx] [PATCH] drm/i915: Force VDD off on the new power seqeuencer before starting to use it

On Thu, Dec 22, 2016 at 11:39:37AM +0200, David Weinehall wrote: > On Tue, Dec 20, 2016 at 06:51:17PM +0200, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Apparently some VLV BIOSen like to leave the VDD force bit enabled > > even for power seqeuncers that aren't properly h

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Assert that the partial VMA fits within the object

Hi Chris, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20161222] [cannot apply to v4.9] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm

Re: [Intel-gfx] [PATCH v3 1/3] drm: Create new structure for HDMI info

On Thu, Dec 22, 2016 at 10:02:26AM +, Jose Abreu wrote: > Hi Shashank, > > > On 21-12-2016 15:29, Shashank Sharma wrote: > > [snip] > > > + > > + /** > > +* @edid_yuv420_dc_modes: bpc for deep color yuv420 encoding. > > +* various sinks can support 10/12/16 bit per channel deep >

Re: [Intel-gfx] [PATCH] drm/i915: Force VDD off on the new power seqeuencer before starting to use it

On Thu, Dec 22, 2016 at 01:49:39PM +0200, Ville Syrjälä wrote: > On Thu, Dec 22, 2016 at 11:39:37AM +0200, David Weinehall wrote: > > On Tue, Dec 20, 2016 at 06:51:17PM +0200, ville.syrj...@linux.intel.com > > wrote: > > > From: Ville Syrjälä > > > > > > Apparently some VLV BIOSen like to leave

[Intel-gfx] [PATCH 1/3] drm/i915: Repeat flush of idle work during suspend

The idle work handler is self-arming - if it detects that it needs to run again it will queue itself from its work handler. Take greater care when trying to drain the idle work, and double check that it is flushed. The free worker has a similar issue where it is armed by an RCU task which may be r

[Intel-gfx] [PATCH 2/3] drm/i915: Don't clflush before release phys object

When we teardown the backing storage for the phys object, we copy from the coherent contiguous block back to the shmemfs object, clflushing as we go. Trying to clflush the invalid sg beforehand just oops and would be redundant (due to it already being coherent, and clflushed afterwards). Reported-

[Intel-gfx] [PATCH 3/3] drm/i915: Silence allocation failure during sg_trim()

As trimming the sg table is merely an optimisation that gracefully fails if we cannot allocate a new table, we do not need to report the failure either. Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table") Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem.c

Re: [Intel-gfx] [GLK MIPI DSI V2 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

On Thu, Dec 15, 2016 at 02:31:33PM +0530, Madhav Chauhan wrote: > From: Deepak M > > Program the clk lane and tlpx time count registers > to configure DSI PHY. > > v2: Addressed Jani's Review comments(renamed bit field macros) > > Signed-off-by: Deepak M > Signed-off-by: Madhav Chauhan > ---

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Silence allocation failure during sg_trim()

On to, 2016-12-22 at 12:00 +, Chris Wilson wrote: > As trimming the sg table is merely an optimisation that gracefully fails > if we cannot allocate a new table, we do not need to report the failure > either. > > Fixes: 0c40ce130e38 ("drm/i915: Trim the object sg table") > Signed-off-by: Chris

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Repeat flush of idle work during suspend

On to, 2016-12-22 at 12:00 +, Chris Wilson wrote: > The idle work handler is self-arming - if it detects that it needs to > run again it will queue itself from its work handler. Take greater care > when trying to drain the idle work, and double check that it is flushed. > > The free worker has

Re: [Intel-gfx] [PATCH] drm/i915: Beef up the IPS vs. CRC workaround

On Wed, Dec 21, 2016 at 03:04:43PM -0200, Paulo Zanoni wrote: > Em Qua, 2016-12-21 às 11:31 +0200, ville.syrj...@linux.intel.com > escreveu: > > From: Ville Syrjälä > > > > Oneshot disabling of IPS when CRC capturing is started is > > insufficient. > > IPS may get re-enabled by any plane update,

Re: [Intel-gfx] [PATCH] drm/i915: moved edid read from _force() to _get_modes()

On Wed, Dec 21, 2016 at 02:49:10PM -0800, Anitha Chrisanthus wrote: > From: "Chrisanthus, Anitha" > > When the connector is forced ON and firmware EDID is provided, > driver still tries to read the EDID from the sink device, this can increase > the driver's start up time by ~25ms per attempt. > T

Re: [Intel-gfx] [PATCH v2] drm/i915/ddi: Rely on VBT DDI port info for eDP detection

On Thu, 2016-12-22 at 11:12 +0200, David Weinehall wrote: > On Wed, Dec 21, 2016 at 12:17:24PM +0200, Imre Deak wrote: > > There is at least one APL based system using port A in DP mode > > (connecting to an on-board DP->VGA adaptor). Atm we'll configure port A > > unconditionally as eDP which is i

Re: [Intel-gfx] [GLK MIPI DSI V2 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

On Thu, 22 Dec 2016, Ville Syrjälä wrote: > On Thu, Dec 15, 2016 at 02:31:33PM +0530, Madhav Chauhan wrote: >> From: Deepak M >> >> Program the clk lane and tlpx time count registers >> to configure DSI PHY. >> >> v2: Addressed Jani's Review comments(renamed bit field macros) >> >> Signed-off-

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Don't clflush before release phys object

On to, 2016-12-22 at 12:00 +, Chris Wilson wrote: > When we teardown the backing storage for the phys object, we copy from > the coherent contiguous block back to the shmemfs object, clflushing as > we go. Trying to clflush the invalid sg beforehand just oops and would > be redundant (due to it

Re: [Intel-gfx] [PATCH] drm/i915: Prevent timeline updates whilst performing reset

Chris Wilson writes: > As the fence may be signaled concurrently from an interrupt on another > device, it is possible for the list of requests on the timeline to be > modified as we walk it. Take both (the context's timeline and the global > timeline) locks to prevent such modifications. > > Fix

Re: [Intel-gfx] [PATCH] drm/i915: Move the min_pixclk[] handling to the end of readout

On Tue, 2016-12-20 at 17:39 +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Trying to determine the pixel rate of the pipe can't be done until we > know the clock, which means it can't be done until the encoder > .get_config() hooks have been called. So let's move the min_pi

Re: [Intel-gfx] [PATCH] drm/i915: Move the min_pixclk[] handling to the end of readout

Op 20-12-16 om 16:39 schreef ville.syrj...@linux.intel.com: > From: Ville Syrjälä > > Trying to determine the pixel rate of the pipe can't be done until we > know the clock, which means it can't be done until the encoder > .get_config() hooks have been called. So let's move the min_pixclk[] > stuf

Re: [Intel-gfx] [PATCH 05/14] drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c

On to, 2016-12-22 at 15:10 +0200, Ander Conselvan De Oliveira wrote: > > On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote: > > > > From: Ville Syrjälä > > > > Let's try to shrink intel_display.c a bit by moving the cdclk/rawclk > > stuff to a new file. It's all reasonably s

Re: [Intel-gfx] [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT

> -Original Message- > From: Nikula, Jani > Sent: Thursday, December 22, 2016 5:09 PM > To: Chauhan, Madhav ; intel- > g...@lists.freedesktop.org > Cc: Conselvan De Oliveira, Ander ; > Saarinen, Jani ; Konduru, Chandra > ; Shankar, Uma ; > Mukherjee, Indranil ; Kumar, Shobhit > ; Tsou, Vinc

Re: [Intel-gfx] [PATCH 06/14] drm/i915: Pass computed vco to bxt_set_cdclk()

On Mon, 2016-12-19 at 19:28 +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Rather than compute the vco inside bxt_set_cdclk() let's precompute it > outside and pass it in. A small step towards a fully precomputed cdclk > state. > > Signed-off-by: Ville Syrjälä Reviewed-b

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