>-Original Message-
>From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
>Sent: Thursday, December 1, 2016 5:24 AM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
>
>Hi,
>
>On 30/11/2016 23:
I'm currently considering the use of DRM_ERROR in i915 perf for steam
config validation errors (i.e. userspace misconfigurations) that should
be changed so that i-g-t tests aren't treated as failures when
triggering these.
I initially proposed changing these to DRM_INFO messages and
intentionally
Avoid using DRM_ERROR for conditions userspace can trigger with a bad
config when opening a stream or from not reading data in a timely
fashion (whereby the OA buffer fills up). These conditions are tested
by i-g-t which treats error messages as failures if using the test
runner. This wasn't an iss
On Thu, Dec 01, 2016 at 02:16:37PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Makes all GEM object constructors consistent.
>
> v2: Fix compilation in GVT code.
>
> Signed-off-by: Tvrtko Ursulin
> Reviewed-by: Chris Wilson (v1)
> Reviewed-by: Joonas Lahtinen (v1)
Still lgtm to
On Thu, Dec 01, 2016 at 02:16:40PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> dev_priv is more appropriate for these so converting saves
> some lines of source.
>
> v2: Commit message and keep the pdev local variable. (Joonas Lahtinen)
>
> Signed-off-by: Tvrtko Ursulin
> Reviewed-
== Series Details ==
Series: drm: Enable dynamic debug for DRM_[DEV]_DEBUG*
URL : https://patchwork.freedesktop.org/series/16235/
State : success
== Summary ==
Series 16235v1 drm: Enable dynamic debug for DRM_[DEV]_DEBUG*
https://patchwork.freedesktop.org/api/1.0/series/16235/revisions/1/mbox/
On 01/12/2016 14:45, Patchwork wrote:
== Series Details ==
Series: GEM object create and driver init dev_priv cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/16162/
State : warning
== Summary ==
Series 16162v2 GEM object create and driver init dev_priv cleanups
https://patchw
== Series Details ==
Series: drm/i915/perf: use DRM_DEBUG for userspace issues
URL : https://patchwork.freedesktop.org/series/16236/
State : success
== Summary ==
Series 16236v1 drm/i915/perf: use DRM_DEBUG for userspace issues
https://patchwork.freedesktop.org/api/1.0/series/16236/revisions/1
>-Original Message-
>From: Hiler, Arkadiusz
>Sent: Thursday, December 1, 2016 4:23 AM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Mcgee, Jeff ;
>Kamble, Sagar A
>Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct
>for
>GuC and HuC
>
>On Wed, No
Sean, could you please review this patch, I have tried to address
all the comments from you.
Regards
Manasi
On Tue, Nov 29, 2016 at 11:30:31PM -0800, Manasi Navare wrote:
> At the time userspace does setcrtc, we've already promised the mode
> would work. The promise is based on the theoretical ca
On Thu, Dec 1, 2016 at 1:58 PM, Manasi Navare wrote:
> Sean, could you please review this patch, I have tried to address
> all the comments from you.
>
Comments look good to me.
Reviewed-by: Sean Paul
Sean
> Regards
> Manasi
>
> On Tue, Nov 29, 2016 at 11:30:31PM -0800, Manasi Navare wrote:
>
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: 192aa18142b28fdcb63b12984e02466ced382a54
commit: bf9e8429ab9747f584e692bad52a7a9f1787a4da [3/10] drm/i915: Make various
init functions take dev_priv
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
m
Hi All,
So while trying to fix my cherrytrail tablet's screen sometimes not
initializing properly (*) I started working on this series to cleanup /
(minor) refactor the dsi enable / disable code, with as goal to then
change it to match the enable / disable sequences which Ville Syrjälä
recently du
Looking at the ADF code from the Android kernel sources for a
cherrytrail tablet I noticed that it is calling the
MIPI_SEQ_ASSERT_RESET sequence from the panel prepare hook.
Until commit b1cb1bd29189 ("drm/i915/dsi: update reset and power sequences
in panel prepare/unprepare hooks") the mainline i
Set the CHV_GPIO_GPIOEN bit when updating GPIOs from chv_exec_gpio.
Fixes: a0a6d4ffd2ad ("drm/i915/dsi: add support for gpio elements on CHV")
Cc: sta...@vger.kernel.org
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Hans de Goede
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ds
Instead of calling wait_for_dsi_fifo_empty on all dsi ports after calling
a drm_panel_foo helper which calls VBT sequences, move it to the VBT
mipi_exec_send_packet helper, which is the one VBT instruction which
actually puts data in the fifo.
This results in a nice cleanup making it clearer what
Move the intel_dsi_clear_device_ready() function to higher up in
intel_dsi.c this pairs it with intel_dsi_device_ready(); and pairs
intel_dsi_*enable* with intel_dsi_*disable without
intel_dsi_clear_device_ready() sitting in the middle of them.
This commit purely moves code around, it does not mak
The drm_panel_enable/disable and drm_panel_prepare/unprepare calls are
not fine grained enough to abstract all the different steps we need to
take (and VBT sequences we need to exec) properly. So simply remove the
panel _enable/disable and prepare/unprepare callbacks and instead
export intel_dsi_ex
intel_dsi_disable/enable only have one caller, merge them into their
respective callers.
Change msleep(2) into usleep_range(2000, 5000) to make checkpatch happy,
otherwise no funtional changes.
The main advantage of this change is that it makes it easier to
follow all the steps of the panel enabl
The enable path has an intel_dsi_prepare() helper which prepares various
registers for the mode-set. Move the function undoing this to a new
intel_dsi_unprepare() helper for better symmetry between the enable and
disable paths. No functional changes.
Signed-off-by: Hans de Goede
---
drivers/gpu/
Now that we are no longer bound to the drm_panel_ callbacks, call
MIPI_SEQ_POWER_ON/OFF at the proper place.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers
Document the DSI panel enable / disable sequences from the spec,
for easy comparison between the code and the spec.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi.c | 64
1 file changed, 64 insertions(+)
diff --git a/drivers/gpu/drm/i915
On enable intel_dsi_enable() directly calls intel_enable_dsi_pll(),
make intel_dsi_disable() also directly call intel_disable_dsi_pll(),
rather then hiding the call in intel_dsi_clear_device_ready(),
no functional changes.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi.c | 4 ++-
MIPI_SEQ_ASSERT_RESET before POWER_ON is not necessary for 2 reasons:
1) The reset should already be asserted before intel_dsi_pre_enable()
gets called
2) Most (some?) VBTs will ensure reset was asserted in their
MIPI_SEQ_DEASSERT_RESET themselves
Signed-off-by: Hans de Goede
---
drivers/g
Move the DPOunit clock gate workaround to directly after the PLL enable.
The exact location of the workaround does not matter and there are 2
reasons to group it with the PLL enable:
1) This moves it out of the middle of the init sequence from the spec,
making it easier to follow the init sequ
Execute MIPI_SEQ_DEASSERT_RESET before putting the device in ready
state (LP-11), this is the sequence in which things should be done
according to the spec.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --gi
According to the spec for v2 VBTs we should call MIPI_SEQ_DISPLAY_OFF
before sending SHUTDOWN, where as for v3 VBTs we should send SHUTDOWN
first.
Since the v2 order has known issues, we use the v3 order everywhere,
add a comment documenting this.
Signed-off-by: Hans de Goede
---
drivers/gpu/dr
According to the spec we should call MIPI_SEQ_TEAR_ON and DISPLAY_ON
on enable for cmd-mode, just like we already call their counterparts
on disable. Note: untested, my panel is a vid-mode panel.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi.c | 2 ++
1 file changed, 2 insertio
For v3 VBTs we should call MIPI_SEQ_TEAR_OFF before
MIPI_SEQ_DISPLAY_OFF, for non v3 VBTs this is a nop.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index
Execute the MIPI_SEQ_BACKLIGHT_ON/OFF VBT sequences at the same time as
we call intel_panel_enable_backlight() / intel_panel_disable_backlight().
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gp
For v3 VBTs in vid-mode the delays are part of the VBT sequences, so
we should not also delay ourselves otherwise we get double delays.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/intel_dsi.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drive
On Thu, Dec 01, 2016 at 06:08:25PM +, Tvrtko Ursulin wrote:
> Merged to dinq. Thanks for the review! (And for spotting all the
> places where it is needed.) :)
Oops, better run make htmldocs and catch the important information that
intel_guc_fini() takes dev_priv.
-Chris
--
Chris Wilson, Int
Hi Daniel,
On Thu, 01 Dec 2016 11:02:26 + Daniel Stone wrote:
>
> On Nov 30 2016, at 10:49 pm, Rob Clark wrote:
>
> > yeah, {cgit,anongit}.fd.o have been having problems all day.. (the ssh
> git urls for folks who have push access work fine).. although it has
> worked for me a coupl
Hi Stephen,
On 1 December 2016 at 20:45, Stephen Rothwell wrote:
> On Thu, 01 Dec 2016 11:02:26 + Daniel Stone wrote:
>> Sorry about this, it is quite bad. I think having mirrors for the key DRM
>> trees on GitHub is a good idea though, and I can get to setting that up.
>> Stephen, you need
Some pieces of code are independent of hardware but are very tricky to
exercise through the normal userspace ABI or via debugfs hooks. Being
able to create mock unit tests and execute them through CI is vital.
Start by adding a central point where we can execute unit tests from and
a parameter to e
On Thu, Dec 01, 2016 at 02:23:54PM +0200, Marius Vlad wrote:
> Latest changes include addressing comments from previous version and include
> some notes about driver loading/unloading when using in combination to
> drm_open_driver().
Pushed the first 2 since I had an ulterior motive in writing a i
On Thu, Dec 01, 2016 at 11:32:44PM +, Chris Wilson wrote:
> To facilitate integration with igt, any parameter beginning with
> i915.subtest__ is interpreted as a selftest subtest executable
> independently via igt/drv_selftest.
>
> +#define selftest(name, func) \
> +module_param_named(subtest_
Reviewed-by: Rodrigo Vivi
On Thu, Nov 10, 2016 at 05:23:20PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has 4 planes (3 sprites) per pipe.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 5 -
> 1 file changed, 4 insertions(
Reviewed-by: Rodrigo Vivi
On Thu, Nov 10, 2016 at 05:23:19PM +0200, Ander Conselvan de Oliveira wrote:
> The sequence is pretty much the same as broxton, except that bspec
> requires the AUX domains to be enabled. But since those can't be enabled
> before the phys are initialized, we just use t
Reviewed-by: Rodrigo Vivi
On Thu, Nov 10, 2016 at 05:23:18PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has double wide pipes so it can output two pixels per CD
> clock.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++
== Series Details ==
Series: drm/i915: Provide a hook for selftests
URL : https://patchwork.freedesktop.org/series/16246/
State : success
== Summary ==
Series 16246v1 drm/i915: Provide a hook for selftests
https://patchwork.freedesktop.org/api/1.0/series/16246/revisions/1/mbox/
Test kms_force
Reviewed-by: Rodrigo Vivi
On Thu, Nov 10, 2016 at 05:23:17PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has the same register layout, reference clock and programming
> sequence as broxton. The difference is that it doesn't support the 1.5
> divider and has different ratios, but a lo
Reviewed-by: Rodrigo Vivi
On Thu, Nov 10, 2016 at 05:23:16PM +0200, Ander Conselvan de Oliveira wrote:
> From: Madhav Chauhan
>
> Add steps for enabling and disabling Port PLL as per bspec.
>
> Signed-off-by: Madhav Chauhan
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/g
Reviewed-by: Rodrigo Vivi
On Thu, Nov 10, 2016 at 05:23:13PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has power wells are similar to SKL, but with the misc IO well
> being split into separate AUX IO wells.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/dr
This could be squashed to the other bit patch with s/broxton/gen9_lp...
but anyway
Reviewed-by: Rodrigo Vivi
On Thu, Nov 10, 2016 at 05:23:12PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake uses the same lane latency optimization masks and registers
> as Broxton, so reuse the code wi
This could also be squashed or reviewed-by you...
either works for me, I just cannot review the patch that I'm listed as author ;)
On Thu, Nov 10, 2016 at 05:23:11PM +0200, Ander Conselvan de Oliveira wrote:
> From: Rodrigo Vivi
>
> As for BXT, GLK doesn't support port detection through SFUSE_S
A reviewed backwards because I was willing to check if all ifs were in place.
I missed the ones from i915_drv.c
*** i915_drv.c:
i915_drm_suspend_late[1500]fw_csr = !IS_GEN9_LP(dev_priv) &&
i915_drm_suspend_late[1513]if (IS_GEN9_LP(dev_priv))
i915_drm_resume_early[1721]if (IS_GEN9_LP(d
Supported link rate common to source and sink as well as the
maximum supported lane count based on source and sink capabilities should
be set only once on hotplug and then used anytime they are requested.
This patch creates and array of common rates and max lane count as the
intel_dp member. It get
== Series Details ==
Series: drm/i915: Calculate common rates and max lane count in Long pulse
handler
URL : https://patchwork.freedesktop.org/series/16250/
State : warning
== Summary ==
Series 16250v1 drm/i915: Calculate common rates and max lane count in Long
pulse handler
https://patchwor
Any comments? Thanks.
Regards,
Libin
>-Original Message-
>From: Yang, Libin
>Sent: Thursday, December 1, 2016 1:17 PM
>To: intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com;
>ville.syrj...@linux.intel.com; Vetter, Daniel ;
>Pandiyan, Dhinakaran ; ti...@suse.de
>Cc: Yang, Libin
On Thu, Dec 01, 2016 at 01:44:14PM +0530, swati.dhin...@intel.com wrote:
> From: Swati Dhingra
>
> Currently, for the purpose of providing output debug/loggging/crc and various
> other kinds of data from DRM layer to userspace, we don't have a standard
> filesystem, which would suffice for all th
On Thu, Dec 01, 2016 at 01:44:15PM +0530, swati.dhin...@intel.com wrote:
> From: Swati Dhingra
>
> The patch introduces a new pseudo filesystem type, named 'drmfs' which is
> intended to house the files for the data generated by drm subsystem that
> cannot be accommodated by any of the existing f
On Tue, 2016-11-29 at 13:48 +0200, Ander Conselvan de Oliveira wrote:
> In commit c39055b072f8 ("drm/i915: Pass dev_priv to
> intel_setup_outputs()"), I forgot to update the kerneldoc for
> intel_psr_init() init, leading to warnings when building the
> documentation:
>
> drivers/gpu/drm/i915/i
On Thu, Dec 01, 2016 at 01:44:16PM +0530, swati.dhin...@intel.com wrote:
> From: Swati Dhingra
>
> During drm module initialization, drm_core_init initializes the drmfs
> filesystem and register this with kernel. A driver specific directory is
> created
> inside drmfs root, and dentry of this di
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