On Wed, Sep 07, 2016 at 12:47:49PM +0300, Mika Kahola wrote:
> On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> > According to the DisplayPort Spec, in case of Clock Recovery failure
> > the link training sequence should fall back to the lower link rate
> > followed by lower lane count unt
This fixes the error path for platforms that don't define the new
page_flip_target() hook.
Fixes: c229bfbbd04 ("drm: Add page_flip_target CRTC hook v2")
Testcase: igt/kms_flip/basic-flip-vs-dpms
CC: Michel Dänzer
Signed-off-by: Imre Deak
---
drivers/gpu/drm/drm_crtc.c | 2 +-
1 file changed, 1
Between v2 and v3 of this patch,
c4e68a583202 ("drm: Introduce DRM_DEV_* log messages")
was introduced upstream, and this was the reason for the rewrite as v3.
Unfortunately a maintainer pushed the earlier version to drm-intel-next
30b0da8d556e ("drm: extra printk() wrapper macros")
creating a
On 26/08/16 20:55, Chris Wilson wrote:
On Fri, Aug 26, 2016 at 08:46:25PM +0100, Dave Gordon wrote:
@@ -1520,6 +1528,14 @@ static void eb_export_fence(struct drm_i915_gem_object
*obj,
if (ret)
return ret;
+ if (instp_mode != I915_EXEC_CONSTANTS_REL_GENERAL) {
+
== Series Details ==
Series: drm: Fix error path in drm_mode_page_flip_ioctl()
URL : https://patchwork.freedesktop.org/series/12129/
State : failure
== Summary ==
Series 12129v1 drm: Fix error path in drm_mode_page_flip_ioctl()
http://patchwork.freedesktop.org/api/1.0/series/12129/revisions/1/
The existing code that accesses the "enable_guc_submission"
parameter uses explicit numerical values for the various
possibilities, including in one case relying on boolean 0/1
mapping to specific values (which could be confusing for
maintainers).
So this patch just provides and uses names for the
The existing code that accesses the "guc_log_level" parameter
uses an explicit numerical value for the "no logging" case,
whereas there are symbolic names for the other levels.
So this patch just provides and uses a name for the default log
level (NONE), with the same numeric value that is already
There are various literal constants used in the GuC module-parameter
processing code; this sequence of patches replaces them with symbolic
names for greater clarity.
And then it re-enables GuC submission by default
v3:
Original patch broken into two (1/4 + 2/4)
Name for GuC log level NONE ad
The existing code that accesses the "enable_guc_loading"
parameter uses explicit numerical values for the various
possibilities, including in one case relying on boolean
0/1 mapping to specific values (which could be confusing
for maintainers).
So this patch just provides and uses names for the v
Previously the code allowed *any* values for the enable_guc_loading and
enable_guc_submission parameters, and forced them into range by clipping
at each extremum. This version instead ignores unknown values, treating
them as DEFAULT (which then gets converted to DISABLED or PREFERRED).
Of course w
Of course, this also re-enables GuC loading and submission
by default on suitable platforms, since it's Intel's Plan
of Record that GuC submission shall be used where available.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_params.c | 10 +-
1 file changed, 5 insertions(+), 5
== Series Details ==
Series: drm: two more (drm_)printk() wrapper macros (fixup)
URL : https://patchwork.freedesktop.org/series/12130/
State : failure
== Summary ==
Series 12130v1 drm: two more (drm_)printk() wrapper macros (fixup)
http://patchwork.freedesktop.org/api/1.0/series/12130/revision
According to the DisplayPort Spec, in case of Clock Recovery failure
the link training sequence should fall back to the lower link rate
followed by lower lane count until CR succeeds.
On CR success, the sequence proceeds with Channel EQ.
In case of Channel EQ failures, it should fallback to
lower l
From: Durgadoss R
To support USB type C alternate DP mode, the display driver needs to
know the number of lanes required by the DP panel as well as number
of lanes that can be supported by the type-C cable. Sometimes, the
type-C cable may limit the bandwidth even if Panel can support
more lanes.
From: Dhinakaran Pandiyan
This function cleans up clock recovery loop in link training compliant
tp Dp Spec 1.2. It tries the clock recovery 5 times for the same voltage
or until max voltage swing is reached and removes the additional non
compliant retries. This function now returns a boolean val
From: Dhinakaran Pandiyan
Wrap the max. vswing check in a separate function.
This makes the clock recovery phase of DP link training cleaner
v3:
Fixed the paranthesis warning (Mika Kahola)
v2:
Fixed the Compiler warning (Mika Kahola)
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Manasi Nav
On Wed, Aug 17, 2016 at 01:49:42PM +0300, Mika Kahola wrote:
> Let's remove reference to "struct intel_connector *connector"
> in intel_dp_aux_init() function as it is no longer required.
>
> Signed-off-by: Mika Kahola
Reviewed-by: Jim Bride
> ---
> drivers/gpu/drm/i915/intel_dp.c | 4 ++--
>
On Wed, Aug 17, 2016 at 01:49:43PM +0300, Mika Kahola wrote:
> HW revision is mandatory field for DisplayPort branch
> devices. This is defined in DPCD register field 0x509.
>
> v2: move drm_dp_ds_revision structure to be part of
> drm_dp_link structure (Daniel)
> v3: remove dependency to drm_
On 2016-09-07 16:49, Jani Nikula wrote:
On Tue, 06 Sep 2016, li...@eikelenboom.it wrote:
On 2016-09-06 11:25, Jani Nikula wrote:
On Tue, 06 Sep 2016, li...@eikelenboom.it wrote:
L.S.,
Since one of the last 4.8 RC's i'm getting the warning below when
booting on my sandybridge based thinkpad.
On Wed, Aug 17, 2016 at 01:49:44PM +0300, Mika Kahola wrote:
> SW revision is mandatory field for DisplayPort branch
> devices. This is defined in DPCD register field 0x50A.
To be precise, the revision info is in 0x50A and 0x50B. Since
both the major and minor versions are called out separately
in
On Wed, Aug 17, 2016 at 01:49:45PM +0300, Mika Kahola wrote:
> Filter out a mode that exceeds the max pixel rate setting
> for DP to VGA dongle. This is defined in DPCD register 0x81
> if detailed cap info i.e. info field is 4 bytes long and
> it is available for DP downstream port.
>
> The regist
On Wed, Aug 17, 2016 at 01:49:47PM +0300, Mika Kahola wrote:
> DisplayPort branch device may define max supported bits per
> component. Update display info based on this value if bpc
> is defined.
>
> v2: cleanup to match the drm_dp_helper.c patches introduced
> earlier in this series
> v3: Fi
On Wed, Aug 17, 2016 at 01:49:48PM +0300, Mika Kahola wrote:
> Read DisplayPort branch device info from through debugfs
> interface.
>
> v2: use drm_dp_helper routines to collect data
> v3: cleanup to match the drm_dp_helper.c patches introduced
> earlier in this series
> v4: move DP branch de
On Wed, Aug 17, 2016 at 01:49:49PM +0300, Mika Kahola wrote:
> Respect max TMDS clock frequency from DPCD for active
> DP to HDMI adapters.
>
> Signed-off-by: Mika Kahola
Reviewed-by: Jim Bride
> ---
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> drivers/gpu/drm/i915/intel_hdmi.c | 27 ++
On Fri, Sep 02, 2016 at 01:06:32PM -0700, Pandiyan, Dhinakaran wrote:
> On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > From: Jim Bride
> >
> > Add the PLL selection code for HSW/BDW/BXT/SKL into a stand-alone function
> > in order to allow for the implementation of a platform neutral
From: Jim Bride
Add the PLL selection code for HSW/BDW/BXT/SKL into a stand-alone function
in order to allow for the implementation of a platform neutral upfront
link training function.
v4:
* Removed dereferencing NULL pointer in case of failure (Dhinakaran Pandiyan)
v3:
* Add Hooks for all DDI
Reviewed-by: Rodrigo Vivi
On Wed, Aug 17, 2016 at 12:30:41PM -0700, Carlos Santa wrote:
> No need for HAS_CORE_RING_FREQ as that flag is actually the same as
> .has_llc. Feedback from V. Syrjala.
>
> Signed-off-by: Carlos Santa
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gp
Reviewed-by: Rodrigo Vivi
On Wed, Aug 17, 2016 at 12:30:45PM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct
>
Reviewed-by: Rodrigo Vivi
On Wed, Aug 17, 2016 at 12:30:40PM -0700, Carlos Santa wrote:
> Remove runtime PM support for SNB as it breaks hotplug support.
> Feedback from V. Syrjala.
>
> Signed-off-by: Carlos Santa
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Rodrigo Vivi
On Wed, Aug 17, 2016 at 12:30:39PM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct
>
On 07/09/16 18:03, Dave Gordon wrote:
> On 06/09/16 21:36, Nicolas Iooss wrote:
>> On 06/09/16 12:21, Dave Gordon wrote:
>>> On 04/09/16 19:58, Nicolas Iooss wrote:
When building the kernel with clang and some warning flags, the
compiler
reports that the return value of dcs_get_backl
On Tue, 2016-09-06 at 21:52 -0300, Paulo Zanoni wrote:
> During watermarks calculations, this value is used in 3 different
> places. Only one of them was not using a hardcoded 4. Move the code
> up
> so everybody can benefit from the actual value.
>
> This should only help on situations with Y til
For patches 6-8:
Reviewed-by: Lyude
On Tue, 2016-09-06 at 21:52 -0300, Paulo Zanoni wrote:
> Hi
>
> This series is the result of me comparing the code against BSpec. It
> doesn't solve any particular problem I was seeing, but there's enough
> changes that this code could potentially change the
On Wed, 2016-08-31 at 18:09 +0200, Daniel Vetter wrote:
> Now that there's less stuff in there I noticed that I overlooked
> them.
> Sprinkle some docs over them while at it.
>
> Signed-off-by: Daniel Vetter
> ---
> include/drm/drm_connector.h | 24 ++--
> include/drm/drm_c
According to the DisplayPort Spec, in case of Clock Recovery failure
the link training sequence should fall back to the lower link rate
followed by lower lane count until CR succeeds.
On CR success, the sequence proceeds with Channel EQ.
In case of Channel EQ failures, it should fallback to
lower l
On Wed, 2016-09-07 at 15:37 +0300, Jani Nikula wrote:
> On Sun, 04 Sep 2016, Dominik Brodowski wrote:
> > Hi!
> >
> > Since commit 1c80c25fb6 (determined by git bisect, and confirmed by
> > reverting this patch on top of 9ca581b50d), the sceen on my DELL XPS 13
> > is flickering every once in a wh
This reverts commit 1c80c25fb622973dd135878e98d172be20859049.
There are panels that needs 4 idle frames before entering PSR,
but VBT is unproperly set.
Also lately it was identified that idle frame count calculated at HW
can be off by 1, what makes the minimum of 2, at least.
Without the current
== Series Details ==
Series: Revert "drm/i915/psr: Make idle_frames sensible again"
URL : https://patchwork.freedesktop.org/series/12148/
State : warning
== Summary ==
Series 12148v1 Revert "drm/i915/psr: Make idle_frames sensible again"
http://patchwork.freedesktop.org/api/1.0/series/12148/re
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/intel_pm.c
between commit:
9909113cc48a ("drm/i915/gen9: Only copy WM results for changed pipes to
skl_hw")
from Linus' tree and commits:
2722efb90b34 ("drm/i915/gen9: Only copy WM results fo
On 08/09/16 02:23 AM, Imre Deak wrote:
> This fixes the error path for platforms that don't define the new
> page_flip_target() hook.
>
> Fixes: c229bfbbd04 ("drm: Add page_flip_target CRTC hook v2")
> Testcase: igt/kms_flip/basic-flip-vs-dpms
> CC: Michel Dänzer
> Signed-off-by: Imre Deak
> ---
On ke, 2016-09-07 at 15:45 +0100, Chris Wilson wrote:
> If we find a ring waiting on a semaphore for another assigned but not yet
> emitted request, treat it as valid and waiting.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas Lahtinen
Open Source Techn
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