On Thu, Jun 30, 2016 at 05:04:42PM -0700, James Xiong wrote:
> From: "Xiong, James"
>
> currently mmap of a tiled object that is larger than mappable
> aperture is rejected in fault handler, and causes sigbus error
> and application crash.
Please note that SIGBUS can be returned at any time. If
On 06/29/2016 06:24 PM, Shobhit Kumar wrote:
From: Shobhit Kumar
CHV pipe C hits underrun when we get negative crtc_x values of cursor.
To avoid this we clip and shift the cursor image by negative crtc_x
value.
v2: Make a copy of cursor plane state and allocate new gem object and fb
for cl
Consolidate the block of default vfuncs for dispatching the batchbuffer.
Just a minor tweak on top of Tvrtko's great job of tidying up the vfunc
initialisation.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 27 ++-
1 file ch
Just plonk all the default irq vfuncs together in one function to keep
the initialisers of reasonable size.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 43 ++---
1 file changed, 24 insertions(+), 19 deletions(-)
diff
On 01/07/16 09:18, Chris Wilson wrote:
Consolidate the block of default vfuncs for dispatching the batchbuffer.
Just a minor tweak on top of Tvrtko's great job of tidying up the vfunc
initialisation.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c
== Series Details ==
Series: series starting with [1/2] drm/i915/ringbuffer: Move all generic
engine->dispatch_batchbuffer together
URL : https://patchwork.freedesktop.org/series/9357/
State : failure
== Summary ==
Series 9357v1 Series without cover letter
http://patchwork.freedesktop.org/api
On 01/07/16 09:18, Chris Wilson wrote:
Just plonk all the default irq vfuncs together in one function to keep
the initialisers of reasonable size.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 43 ++---
1 file chang
On Fri, Jul 01, 2016 at 08:41:03AM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/ringbuffer: Move all generic
> engine->dispatch_batchbuffer together
> URL : https://patchwork.freedesktop.org/series/9357/
> State : failure
>
> == Summary ==
>
>
On 01/07/16 07:16, Goel, Akash wrote:
[snip]
+/* Process all the GuC to Host events in bottom half */
+gen6_disable_pm_irq(dev_priv,
+GEN9_GUC_TO_HOST_INT_EVENT);
Why it is important to disable the interrupt here? Not for the queue
work I think.
W
On 01/07/16 06:20, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] Revert "drm/i915/kbl: drm/i915: Avoid GuC
> loading for now on Kabylake."
> URL : https://patchwork.freedesktop.org/series/9332/
> State : failure
>
> == Summary ==
>
> Series 9332v1 Series with
On Fri, Jul 01, 2016 at 09:52:05AM +0100, Tvrtko Ursulin wrote:
>
> On 01/07/16 06:20, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [1/2] Revert "drm/i915/kbl: drm/i915: Avoid
> > GuC loading for now on Kabylake."
> > URL : https://patchwork.freedesktop.org/se
On 01/07/16 09:52, Tvrtko Ursulin wrote:
>
> On 01/07/16 06:20, Patchwork wrote:
>> == Series Details ==
>>
>> Series: series starting with [1/2] Revert "drm/i915/kbl: drm/i915: Avoid GuC
>> loading for now on Kabylake."
>> URL : https://patchwork.freedesktop.org/series/9332/
>> State : failur
On pe, 2016-07-01 at 12:19 +0530, Kamble, Sagar A wrote:
> Have seen BIOS having option "RC6" disabled and "GTPM" enabled for cases
> where there are RC6 specific issues.
It's possible although I haven't seen any based on the specs I have and
the tests I ran. In any case the checks I added shoul
From: Tvrtko Ursulin
These messages are not errors unless GuC loading or submission is
in the mandatory mode and even then the final status will be
logged as error in intel_guc_setup.
Therefore demote the messages in guc_fw_fetch to DRM_DEBUG_DRIVER.
If more detail about the cause of the fail i
On Fri, Jul 01, 2016 at 10:35:12AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> These messages are not errors unless GuC loading or submission is
> in the mandatory mode and even then the final status will be
> logged as error in intel_guc_setup.
>
> Therefore demote the messages in g
Pooled EU is a bxt only feature and kernel changes are already merged. This
feature is not yet exposed to userspace as the support was not yet
available. Beignet team expressed interest and added patches to use this.
Since we now have a user and patches to use them, expose them from the
kernel sid
On 7/1/2016 2:17 PM, Tvrtko Ursulin wrote:
On 01/07/16 07:16, Goel, Akash wrote:
[snip]
+/* Process all the GuC to Host events in bottom half */
+gen6_disable_pm_irq(dev_priv,
+GEN9_GUC_TO_HOST_INT_EVENT);
Why it is important to disable the inter
From: Tvrtko Ursulin
These messages are not errors unless GuC loading or submission is
in the mandatory mode and even then the final status will be
logged as error in intel_guc_setup.
Therefore demote the messages in guc_fw_fetch to DRM_DEBUG_DRIVER.
If more detail about the cause of the fail i
== Series Details ==
Series: drm/i915/guc: Demote some firmware loading messages to debug
URL : https://patchwork.freedesktop.org/series/9366/
State : warning
== Summary ==
Series 9366v1 drm/i915/guc: Demote some firmware loading messages to debug
http://patchwork.freedesktop.org/api/1.0/serie
== Series Details ==
Series: drm/i915/bxt: Export pooled eu info to userspace
URL : https://patchwork.freedesktop.org/series/9367/
State : failure
== Summary ==
CC drivers/acpi/acpica/uthex.o
CC drivers/acpi/acpica/utids.o
CC drivers/acpi/acpica/utinit.o
CC drivers/
== Series Details ==
Series: drm/i915/guc: Demote some firmware loading messages to debug (rev2)
URL : https://patchwork.freedesktop.org/series/9366/
State : failure
== Summary ==
Series 9366v2 drm/i915/guc: Demote some firmware loading messages to debug
http://patchwork.freedesktop.org/api/1.
Pooled EU is a bxt only feature and kernel changes are already merged. This
feature is not yet exposed to userspace as the support was not yet
available. Beignet team expressed interest and added patches to use this.
Since we now have a user and patches to use them, expose them from the
kernel sid
On 7/1/2016 2:45 PM, Imre Deak wrote:
On pe, 2016-07-01 at 12:19 +0530, Kamble, Sagar A wrote:
Have seen BIOS having option "RC6" disabled and "GTPM" enabled for cases
where there are RC6 specific issues.
It's possible although I haven't seen any based on the specs I have and
the tests I ran
== Series Details ==
Series: drm/i915/bxt: Export pooled eu info to userspace (rev2)
URL : https://patchwork.freedesktop.org/series/9367/
State : success
== Summary ==
Series 9367v2 drm/i915/bxt: Export pooled eu info to userspace
http://patchwork.freedesktop.org/api/1.0/series/9367/revisions/
Since those clamoring for the RC6 hole to be plugged are on holiday and
didn't leave a review on the regression fixes, let's push this ahead of
their return. Just a small number of patches left without r-b and then
after almost 12 months of waiting we can close a critical customer
issue.
[PATCH 02
The queue only ever contains at most one item and has no special flags.
It is just a very simple wrapper around the system-wq - a complication
with no benefits.
v2: Use the system_long_wq as we may wish to capture the error state
after detecting the hang - which may take a bit of time.
Signed-off
We can forgo queuing the hangcheck from the start of every request to
until we wait upon a request. This reduces the overhead of every
request, but may increase the latency of detecting a hang. Howeever, if
nothing every waits upon a hang, did it ever hang? It also improves the
robustness of the wa
As we inspect obj->active to decide how many objects we can shrink (we
only shrink idle objects), it helps to flush the active lists first
in order to have a more accurate count of available objects.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_shrin
Currently __i915_wait_request uses a per-engine wait_queue_t for the dual
purpose of waking after the GPU advances or for waking after an error.
In the future, we may add even more wake sources and require greater
separation, but for now we can conceptually simplify wakeups by separating
the two so
One particularly stressful scenario consists of many independent tasks
all competing for GPU time and waiting upon the results (e.g. realtime
transcoding of many, many streams). One bottleneck in particular is that
each client waits on its own results, but every client is woken up after
every batch
When waiting for an interrupt (waiting for the engine to complete some
work), we know we are the only waiter to be woken on this engine. We also
know when the GPU has nearly completed our request (or at least started
processing it), so after being woken and we detect that the GPU is
active and work
If we flag the seqno as potentially stale upon receiving an interrupt,
we can use that information to reduce the frequency that we apply the
heavyweight coherent seqno read (i.e. if we wake up a chain of waiters).
v2: Use cmpxchg to replace READ_ONCE/WRITE_ONCE for more explicit
control of the ord
If we have multiple waiters, we may find that many complete on the same
wake up. If we first inspect the seqno from the CPU cache, we may reduce
the number of heavyweight coherent seqno reads we require.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h
With the last direct CPU access to the scratch page removed, we can now
allocate it from our small amount of reserved system pages (stolen
memory).
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +++-
1 file changed, 3 insertions(+), 1 de
Since the function is a small wrapper around schedule_delayed_work(),
move it inline to remove the function call overhead for the principle
caller.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 18 +-
drivers/gpu/drm/i915/i915_irq.
The gen2 w/a buffer is stuffed into the same slot as the gen5+ scratch
buffer. If we pass in the size we want to allocate for the scratch
buffer, both callers can use the same routine.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c| 2 +-
d
On Ironlake, there is no command nor register to ensure that the write
from a MI_STORE command is completed (and coherent on the CPU) before the
command parser continues. This means that the ordering between the seqno
write and the subsequent user interrupt is undefined (like gen6+). So to
ensure t
With only a single callsite for intel_engine_cs->irq_get and ->irq_put,
we can reduce the code size by moving the common preamble into the
caller, and we can also eliminate the reference counting.
For completeness, as we are no longer doing reference counting on irq,
rename the get/put vfunctions
Under the assumption that enabling signaling will be a frequent
operation, lets preallocate our attachments for signaling inside the
(rather large) request struct (and so benefiting from the slab cache).
v2: Convert from void * to more meaningful names and types.
Signed-off-by: Chris Wilson
Revi
Since the tests can and do explicitly check debugfs/i915_ring_missed_irqs
for the handling of a "missed interrupt", adding it to the dmesg at INFO
is just noise. When it happens for real, we still class it as an ERROR.
Note that I have chose to remove it entirely because when we detect the
"missed
Borrow the idea from intel_lrc.c to precompute the mask of interrupts we
wish to always enable to avoid having lots of conditionals inside the
interrupt enabling.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 34 +++
We have testcases to ensure that seqno wraparound works fine, so we can
forgo forcing everyone to encounter seqno wraparound during early
uptime. seqno wraparound incurs a full GPU stall so not forcing it
will eliminate one jitter from the early system. Using the testcases, we
have very determinist
If we convert the tracing over from direct use of ring->irq_get() and
over to the breadcrumb infrastructure, we only have a single user of the
ring->irq_get and so we will be able to simplify the driver routines
(eliminating the redundant validation and irq refcounting).
Process context is preferr
After the elimination of using the scratch page for Ironlake's
breadcrumb, we no longer need to kmap the object. We therefore can move
it into the high unmappable space and do not need to force the object to
be coherent (i.e. snooped on !llc platforms).
Signed-off-by: Chris Wilson
Reviewed-by: Tv
By using the same address for storing the HWS on every platform, we can
remove the platform specific vfuncs and reduce the get-seqno routine to
a single read of a cached memory location.
v2: Fix semaphore_passed() to look at the signaling engine (not the
waiter's)
Signed-off-by: Chris Wilson
---
== Series Details ==
Series: series starting with [01/20] drm/i915/shrinker: Flush active on objects
before counting
URL : https://patchwork.freedesktop.org/series/9370/
State : failure
== Summary ==
Series 9370v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/937
On Fri, Jul 01, 2016 at 11:43:02AM +0100, Arun Siluvery wrote:
> Pooled EU is a bxt only feature and kernel changes are already merged. This
> feature is not yet exposed to userspace as the support was not yet
> available. Beignet team expressed interest and added patches to use this.
>
> Since we
On ke, 2016-06-29 at 17:06 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Fix log type for RC6
> debug messages
> URL : https://patchwork.freedesktop.org/series/9285/
> State : success
Thanks for the review, I pushed the patches to -dinq.
> == S
Found a problem: After screensaver kicked in and display was turned off
the brightness keys stop working.
Problem can be reproduced like that:
1. Boot laptop
2. Test brightness keys, they are working
3. open Terminal and issue "xset -display :0 dpms force off"
4. the screen goes blank (like after
This is due to commit d308bb082d429eb25 (lib: Start weaning off defunct
intel_chipset.h) which ``moved'' i915_pciids.h to lib/ from overlay/.
Signed-off-by: Marius Vlad
CC: Chris Wilson
---
overlay/Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/overlay/Makefile.
Signed-off-by: Marius Vlad
CC: Chris Wilson
---
tests/gvt_basic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gvt_basic.c b/tests/gvt_basic.c
index 9e17f29..056c472 100644
--- a/tests/gvt_basic.c
+++ b/tests/gvt_basic.c
@@ -26,7 +26,7 @@
IGT_TEST_DESCRIPTION("Bas
On Fri, Jul 01, 2016 at 03:32:44PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
> CC: Chris Wilson
> ---
> tests/gvt_basic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
This is a stub that I expect to be filled with subtests. I want to keep
it easy for people to add tests.
On Fri, Jul 01, 2016 at 03:32:45PM +0300, Marius Vlad wrote:
> This is due to commit d308bb082d429eb25 (lib: Start weaning off defunct
> intel_chipset.h) which ``moved'' i915_pciids.h to lib/ from overlay/.
>
> Signed-off-by: Marius Vlad
> CC: Chris Wilson
The line can be dropped from sources,
On 01/07/2016 12:56, Chris Wilson wrote:
On Fri, Jul 01, 2016 at 11:43:02AM +0100, Arun Siluvery wrote:
Pooled EU is a bxt only feature and kernel changes are already merged. This
feature is not yet exposed to userspace as the support was not yet
available. Beignet team expressed interest and ad
On 6/30/2016 5:37 PM, Rodrigo Vivi wrote:
From: Peter Antoine
This patch added the loading of the GuC for Kabylake.
It loads a 9.14 firmware.
Hello, in case you need a fresh r-b for v3:
v2: Fix commit message
v3: Fix major/minor var names to match -nightly. (Rodrigo)
Cc: Christophe Prigent
Right, but bare in mind that it can't be released as is...
On Fri, Jul 01, 2016 at 01:33:02PM +0100, Chris Wilson wrote:
> On Fri, Jul 01, 2016 at 03:32:44PM +0300, Marius Vlad wrote:
> > Signed-off-by: Marius Vlad
> > CC: Chris Wilson
> > ---
> > tests/gvt_basic.c | 2 +-
> > 1 file changed, 1
On Fri, Jul 01, 2016 at 01:33:36PM +0100, Chris Wilson wrote:
> On Fri, Jul 01, 2016 at 03:32:45PM +0300, Marius Vlad wrote:
> > This is due to commit d308bb082d429eb25 (lib: Start weaning off defunct
> > intel_chipset.h) which ``moved'' i915_pciids.h to lib/ from overlay/.
> >
> > Signed-off-by:
This patch adds the HuC Loading for the BXT.
Version 1.7 of the HuC firmware.
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
b/drivers/gpu/drm/i915/intel_huc_loader.c
ind
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
v2: rebased on top of drm-intel-nightly.
changed name format and upped version 1.7.
Signed-off-by: Alex Dai
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_guc_submission.c | 65
HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.
v2: rebased on-top of drn-intel-nightly
Signed-off-by: Al
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon
This patch series enables the HuC loading. These patches are a port of the
patches that were created by Yu Dai (Alex) and have been ported to work with
the new GuC patches.
The series include a patch to enable the HuC on BXT. This is a separate patch
as the state of the BXT HuC firmware is still i
Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
s/intel_guc_fw/intel_uc_fw/g
s/GUC_FIRMWARE/UC_FIRMWARE/g
Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to '
Add debugfs entry for HuC loading status check.
v2: rebase on-top of drm-intel-nightly.
Signed-off-by: Alex Dai
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_debugfs.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_d
On Fri, Jul 01, 2016 at 04:19:31PM +0300, Marius Vlad wrote:
> On Fri, Jul 01, 2016 at 01:33:36PM +0100, Chris Wilson wrote:
> > On Fri, Jul 01, 2016 at 03:32:45PM +0300, Marius Vlad wrote:
> > > This is due to commit d308bb082d429eb25 (lib: Start weaning off defunct
> > > intel_chipset.h) which ``
On Fri, Jul 01, 2016 at 04:18:46PM +0300, Marius Vlad wrote:
> Right, but bare in mind that it can't be released as is...
Why not? Which bit of infrastructure is broken?
Just add a igt_subtest_f("placeholder") ;
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Use named struct initializers for clarity. Also fix the target cache
definition to reflect its role in GEN9 onwards. On GEN8 a TC value of 0
meant ELLC but on GEN9+ it means the TC and LRU controls are taken from
the PTE.
No functional change, igt/gem_mocs_settings still passing after this
change.
This is v3 of [1] addressing Ville's and Chris' comments. On Daniel's
request I also discussed about these changes with Rong R Yang from the
Beignet and Yakui Zhao from the Libva team, they are CC'd.
Rong, Yakui please add your Acked-by/Tested-by if you are ok with the
changes.
I suggest merging
Setting a write-back cache policy in the MOCS entry definition also
implies snooping, which has a considerable overhead. This is
unexpected for a few reasons:
- From user-space's point of view since it didn't want a coherent
surface (it didn't set the buffer as such via the set caching IOCTL).
-
The purpose for each MOCS entry isn't well defined atm. Defining these
is important to remove any uncertainty about the use of these entries
for example in terms of performance and GPU/CPU coherency.
Suggested by Ville.
CC: Rong R Yang
CC: Yakui Zhao
CC: Ville Syrjälä
CC: Chris Wilson
Signed-
On 30/06/2016 09:43, Song, Ruiling wrote:
LGTM
Ruiling
Could you please let me know whether these patches are merged/yet to be
merged?
I have submitted kernel patch which is ready to be merged but we would
like to know if userspace bits are merged or not?
https://lists.freedesktop.org/ar
On Fri, Jul 01, 2016 at 04:40:06PM +0300, Imre Deak wrote:
> The purpose for each MOCS entry isn't well defined atm. Defining these
> is important to remove any uncertainty about the use of these entries
> for example in terms of performance and GPU/CPU coherency.
>
> Suggested by Ville.
>
> CC:
On Fri, 01 Jul 2016, Rainer Koenig wrote:
> Found a problem: After screensaver kicked in and display was turned off
> the brightness keys stop working.
>
> Problem can be reproduced like that:
>
> 1. Boot laptop
> 2. Test brightness keys, they are working
> 3. open Terminal and issue "xset -displa
On 01/07/16 13:45, Arun Siluvery wrote:
On 01/07/2016 12:56, Chris Wilson wrote:
On Fri, Jul 01, 2016 at 11:43:02AM +0100, Arun Siluvery wrote:
Pooled EU is a bxt only feature and kernel changes are already
merged. This
feature is not yet exposed to userspace as the support was not yet
availab
On pe, 2016-07-01 at 14:49 +0100, Chris Wilson wrote:
> On Fri, Jul 01, 2016 at 04:40:06PM +0300, Imre Deak wrote:
> > The purpose for each MOCS entry isn't well defined atm. Defining these
> > is important to remove any uncertainty about the use of these entries
> > for example in terms of perform
== Series Details ==
Series: HuC Loading Patches (rev2)
URL : https://patchwork.freedesktop.org/series/9011/
State : warning
== Summary ==
Series 9011v2 HuC Loading Patches
http://patchwork.freedesktop.org/api/1.0/series/9011/revisions/2/mbox
Test drv_hangman:
Subgroup error-state-bas
On 01/07/16 12:22, Chris Wilson wrote:
By using the same address for storing the HWS on every platform, we can
remove the platform specific vfuncs and reduce the get-seqno routine to
a single read of a cached memory location.
v2: Fix semaphore_passed() to look at the signaling engine (not the
w
On Thu, Jun 30, 2016 at 10:58 PM, Sharma, Shashank
wrote:
> Thanks for the review Rodrigo. My comments inline.
>
> Regards
> Shashank
>
>
> On 7/1/2016 3:46 AM, Rodrigo Vivi wrote:
>>
>> On Tue, Jun 21, 2016 at 8:00 AM, Shashank Sharma
>> wrote:
>>>
>>> This patch adds lspcon support in dp_dual_m
On Fri, Jul 01, 2016 at 03:09:16PM +0100, Tvrtko Ursulin wrote:
> Looks OK if Gen5 is happy about it.
Happier than it has been for years. Still trying to beat some odd
coherency issues that upset igt (not introduced by these patches I
hasten to add), but we may just about get it working in time fo
On 01/07/16 12:22, Chris Wilson wrote:
On Ironlake, there is no command nor register to ensure that the write
from a MI_STORE command is completed (and coherent on the CPU) before the
command parser continues. This means that the ordering between the seqno
Command *streamer* I think. (More ins
The purpose for each MOCS entry isn't well defined atm. Defining these
is important to remove any uncertainty about the use of these entries
for example in terms of performance and GPU/CPU coherency.
Suggested by Ville.
v4:
- Rename I915_MOCS_AUTO to I915_MOCS_PTE. (Chris)
CC: Rong R Yang
CC: Y
On Fri, Jul 01, 2016 at 03:27:40PM +0100, Tvrtko Ursulin wrote:
>
> On 01/07/16 12:22, Chris Wilson wrote:
> >On Ironlake, there is no command nor register to ensure that the write
> >from a MI_STORE command is completed (and coherent on the CPU) before the
> >command parser continues. This means
On 01/07/16 12:22, Chris Wilson wrote:
With only a single callsite for intel_engine_cs->irq_get and ->irq_put,
we can reduce the code size by moving the common preamble into the
caller, and we can also eliminate the reference counting.
For completeness, as we are no longer doing reference count
Broxton is now part of CI which doesn't indicate any major problems so
enable the driver by default.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a7f8f4f..94
Reviewed-by: Rodrigo Vivi
On Fri, Jul 1, 2016 at 7:40 AM, Imre Deak wrote:
> Broxton is now part of CI which doesn't indicate any major problems so
> enable the driver by default.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> 1 file changed, 1 deletion(-)
>
> di
== Series Details ==
Series: drm/i915/bxt: Fix performance due to bogus MOCS entry
URL : https://patchwork.freedesktop.org/series/9377/
State : warning
== Summary ==
Series 9377v1 drm/i915/bxt: Fix performance due to bogus MOCS entry
http://patchwork.freedesktop.org/api/1.0/series/9377/revisio
On 01/07/16 12:22, Chris Wilson wrote:
Currently __i915_wait_request uses a per-engine wait_queue_t for the dual
purpose of waking after the GPU advances or for waking after an error.
In the future, we may add even more wake sources and require greater
separation, but for now we can conceptually
== Series Details ==
Series: drm/i915/bxt: Fix performance due to bogus MOCS entry (rev2)
URL : https://patchwork.freedesktop.org/series/9377/
State : warning
== Summary ==
Series 9377v2 drm/i915/bxt: Fix performance due to bogus MOCS entry
http://patchwork.freedesktop.org/api/1.0/series/9377/
On 01/07/16 12:22, Chris Wilson wrote:
We can forgo queuing the hangcheck from the start of every request to
until we wait upon a request. This reduces the overhead of every
request, but may increase the latency of detecting a hang. Howeever, if
nothing every waits upon a hang, did it ever hang?
== Series Details ==
Series: drm/i915/bxt: Remove the preliminary_hw_support flag
URL : https://patchwork.freedesktop.org/series/9381/
State : warning
== Summary ==
Series 9381v1 drm/i915/bxt: Remove the preliminary_hw_support flag
http://patchwork.freedesktop.org/api/1.0/series/9381/revisions
Thanks,
James
-Original Message-
From: Chris Wilson [mailto:chris.ickle.wil...@gmail.com] On Behalf Of Chris
Wilson
Sent: Friday, July 1, 2016 12:25 AM
To: Xiong, James
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: gracefully reject mmap of huge
tile
== Series Details ==
Series: drm/i915: Mass convert dev->dev_private to to_i915(dev)
URL : https://patchwork.freedesktop.org/series/9385/
State : success
== Summary ==
Series 9385v1 drm/i915: Mass convert dev->dev_private to to_i915(dev)
http://patchwork.freedesktop.org/api/1.0/series/9385/rev
Currently __i915_wait_request uses a per-engine wait_queue_t for the dual
purpose of waking after the GPU advances or for waking after an error.
In the future, we may add even more wake sources and require greater
separation, but for now we can conceptually simplify wakeups by separating
the two so
As we inspect obj->active to decide how many objects we can shrink (we
only shrink idle objects), it helps to flush the active lists first
in order to have a more accurate count of available objects.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_shrin
With the last direct CPU access to the scratch page removed, we can now
allocate it from our small amount of reserved system pages (stolen
memory).
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +++-
1 file changed, 3 insertions(+), 1 de
One particularly stressful scenario consists of many independent tasks
all competing for GPU time and waiting upon the results (e.g. realtime
transcoding of many, many streams). One bottleneck in particular is that
each client waits on its own results, but every client is woken up after
every batch
Since the function is a small wrapper around schedule_delayed_work(),
move it inline to remove the function call overhead for the principle
caller.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 18 +-
drivers/gpu/drm/i915/i915_irq.
The gen2 w/a buffer is stuffed into the same slot as the gen5+ scratch
buffer. If we pass in the size we want to allocate for the scratch
buffer, both callers can use the same routine.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c| 2 +-
d
On Ironlake, there is no command nor register to ensure that the write
from a MI_STORE command is completed (and coherent on the CPU) before the
command parser continues. This means that the ordering between the seqno
write and the subsequent user interrupt is undefined (like gen6+). So to
ensure t
We can forgo queuing the hangcheck from the start of every request to
until we wait upon a request. This reduces the overhead of every
request, but may increase the latency of detecting a hang. However, if
nothing every waits upon a hang, did it ever hang? It also improves the
robustness of the wai
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