On Mon, 06 Jun 2016, Lyude Paul wrote:
> On Mon, 2016-06-06 at 14:30 +0300, Ville Syrjälä wrote:
>> On Thu, May 26, 2016 at 09:54:56AM +0200, Daniel Vetter wrote:
>> >
>> > Queued for -next, thanks for the patch.
>> Looks like this one broke one of the ILKs in CI.
>>
>> [ 13.100979] [drm:ironl
When resetting and reloading the GuC, the GuC submission management code
also needs to destroy and recreate the GuC client(s). Currently this is
done by a separate call from the GuC loader, but really, it's just an
internal detail of the submission code. So here we remove the call from
the loader (
The last stage of the GuC loader also sanitises the GuC submission
settings, so should be called unconditionally (even on platforms
without a GuC) to ensure consistent settings; in particular, this
prevents any attempt to use GuC submission on GuCless platforms!
Also fix error path handling and cl
The recent patch
. fce91f2 drm/i915/guc: add enable_guc_loading parameter
enabled GuC loading and submission by default, but as issues
were found with warnings being issued during suspend-resume
cycles, GuC loading was disabled by default, by patch
. 2335986 drm/i915/guc: Disable automatic GuC firm
So that we can add an alternative implementation for the other arches.
This is basically what the kernel does.
Signed-off-by: Tomeu Vizoso
---
tests/kms_cursor_legacy.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/kms_cursor_legacy.c b/tests/kms_cursor_legacy.
On 07/06/16 09:14, Dave Gordon wrote:
The last stage of the GuC loader also sanitises the GuC submission
settings, so should be called unconditionally (even on platforms
without a GuC) to ensure consistent settings; in particular, this
prevents any attempt to use GuC submission on GuCless platfo
== Series Details ==
Series: series starting with [1/3] drm/i915/guc: fix GuC loading/submission
check
URL : https://patchwork.freedesktop.org/series/8380/
State : failure
== Summary ==
Series 8380v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/8380/revisions/1/
On Wed, 2016-06-01 at 11:31 +0100, Tvrtko Ursulin wrote:
> On 31/05/16 07:19, ankitprasad.r.sha...@intel.com wrote:
> > From: Ankitprasad Sharma
.
.
.
> > +
> > +void i915_gem_stolen_size_info(struct drm_i915_private *dev_priv,
> > + uint64_t *stolen_free,
> > +
On pe, 2016-06-03 at 15:37 +0100, Chris Wilson wrote:
> The kernel context exists simply as a placeholder and should never be
> executed with a render context. It does not need the golden render
> state, as that will always be applied to a user context. By skipping the
> initialisation we can avoid
On 07/06/16 09:14, Dave Gordon wrote:
When resetting and reloading the GuC, the GuC submission management code
also needs to destroy and recreate the GuC client(s). Currently this is
done by a separate call from the GuC loader, but really, it's just an
internal detail of the submission code. So
On 07/06/16 09:14, Dave Gordon wrote:
The recent patch
. fce91f2 drm/i915/guc: add enable_guc_loading parameter
enabled GuC loading and submission by default, but as issues
Not submission, just the loading.
were found with warnings being issued during suspend-resume
cycles, GuC loading was d
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 07/06/16 10:51, Tvrtko Ursulin wrote:
On 07/06/16 09:14, Dave Gordon wrote:
When resetting and reloading the GuC, the GuC submission management code
also needs to destroy and recreate the GuC client(s). Currently this is
done by a separate call from the GuC loader, but really, it's just an
i
Change return value to int to propagate errors from gamma_set,
and remove start parameter. Updates always use the full size,
and some drivers even ignore the start parameter altogether.
This is needed for atomic drivers, where an atomic commit can
fail with -EINTR or -ENOMEM and should be restarte
On 07/06/16 09:43, Patchwork wrote:
== Series Details ==
Series: series starting with [1/3] drm/i915/guc: fix GuC loading/submission
check
URL : https://patchwork.freedesktop.org/series/8380/
State : failure
== Summary ==
Series 8380v1 Series without cover letter
http://patchwork.freedeskto
On Tue, Jun 7, 2016 at 12:49 PM, Maarten Lankhorst
wrote:
> Change return value to int to propagate errors from gamma_set,
> and remove start parameter. Updates always use the full size,
> and some drivers even ignore the start parameter altogether.
>
> This is needed for atomic drivers, where an
Op 01-06-16 om 19:07 schreef john.c.harri...@intel.com:
> From: John Harrison
>
> The purpose of this patch series is to convert the requst structure to
> use fence objects for the underlying completion tracking. The fence
> object requires a sequence number. The ultimate aim is to use the same
>
On pe, 2016-06-03 at 17:36 +0100, Chris Wilson wrote:
> The retire worker is a low frequency task that makes sure we retire
> outstanding requests if userspace is being lax. We only need to start it
> once as it remains active until the GPU is idle, so do a cheap test
> before the more expensive qu
On pe, 2016-06-03 at 17:36 +0100, Chris Wilson wrote:
> Rather than persistently postponing the idle-work everytime somebody
> calls i915_gem_retire_requests() (potentially ensuring that we never
> reach the idle state), queue the work the first time we detect all
> requests are complete. Then if i
On pe, 2016-06-03 at 17:36 +0100, Chris Wilson wrote:
> We know, by design, that whilst the GPU is active (and thus we are
> throttling) the retire_worker is queued. Therefore attempting to requeue
> it with queue_delayed_work() is a no-op and we can safely remove it.
>
> Signed-off-by: Chris Wils
Op 02-06-16 om 13:07 schreef Tvrtko Ursulin:
>
> On 01/06/16 18:07, john.c.harri...@intel.com wrote:
>> From: John Harrison
>>
>> There is a construct in the linux kernel called 'struct fence' that is
>> intended to keep track of work that is executed on hardware. I.e. it
>> solves the basic probl
All outputs have a 1:1 relationship between connectors and encoders
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/sti/sti_d
All outputs have a 1:1 relationship between connectors and encoders
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/sun4i/sun
All outputs have a 1:1 relationship between connectors and encoders and
the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/vc4/vc4_d
For all outputs except dp_mst, we have a 1:1 relationship between
connectors and encoders and the driver is relying on the atomic helpers:
we can drop the custom ->best_encoder() implementation and let the core
call drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
driv
We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder() and let the core call drm_atomic_helper_best_encoder()
for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c |
All outputs have a 1:1 relationship between connectors and encoders
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
Acked-by: Mark Yao
---
driv
Adapt drm_pick_crtcs() and update_connector_routing() to fallback to
drm_atomic_helper_best_encoder() if funcs->best_encoder() is NULL so
that DRM drivers can leave this hook unassigned if they know they want
to use drm_atomic_helper_best_encoder().
Update the vtables documentation accordingly.
S
We have a 1:1 relationship between connectors and encoders, and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder(),
and let the core call drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/bridge/nxp-ptn3460.c | 8 ---
All outputs have a 1:1 relationship between connectors and encoders,
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
Reviewed-by: Laurent Pinchart
We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder() and let the core call drm_atomic_helper_best_encoder()
for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 9
For all outputs except DSI we have a 1:1 relationship between connectors
and encoders and the driver is relying on the atomic helpers: we can
drop the custom ->best_encoder() and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/msm/edp
We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementation and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
Reviewed-by: Laurent Pinchart
---
driv
The virtgpu output exposes a 1:1 relationship between connectors and
encoders and the driver is relying on the atomic helpers: we can drop
the custom ->best_encoder() implementation and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/
We have 1:1 relationship between connectors and encoders and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder()
implementations and let the core call drm_atomic_helper_best_encoder()
for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/exynos/exynos_drm_dp
Hello,
This patch series aims at replacing all dummy ->best_encoder()
implementations where we have a 1:1 relationship between encoders
and connectors.
The core already provides the drm_atomic_helper_best_encoder()
function which is taking the first encoder attached to the
connector (after making
All outputs have a 1:1 relationship between connectors and encoders
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementation and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/tegra/drm.
We have a 1:1 relationship between connectors and encoders, and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder(),
and let the core call drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/bridge/parade-ps8622.c | 10
We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder(), and let the core call drm_atomic_helper_best_encoder()
for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/arc/arcpgu_hdmi.c | 18 --
We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementation and let the core call
drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/mediatek/mtk_dsi.c
We have a 1:1 relationship between connectors and encoders, which means
we can rely on the drm_atomic_helper_best_encoder() behavior.
We still have to explicitly assign ->best_encoder() to
drm_atomic_helper_best_encoder(), because the automated fallback to
drm_atomic_helper_best_encoder() when ->b
We have a 1:1 relationship between connectors and encoders, and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder(),
and let the core call drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/bridge/analogix-anx78xx.c | 8 --
Op 02-06-16 om 15:25 schreef Tvrtko Ursulin:
>
> On 01/06/16 18:07, john.c.harri...@intel.com wrote:
>> From: John Harrison
>>
>> The intended usage model for struct fence is that the signalled status
>> should be set on demand rather than polled. That is, there should not
>> be a need for a 'sign
== Series Details ==
Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
URL : https://patchwork.freedesktop.org/series/8164/
State : success
== Summary ==
Series 8164v2 drm/atomic: Provide default ->best_encoder() behavior
http://patchwork.freedesktop.org/api/1.0/series/8164/
On 03/06/16 17:08, Chris Wilson wrote:
If we convert the tracing over from direct use of ring->irq_get() and
over to the breadcrumb infrastructure, we only have a single user of the
ring->irq_get and so we will be able to simplify the driver routines
(eliminating the redundant validation and irq
Op 01-06-16 om 19:07 schreef john.c.harri...@intel.com:
> From: John Harrison
>
> The change to the implementation of i915_gem_request_completed() means
> that the lazy coherency flag is no longer used. This can now be
> removed to simplify the interface.
>
> v6: Updated to newer nightly and resol
On 06/06/2016 18:30, Tvrtko Ursulin wrote:
On 03/06/16 17:08, Chris Wilson wrote:
Currently __i915_wait_request uses a per-engine wait_queue_t for the dual
purpose of waking after the GPU advances or for waking after an error.
In the future, we may add even more wake sources and require greater
On 07/06/16 12:42, Maarten Lankhorst wrote:
Op 02-06-16 om 13:07 schreef Tvrtko Ursulin:
[snip]
+static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
+ bool lazy_coherency)
+{
+return fence_is_signaled(&req->fence);
+}
I would squash
Op 01-06-16 om 19:07 schreef john.c.harri...@intel.com:
> From: John Harrison
>
> Added the '_complete' trace event which occurs when a fence/request is
> signaled as complete. Also moved the notify event from the IRQ handler
> code to inside the notify function itself.
>
> v3: Added the current r
On 07/06/16 13:02, Maarten Lankhorst wrote:
Op 02-06-16 om 15:25 schreef Tvrtko Ursulin:
[snip]
+return;
+
+if (!fence_locked)
+spin_lock_irqsave(&engine->fence_lock, flags);
Not called from hard irq context so can be just spin_lock_irq.
But if you agree to go with the
On 03/06/16 17:08, Chris Wilson wrote:
Under the assumption that enabling signaling will be a frequent
operation, lets preallocate our attachments for signaling inside the
request struct (and so benefiting from the slab cache).
Oh you did this part which I suggested in the previous patch. :)
Op 01-06-16 om 19:07 schreef john.c.harri...@intel.com:
> From: John Harrison
>
> The notify function can be called many times without the seqno
> changing. Some are to prevent races due to the requirement of not
> enabling interrupts until requested. However, when interrupts are
> enabled the IRQ
On 03/06/16 17:08, Chris Wilson wrote:
With only a single callsite for intel_engine_cs->irq_get and ->irq_put,
we can reduce the code size by moving the common preamble into the
caller, and we can also eliminate the reference counting.
For completeness, as we are no longer doing reference count
On 03/06/16 17:08, Chris Wilson wrote:
Borrow the idea from intel_lrc.c to precompute the mask of interrupts we
wish to always enable to avoid having lots of conditionals inside the
interrupt enabling.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 +++--
On 03/06/16 17:08, Chris Wilson wrote:
Since the tests can and do explicitly check debugfs/i915_ring_missed_irqs
for the handling of a "missed interrupt", adding it to the dmesg at INFO
is just noise. When it happens for real, we still class it as an ERROR.
Signed-off-by: Chris Wilson
---
dr
== Series Details ==
Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
URL : https://patchwork.freedesktop.org/series/8164/
State : success
== Summary ==
Series 8164v2 drm/atomic: Provide default ->best_encoder() behavior
http://patchwork.freedesktop.org/api/1.0/series/8164/
Op 07-06-16 om 14:03 schreef Patchwork:
> == Series Details ==
>
> Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
> URL : https://patchwork.freedesktop.org/series/8164/
> State : success
>
> == Summary ==
>
> Series 8164v2 drm/atomic: Provide default ->best_encoder() behavio
On 07/06/16 11:54, Dave Gordon wrote:
On 07/06/16 09:43, Patchwork wrote:
== Series Details ==
Series: series starting with [1/3] drm/i915/guc: fix GuC
loading/submission check
URL : https://patchwork.freedesktop.org/series/8380/
State : failure
== Summary ==
Series 8380v1 Series without c
== Series Details ==
Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
URL : https://patchwork.freedesktop.org/series/8164/
State : failure
== Summary ==
Series 8164v2 drm/atomic: Provide default ->best_encoder() behavior
http://patchwork.freedesktop.org/api/1.0/series/8164/
Kabylake is part of gen9 family so init the generic gen9
workarounds for it.
v2: rebase
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++---
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/dri
The revision id range for this workaround has changed. So apply
it to all revids on all gen9.
References: HSD#2134449
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git
We need this crucial workaround from skl also to all kbl revisions.
Lack of it was causing system hangs on skl enabling so this is
a must have.
v2: Don't add revid checks to gen9 init workarounds (Arun)
References: HSD#2126660
Cc: Arun Siluvery
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew
Workaround for display underrun issues with Y & Yf Tiling.
Set this on all gen9 as stated by bspec.
v2: proper workaround name
References: HSD#2136383, BSID#857
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c |
Extend the scope of this workaround, already used in skl,
to also take effect in kbl.
v2: Fix KBL_REVID_E0 (Matthew)
References: HSD#2132677
Cc: Matthew Auld
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel
This is needed for all kbl revision.
v2: Don't add revid checks to generic gen9 init (Arun)
References: HSD#2135593
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i
According to bspec this workaround helps to reduce lag and improve
performance on edp.
Documentation suggests this for bdw and all gen9. However evidence
shows that this register is missing on gen9 and causing unclaimed mmio
access if we access it. So apply to bdw only where the reg
exists and can
This workaround is for fbc working with rc6 on skylake. Bspec
states that setting this bit needs to be coordinated with uncore
but offers no further details.
v2: rebase
References: HSD#4712857
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
d
Bspec states that we need to set nuke on modify all to prevent
screen corruption with fbc on skl and kbl.
v2: proper workaround name
References: HSD#2227109, HSDES#1404569388
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
d
Add this workaround for kbl revid A0 only.
v2: rebase
v3: carve out a non related workaround (Chris)
References: HSD#1911714
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --g
Add REVID macro for kbl to limit wa applicability to particular
revision range.
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
This workaround for bdw and chv, is also needed for kbl A0.
References: HSD#1911519, BSID#569
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_lrc.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/driv
Past evidence with system hangs and hsds tie
WaForceEnableNonCoherent and WaDisableHDCInvalidation to
WaForceContextSaveRestoreNonCoherent. Documentation
states that WaForceContextSaveRestoreNonCoherent would
not be needed on skl past E0 but evidence proved otherwise. See
commit <510650e8b2ab> ("dr
Add this workaround for A0 and B0 revisions
References: HSD#2226935
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_lrc.c | 36 ++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lr
Add this workaround until upto kbl revid B0.
References: HSD#1802092
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_pm.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/d
We need to disable clock gating in this unit to work around
hardware issue causing possible corruption/hang.
v2: name the bit (Ville)
v3: leave the fix enabled for 2227050 and set correct bit (Matthew)
References: HSD#2227156, HSD#2227050
Cc: Ville Syrjälä
Cc: Matthew Auld
Reviewed-by: Matthew
The bspec states that these must be set in CONFIG0 for all gen9.
v2: rebase
v3: fix spacing (Matthew)
References: HSD#2134995
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 24 ++--
2 fi
On 06/07/2016 04:07 PM, Maarten Lankhorst wrote:
Op 07-06-16 om 14:03 schreef Patchwork:
== Series Details ==
Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
URL : https://patchwork.freedesktop.org/series/8164/
State : success
...
ro-snb-i7-2620M failed to connect after r
According to bspec we need to disable gam unit clock gating on
on kbl revids A0 and B0.
References: HSD#2226858, HSD#1944358
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed, 6 insertions
Hi,
Reordered and rebased series. I singled out major skl one to
the start of series for easier backporting.
Only 27/27 is missing r-b tag.
Thank you for Matthew and Ville for reviews.
-Mika
Mika Kuoppala (27):
drm/i915/skl: Add WaDisableGafsUnitClkGating
drm/i915/kbl: Init gen9 workaround
For now If we want to achieve that, we have to add a member in struct
i915_gem_request like your code. :(
/* Assume in all host GEM request, req->vgpu == NULL*/
If (req0->vgpu = req1->vgpu)
combine!
> -Original Message-
> From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.
Add this fbc related workaround for all gen9
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
Bspec states that we need to turn off dynamic credit
sharing on kbl revid a0 and b0. This happens by writing bit 28
on 0x4ab8.
References: HSD#2225601, HSD#2226938, HSD#2225763
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gp
Set bit 8 in 0x43224 to prevent screen corruption and system
hangs on high memory bandwidth conditions. The same wa also suggest
setting bit 31 on ARB_CTL. According to another workaround we gain
better idle power savings when FBC is enabled.
v2: use correct workaround name
v3: split out overlappi
We need to disable clock gating in this unit to work around
hardware issue causing possible corruption/hang.
v2: name the bit (Ville)
v3: leave the fix enabled for 2227050 and set correct bit (Matthew)
v4: Split out the skl part in separate commit for easier backport
References: HSD#2227156, HSD#
Add this workaround for both bxt and kbl up to until
rev B0.
References: HSD#2136703
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++
2 files changed, 11 insertions(+)
diff --git
According to bspec this prevents screen corruption when fbc is
used.
v2: This workaround has a name, use it (Ville)
v3: remove bogus gen check on ilk/vlv wm path (Ville)
References: HSD#213, HSD#2137270, BSID#562
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
Reviewed-by:
We need this for kbl a0 boards. Note that this should be also
for bxt A0 but we omit that on purpose as bxt A0's are
out of fashion already.
References: HSD#1912158, HSD#4393097
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 6 --
1 file
Make sure that we never enable skip caching on gen9 by
accident.
References: HSD#2134698
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_mocs.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/
There is ambiguity in the documentation between D0 and E0.
Extend this workaround to E0.
References: BSID#779
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i9
On Tue, Jun 07, 2016 at 01:47:56PM +0200, Boris Brezillon wrote:
> Adapt drm_pick_crtcs() and update_connector_routing() to fallback to
> drm_atomic_helper_best_encoder() if funcs->best_encoder() is NULL so
> that DRM drivers can leave this hook unassigned if they know they want
> to use drm_atomic
== Series Details ==
Series: gen9 workarounds v3
URL : https://patchwork.freedesktop.org/series/8405/
State : success
== Summary ==
Series 8405v1 gen9 workarounds v3
http://patchwork.freedesktop.org/api/1.0/series/8405/revisions/1/mbox
fi-bdw-i7-5557u total:102 pass:93 dwarn:0 dfail:0
This patchset introduces the implementation of GVT context. GVT
context is a special GEM context used by GVT-g. GVT-g uses it as the shadow
context.It doesn't have a drm client nor a PPGTT. And it requires a larger
ring buffer with several special features need by GVT-g workload scheduler
like cont
To get the offset of the members in PVINFO page, offsetof() looks much
better than the tricky approach in current code.
v7:
- Move "offsetof()" modification into a dedicated patch. (Joonas)
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
1 file changed, 1 insertion(+), 1
This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.
v7:
- Refine the URL link in Kconfig. (Joonas)
- Refine the introduction of GVT-g host support in Kconfig. (Joonas)
- Remove the macro GVT_ALIGN(), use round_down() instead
This function needs to be changed to have a proper goto teardown path.
Destructors/fini functions are only expected to be called after a
successful initialization, so calling it at random phase in init function
is bad. (Joonas)
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_vgpu.c | 7 +++
Currently the addressing mode bit in context descriptor is statically
generated from the configuration of system-wide PPGTT usage model.
GVT-g will load the PPGTT shadow page table by itself and probably one
guest is using a different addressing mode with i915 host. The addressing
mode bits of a L
GVT workload scheduler needs special host LRC contexts, the so called
"shadow LRC context" to submit guest workload to host i915. During the
guest workload submission, workload scheduler fills the shadow LRC
context with the content of guest LRC context: engine context is copied
without changes, ri
v5:
- Let functions take struct drm_i915_private *. (Tvrtko)
- Fold vGPU related active check into the inner functions. (Kevin)
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ---
drivers/gpu/drm/i915/i915_vgpu.c| 13 +
drivers/gpu/drm/i915/i915_vgp
From: Bing Niu
This patch introduces host graphics memory partition when GVT-g
is enabled.
Under GVT-g, i915 host driver only owned limited graphics resources,
others are managed by GVT-g resource allocator and kept for other vGPUs.
v7:
- Add comments about low/high GM size for host. (Joonas)
This patch introduces an option for configuring the ring buffer size
of a LRC context after the context creation.
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/intel_lrc.c| 3 ++-
3 files cha
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