On Fri, May 27, 2016 at 08:47:48AM +0200, Daniel Vetter wrote:
> On Thu, May 26, 2016 at 02:06:13PM +0100, Chris Wilson wrote:
> > On Thu, May 26, 2016 at 01:35:18PM +0100, Chris Wilson wrote:
> > > In order to give the driver the chance to initialise the data structures
> > > that will be exposed
On 26/05/2016 20:59, Mika Kuoppala wrote:
We need this crucial workaround from skl also to all kbl revisions.
Lack of it was causing system hangs on skl enabling so this is
a must have.
References: HSD#2126660
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +
On 25 May 2016 at 08:31, Sedat Dilek wrote:
> Hi Daniel,
>
> with latest Linus Git I see this with my Intel SandyBridge GPU...
>
> [ 17.629014] [drm:intel_cpu_fifo_underrun_irq_handler [i915]]
> *ERROR* CPU pipe A FIFO underrun
> [ 17.630652] [drm:intel_set_pch_fifo_underrun_reporting [i915]]
Mika Kuoppala writes:
> [ text/plain ]
> According to bspec this workaround helps to reduce lag and improve
> performance on edp.
>
Bspec says this is for bdw,skl.
wa database says this is for bdw and all gen9.
If we write to 0x42090 on kbl,skl it doesn't
hold value and we get the mmio debug tr
On Tue, May 03, 2016 at 06:39:57PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Minimize the resulting X coordinate after intel_adjust_tile_offset() is
> done with it's offset adjustment. This allows calling
> intel_adjust_tile_offset() multiple times in case we need to a
From: Ville Syrjälä
Several nasty i915 regressions affecting CHV slipped through
to 4.5 and 4.6.
The first fix we want in 4.5 and 4.6 is
commit caed361d83b2 ("drm/i915: Fix watermarks for VLV/CHV")
It won't cherry-pick cleanly to either one, so I've included conflict
free versions for both. This
From: Ville Syrjälä
commit caed361d83b2 upstream
commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the
crtc_state, v4.")
broke thigns by removing the pre vs. post wm update distinction. We also
lost the pre plane wm update entirely for VLV/CHV from the crtc enable
path.
Th
From: Ville Syrjälä
commit caed361d83b2 upstream
commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the
crtc_state, v4.")
broke thigns by removing the pre vs. post wm update distinction. We also
lost the pre plane wm update entirely for VLV/CHV from the crtc enable
path.
Th
== Series Details ==
Series: drm/i915: Fix watermarks for VLV/CHV
URL : https://patchwork.freedesktop.org/series/7867/
State : failure
== Summary ==
Applying: drm/i915: Fix watermarks for VLV/CHV
Patch failed at 0001 drm/i915: Fix watermarks for VLV/CHV
The copy of the patch that failed is fou
On ti, 2016-05-24 at 16:18 +0300, Imre Deak wrote:
> On ti, 2016-05-24 at 13:02 +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [v2,1/2] drm/i915/gen9: Assume CDCLK PLL
> > is off if it's not locked
> > URL : https://patchwork.freedesktop.org/series/7631/
>
While the details of getting a shared dpll are wrapped by
intel_get_shared_dpll(), the release was still hand rolled into the
modeset code. Fix that by creating an entry point for releasing the
pll and move that code there.
v2: Take old_dpll from crtc->state instead of crtc_state. (CI)
Signed-off-
The hook is called from intel_prepare_shared_dpll(). The name doesn't
make sense after all the changes to modeset code. So just call it
prepare.
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Durgadoss R
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 8
drivers/gpu/drm/i915/inte
The function intel_shared_dpll_commit() performs the equivalent of
drm_atomic_helper_swap_state() for the shared dpll state, which is not
handled by the helpers. So rename it for consistency.
v2: Fix typo in the commit message. (Durga)
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Durg
The documentation for most of the non-static members and structs were
missing. Fix that.
v2: Fix typos (Durga)
Cc: Daniel Vetter
Signed-off-by: Ander Conselvan de Oliveira
Reviewed-by: Durgadoss R
---
Documentation/DocBook/gpu.tmpl| 7 +++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 90 +
Pushed.
On Thu, May 26, 2016 at 04:02:05PM -0700, Matt Roper wrote:
> Some validation teams seem to run tests out of source directories that
> have been nfs mounted or rsync'd to different locations on the target
> machine. This causes the igt_srcdir that the tests were built with to
> be invalid
== Series Details ==
Series: series starting with [1/4] drm/i915: Introduce
intel_release_shared_dpll()
URL : https://patchwork.freedesktop.org/series/7872/
State : failure
== Summary ==
Series 7872v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/7872/revisions/1
For me I think maybe i915 could save the snapshot for GVT, then GVT-g patch the
snapshot itself, then there won't be leaking happened I think. Even we wrote a
dedicated little program, we would do the same thing.
From: Wang, Zhi A
Sent: Friday, May 27, 2016 12:59 PM
To: joonas.lahti...@linux.int
Curious why leaking BIOS configuration to VM is a security problem... Can
someone elaborate this view?
From: Wang, Zhi A
Sent: Friday, May 27, 2016 6:05 PM
To: intel-gfx@lists.freedesktop.org
Cc: joonas.lahti...@linux.intel.com; Chris Wilson; Vetter, Daniel;
tvrtko.ursu...@linux.intel.com; Tian,
On Fri, May 20, 2016 at 08:53:12PM +0100, Chris Wilson wrote:
> On Fri, May 20, 2016 at 08:02:46PM +0300, Marius Vlad wrote:
> > Tune down from 20s to 2s. Add the old timeout values under extended tests.
>
> Does it fail with the new timeout? If not, increase it.
>
> This test should be a fail on
On pe, 2016-05-27 at 10:05 +, Wang, Zhi A wrote:
> For me I think maybe i915 could save the snapshot for GVT, then GVT-g
> patch the snapshot itself, then there won’t be leaking happened I
> think. Even we wrote a dedicated little program, we would do the same
> thing.
>
> From: Wang, Zhi A
On pe, 2016-05-27 at 10:09 +, Tian, Kevin wrote:
> Curious why leaking BIOS configuration to VM is a security problem…
> Can someone elaborate this view?
>
Hi,
It is a potential vector in case we are blindly reading everything but
blacklisted registers. Whitelisting would make it less so.
On Tue, May 03, 2016 at 04:25:20PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be
> more generic (v4)
> URL : https://patchwork.freedesktop.org/series/6688/
> State : failure
>
> == Summary ==
>
> Series 6688v1
Signed-off-by: Marius Vlad
---
tests/gem_exec_flush.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_exec_flush.c b/tests/gem_exec_flush.c
index d08b843..b608060 100644
--- a/tests/gem_exec_flush.c
+++ b/tests/gem_exec_flush.c
@@ -523,7 +523,7 @@ igt_main
Signed-off-by: Marius Vlad
---
tests/gem_exec_nop.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_exec_nop.c b/tests/gem_exec_nop.c
index e90d5eb..1b2d144 100644
--- a/tests/gem_exec_nop.c
+++ b/tests/gem_exec_nop.c
@@ -213,7 +213,7 @@ igt_main
igt_fork_han
Signed-off-by: Marius Vlad
---
tests/gem_exec_suspend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_exec_suspend.c b/tests/gem_exec_suspend.c
index cd133cc..3d529bd 100644
--- a/tests/gem_exec_suspend.c
+++ b/tests/gem_exec_suspend.c
@@ -247,7 +247,7 @@ igt_main
Signed-off-by: Marius Vlad
---
tests/gem_sync.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/gem_sync.c b/tests/gem_sync.c
index 320bce3..f824d1e 100644
--- a/tests/gem_sync.c
+++ b/tests/gem_sync.c
@@ -126,7 +126,7 @@ sync_ring(int fd, unsigned ring, int num_chil
Add a extended subtest and reduce the number of iteration to qualify
for BAT. Renamed to test to gem_tiled_pread.
Signed-off-by: Marius Vlad
---
tests/Makefile.sources| 2 +-
tests/gem_tiled_pread.c | 231 ++
tests/gem_tiled_pread_basic.c |
Signed-off-by: Marius Vlad
---
tests/gem_storedw_loop.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_storedw_loop.c b/tests/gem_storedw_loop.c
index 317b8c6..89f0182 100644
--- a/tests/gem_storedw_loop.c
+++ b/tests/gem_storedw_loop.c
@@ -187,7 +187,7 @@ igt_main
Signed-off-by: Marius Vlad
---
tests/gem_ctx_switch.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
index 7b27336..066a5fc 100644
--- a/tests/gem_ctx_switch.c
+++ b/tests/gem_ctx_switch.c
@@ -73,6 +73,7 @@ static void single(
Signed-off-by: Marius Vlad
---
tests/gem_close_race.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_close_race.c b/tests/gem_close_race.c
index 94fb905..45aa2cc 100644
--- a/tests/gem_close_race.c
+++ b/tests/gem_close_race.c
@@ -232,7 +232,7 @@ igt_main
}
On Fri, May 27, 2016 at 02:43:32PM +0300, Ville Syrjälä wrote:
> On Tue, May 03, 2016 at 04:25:20PM -, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to
> > be more generic (v4)
> > URL : https://patchwork.freedeskto
On Wed, May 25, 2016 at 05:22:21AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Reject modeset if the dotclock is too high
> URL : https://patchwork.freedesktop.org/series/7653/
> State : warning
>
> == Summary ==
>
> Series 7653v1 drm/i915: Reject modeset if the dotclo
On Wed, May 25, 2016 at 11:15:35AM +0300, Jani Nikula wrote:
> On Tue, 24 May 2016, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Reject the modeset if the requested dotclock exceeds the maximum allowed
> > by the hardware. So far we've only checked this on gen2/3 while also
On Fri, May 27, 2016 at 02:50:31PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
Nak. Please suggest how to make this test reliable first. At the moment,
we need to increase the time.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
__
On Fri, May 27, 2016 at 02:50:35PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
NAK. gem_sync is not reliable enough, please suggest how to improve
detection rates for *existing* issues.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
__
On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
Nak. It's a race detector. Please suggest how to increase detection
rates.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
On Fri, May 27, 2016 at 02:50:38PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
Nak. Please suggest how to fix the broken machines first.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
Intel-gfx@lists.
On Fri, May 27, 2016 at 02:50:32PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
Nak. Please suggest how to improve reliablity first.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
Intel-gfx@lists.freed
On Fri, May 27, 2016 at 02:50:36PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
Summary and patch do not match.
But you could remove gem_storedw_loop as everything BAT about it is
tested elsewhere.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
__
On Fri, May 27, 2016 at 02:50:37PM +0300, Marius Vlad wrote:
> Add a extended subtest and reduce the number of iteration to qualify
> for BAT. Renamed to test to gem_tiled_pread.
No. This doesn't increase coverage.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_
On Fri, May 27, 2016 at 02:50:33PM +0300, Marius Vlad wrote:
You need some explanation here to explain how you believe that all the
corner-cases from this minimal stress test are covered elsewhere.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
__
On 27/05/16 12:58, Chris Wilson wrote:
On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote:
Signed-off-by: Marius Vlad
Nak. It's a race detector. Please suggest how to increase detection
rates.
As a more or less well know TV personality would say - "it's better than
nothing"! :))
On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote:
>
> On 27/05/16 12:58, Chris Wilson wrote:
> >On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote:
> >>Signed-off-by: Marius Vlad
> >
> >Nak. It's a race detector. Please suggest how to increase detection
> >rates.
>
> As a
On 27/05/16 13:16, Chris Wilson wrote:
On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote:
On 27/05/16 12:58, Chris Wilson wrote:
On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote:
Signed-off-by: Marius Vlad
Nak. It's a race detector. Please suggest how to increase d
On Wed, May 25, 2016 at 11:15:35AM +0300, Jani Nikula wrote:
> On Tue, 24 May 2016, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Reject the modeset if the requested dotclock exceeds the maximum allowed
> > by the hardware. So far we've only checked this on gen2/3 while also
On Fri, May 27, 2016 at 01:31:10PM +0100, Tvrtko Ursulin wrote:
>
> On 27/05/16 13:16, Chris Wilson wrote:
> >On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote:
> >>
> >>On 27/05/16 12:58, Chris Wilson wrote:
> >>>On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote:
> Sign
On Fri, May 13, 2016 at 11:13:19PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Refresh cached DP port register value on resume
> URL : https://patchwork.freedesktop.org/series/7163/
> State : failure
>
> == Summary ==
>
> Series 7163v1 drm/i915: Refresh cached DP port
Tvrtko Ursulin writes:
> [ text/plain ]
>
> On 27/05/16 13:16, Chris Wilson wrote:
>> On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote:
>>>
>>> On 27/05/16 12:58, Chris Wilson wrote:
On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote:
> Signed-off-by: Marius Vlad
What started out as a simple patch turned into a midlayer minefield,
thanks Daniel. The result though should be something much, much safer
for asynchronous loading - please review kindly!
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
If a driver wants to more precisely control its initialisation and in
particular, defer registering its interfaces with userspace until after
everything is setup, it also needs to defer registering the connectors.
As some devices need more work during registration, add a callback so
that drivers ca
Setting up fbdev requires everything ready and registered (in particular
the connectors). In the next patch, we defer registration of the KMS
objects and unless we defer setting off fbdev, it may run before they are
registered and oops.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_d
To complete the transition to manual control of load/unload, we need to
take over unloading from i915_pci_remove(). This allows us to correctly
order our unregister vs shutdown phases, which currently are inverted
due to the midlayer.
However, the unload sequence is still invalid as we shutdown th
Baby step, update to_i915() conversion from drm_device to
drm_i915_private:
textdata bss dec hex filename
1108812 23207 416 1132435 114793 i915.ko (before)
1104999 23207 416 1128622 1138ae i915.ko (after)
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas
The module init/exit routines are a wrapper around the PCI device
init/exit, so move them across.
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.c | 51 +++--
drivers/gpu/drm/i915/i915_pci.c | 45 ++
To reclaim a bit of space from i915_drv.c, we can move the routines that
just hook us into the PCI device tree into i915_pci.c
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 450 +-
Currently debugfs files are created before the driver is even loads.
This gives the opportunity for userspace to open that interface and poke
around before the backing data structures are initialised - with the
possibility of oopsing or worse.
Move the creation of the debugfs files to our registra
Don't try and present the connectors to userspace (via sysfs and other
devices) before the driver is ready.
Correspondingly, be sure to make the userspace interfaces disappear
first.
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_dma.c | 2
Take control over allocating, loading and registering the driver from the
DRM midlayer by performing it manually from i915_pci_probe. This allows
us to carefully control the order of when we setup the hardware vs when
it becomes visible to third parties (including userspace). The current
ordering m
In order to allow drivers to pack their privates and drm_device into one
struct (e.g. for subclassing), export the initialisation routines for
struct drm_device.
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_drv.c | 63
On 27/05/16 15:00, Chris Wilson wrote:
Baby step, update to_i915() conversion from drm_device to
drm_i915_private:
text data bss dec hex filename
1108812 23207 416 1132435 114793 i915.ko (before)
1104999 23207 416 1128622 1138ae i915.ko (after)
This pat
On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote:
>
> On 27/05/16 12:58, Chris Wilson wrote:
> >On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote:
> >>Signed-off-by: Marius Vlad
> >
> >Nak. It's a race detector. Please suggest how to increase detection
> >rates.
>
> As a
On Fri, May 27, 2016 at 01:16:06PM +0100, Chris Wilson wrote:
> On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote:
> >
> > On 27/05/16 12:58, Chris Wilson wrote:
> > >On Fri, May 27, 2016 at 02:50:34PM +0300, Marius Vlad wrote:
> > >>Signed-off-by: Marius Vlad
> > >
> > >Nak. It's a
On Fri, May 27, 2016 at 03:44:20PM +0300, Mika Kuoppala wrote:
> Tvrtko Ursulin writes:
>
> > [ text/plain ]
> >
> > On 27/05/16 13:16, Chris Wilson wrote:
> >> On Fri, May 27, 2016 at 01:10:07PM +0100, Tvrtko Ursulin wrote:
> >>>
> >>> On 27/05/16 12:58, Chris Wilson wrote:
> On Fri, May 27
Kabylake is part of gen9 family so init the generic gen9
workarounds for it.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++---
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b
We need this for kbl a0 boards. Note that this should be also
for bxt A0 but we omit that on purpose as bxt A0's are
out of fashion already.
References: HSD#1912158, HSD#4393097
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 6 --
1 file changed, 4 insertions(+), 2
Add REVID macro for kbl to limit wa applicability to particular
revision range.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e4c8e341655c..98cb1f1
The revision id range for this workaround has changed. So apply
it to all revids on all gen9.
References: HSD#2134449
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/inte
Add this workaround until upto kbl revid B0.
References: HSD#1802092
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b6
WaKVMNotificationOnConfigChange was not for skl/bxt even tho
the documentation claims so.
Addressed Arun's comment about littering the generic gen
workaround function with revid checks.
Fbc ones have a names also as Ville pointed out.
Added one patch to extend one skl workaround.
-Mika
Mika Ku
Make sure that we never enable skip caching on gen9 by
accident.
References: HSD#2134698
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_mocs.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index
According to bspec we need to disable gam unit clock gating on
on kbl revids A0 and B0.
References: HSD#2226858, HSD#1944358
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/drivers/g
Set bit 8 in 0x43224 to prevent screen corruption and system
hangs on high memory bandwidth conditions. The same wa also suggest
setting bit 31 on ARB_CTL. According to another workaround we gain
better idle power savings when FBC is enabled.
v2: use correct workaround name
References: HSD#213721
There is ambiguity in the documentation between D0 and E0.
Extend this workaround to E0.
References: BSID#779
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/dr
Bspec states that we need to turn off dynamic credit
sharing on kbl revid a0 and b0. This happens by writing bit 28
on 0x4ab8.
References: HSD#2225601, HSD#2226938, HSD#2225763
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.
This workaround is for fbc working with rc6 on skylake. Bspec
states that setting this bit needs to be coordinated with uncore
but offers no further details.
v2: rebase
References: HSD#4712857
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_p
According to bspec this prevents screen corruption when fbc is
used.
v2: This workaround has a name, use it (Ville)
References: HSD#213, HSD#2137270, BSID#562
Cc: Paulo Zanoni
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 6 +-
1 file changed, 5 insertions(+), 1 de
This is needed for all kbl revision.
v2: Don't add revid checks to generic gen9 init (Arun)
References: HSD#2135593
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/driver
Add this workaround for both bxt and kbl up to until
rev B0.
References: HSD#2136703
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915
Bspec states that we need to set nuke on modify all to prevent
screen corruption with fbc on skl and kbl.
v2: proper workaround name
References: HSD#2227109, HSDES#1404569388
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 8
2
According to bspec this workaround helps to reduce lag and improve
performance on edp.
Documentation suggests this for bdw and all gen9. However evidence
shows that this register is missing on gen9 and causing unclaimed mmio
access if we access it. So apply to bdw only where the reg
exists and can
The bspec states that these must be set in CONFIG0 for all gen9.
v2: rebase
References: HSD#2134995
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 24 ++--
2 files changed, 17 insertions(+), 10 deletions(-)
diff
Past evidence with system hangs and hsds tie
WaForceEnableNonCoherent and WaDisableHDCInvalidation to
WaForceContextSaveRestoreNonCoherent. Documentation
states that WaForceContextSaveRestoreNonCoherent would
not be needed on skl past E0 but evidence proved otherwise. See
commit <510650e8b2ab> ("dr
We need this gafs bit to be enabled for hw fix to
take effect.
References: HSD#2227156, HSD#2227050
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i
Add this workaround for A0 and B0 revisions
References: HSD#2226935
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 36 ++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/
Add this workaround for kbl revid A0 only.
v2: rebase
References: HSD#1911714
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c| 16
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/
We need this crucial workaround from skl also to all kbl revisions.
Lack of it was causing system hangs on skl enabling so this is
a must have.
v2: Don't add revid checks to gen9 init workarounds (Arun)
References: HSD#2126660
Cc: Arun Siluvery
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/
Extend the scope of this workaround, already used in skl,
to also take effect in kbl.
References: HSD#2132677
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_lrc.c| 5 +++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 ++
Workaround for display underrun issues with Y & Yf Tiling.
Set this on all gen9 as stated by bspec.
v2: proper workaround name
References: HSD#2136383, BSID#857
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 7
Now that drm_i915_private contains drm_device, we can directly go to the
drm_device as required:
textdata bss dec hex filename
1105153 23207 416 1128776 113948 i915.ko (before)
1102849 23207 416 1126472 113048 i915.ko (after)
s/dev_priv->dev->/dev_priv->drm./
s/de
On Fri, May 27, 2016 at 05:27:01PM +0300, Mika Kuoppala wrote:
> According to bspec this prevents screen corruption when fbc is
> used.
>
> v2: This workaround has a name, use it (Ville)
>
> References: HSD#213, HSD#2137270, BSID#562
> Cc: Paulo Zanoni
> Signed-off-by: Mika Kuoppala
> ---
>
On Fri, May 27, 2016 at 05:26:58PM +0300, Mika Kuoppala wrote:
> We need this gafs bit to be enabled for hw fix to
> take effect.
>
> References: HSD#2227156, HSD#2227050
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer
== Series Details ==
Series: kbl and gen9 workarounds (rev6)
URL : https://patchwork.freedesktop.org/series/7824/
State : failure
== Summary ==
Series 7824v6 kbl and gen9 workarounds
http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/6/mbox
Test gem_exec_flush:
Subgroup ba
== Series Details ==
Series: series starting with [01/11] drm: Export drm_dev_init() for subclassing
(rev2)
URL : https://patchwork.freedesktop.org/series/7890/
State : failure
== Summary ==
Applying: drm: Export drm_dev_init() for subclassing
Applying: drm: Add a callback from connector regi
On Fri, May 27, 2016 at 05:26:47PM +0300, Mika Kuoppala wrote:
> Add this workaround for kbl revid A0 only.
2 w/a in one patch, WaClearSlmSpaceAtContextSwitch:kbl is not mentioned
here.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
In
The latest mainline kernel (commit 3f59de0) shows a regression. The symptom is
that as soon as the kernel is started, the display is blanked, and it is never
turned on again. This problem was bisected to commit
f21a21983ef13a031250c4c3f6018e29a549d0f1
("drm/i915: Splitting intel_dp_detect"). The
Hi, Chris
See comment below
BR
Nils
On 27 May 2016 7:01 a.m., "Chris Wilson" wrote:
>
> In order to allow drivers to pack their privates and drm_device into one
> struct (e.g. for subclassing), export the initialisation routines for
> struct drm_device.
>
> Signed-off-by: Chris Wilson
> Cc: Dan
On Fri, May 27, 2016 at 05:29:43PM +0200, Nils Wallménius wrote:
>Hi, Chris
>
>See comment below
>
>> err_setunique:
>> if (drm_core_check_feature(dev, DRIVER_GEM))
>> @@ -653,8 +650,46 @@ err_minors:
>> drm_fs_inode_free(dev->anon_inode);
>> err_free
On 27 May 2016 at 16:36, Chris Wilson wrote:
> On Fri, May 27, 2016 at 05:29:43PM +0200, Nils Wallménius wrote:
>>Hi, Chris
>>
>>See comment below
>>
>>> err_setunique:
>>> if (drm_core_check_feature(dev, DRIVER_GEM))
>>> @@ -653,8 +650,46 @@ err_minors:
>>>
On Fri, May 27, 2016 at 04:54:46PM +0100, Emil Velikov wrote:
> On 27 May 2016 at 16:36, Chris Wilson wrote:
> > On Fri, May 27, 2016 at 05:29:43PM +0200, Nils Wallménius wrote:
> >>Hi, Chris
> >>
> >>See comment below
> >>
> >>> err_setunique:
> >>> if (drm_core_check_fea
On 27 May 2016 at 17:08, Chris Wilson wrote:
> On Fri, May 27, 2016 at 04:54:46PM +0100, Emil Velikov wrote:
>> On 27 May 2016 at 16:36, Chris Wilson wrote:
>> > On Fri, May 27, 2016 at 05:29:43PM +0200, Nils Wallménius wrote:
>> >>Hi, Chris
>> >>
>> >>See comment below
>> >>
>> >>>
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