From: Shubhangi Shrivastava
Since commit 30d9aa4265fe ("drm/i915: Read sink_count dpcd always"),
the status of a DP connector depends on its sink count value.
However, some eDP panels don't set that value appropriately,
causing them to be reported as disconnected.
Fix this by ignoring sink count
From: "jim.br...@linux.intel.com"
In commit 7d23e3c37bb3 ("drm/i915: Cleaning up intel_dp_hpd_pulse") some
much needed clean-up was done, but unfortunately part of the change
broke DP MST. The real issue was setting the connector state to
disconnected in the MST case, which is good, but the code
On Tue, 12 Apr 2016, Thierry Reding wrote:
> On Tue, Apr 12, 2016 at 03:16:13PM +0100, Lee Jones wrote:
> > On Tue, 12 Apr 2016, Thierry Reding wrote:
> >
> > > On Wed, Mar 30, 2016 at 10:03:26PM +0200, Boris Brezillon wrote:
> > > > pwm->period field is not supposed to be changed by PWM users. T
On Wed, 13 Apr 2016, Lee Jones wrote:
> On Tue, 12 Apr 2016, Thierry Reding wrote:
>
> > On Tue, Apr 12, 2016 at 03:16:13PM +0100, Lee Jones wrote:
> > > On Tue, 12 Apr 2016, Thierry Reding wrote:
> > >
> > > > On Wed, Mar 30, 2016 at 10:03:26PM +0200, Boris Brezillon wrote:
> > > > > pwm->perio
On 12/04/16 17:21, Chris Wilson wrote:
On Tue, Apr 12, 2016 at 04:56:51PM +0100, Tvrtko Ursulin wrote:
From: Chris Wilson
By tracking the iomapping on the VMA itself, we can share that area
between multiple users. Also by only revoking the iomapping upon
unbinding from the mappable portion of
On Tue, Apr 12, 2016 at 03:52:48PM -0700, Bob Paauwe wrote:
> if the crtc has audio is enabled. Otherwise, when the first atomic
> modeset happens it will warn when trying to drop the audio power
> domain.
>
> Signed-off-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 +
> 1
On Wed, Apr 13, 2016 at 09:45:03AM +0100, Tvrtko Ursulin wrote:
>
> On 12/04/16 17:21, Chris Wilson wrote:
> >On Tue, Apr 12, 2016 at 04:56:51PM +0100, Tvrtko Ursulin wrote:
> >>From: Chris Wilson
> >>
> >>By tracking the iomapping on the VMA itself, we can share that area
> >>between multiple us
It was noticed on bug #94087 that module parameter
i915.edp_vswing=2 that should override the VBT setting
to use default voltage swing (400 mV) was not applied
for Broadwell.
This patch provides a fix for this by checking if default
i.e. higher voltage swing is requested to be used and
applies the
On 12/04/16 09:16, Patchwork wrote:
== Series Details ==
Series: drm/i915: Fixing eDP detection on certain platforms (rev4)
URL : https://patchwork.freedesktop.org/series/5408/
State : failure
== Summary ==
Series 5408v4 drm/i915: Fixing eDP detection on certain platforms
http://patchwork.f
On 13/04/16 10:04, Chris Wilson wrote:
On Wed, Apr 13, 2016 at 09:45:03AM +0100, Tvrtko Ursulin wrote:
On 12/04/16 17:21, Chris Wilson wrote:
On Tue, Apr 12, 2016 at 04:56:51PM +0100, Tvrtko Ursulin wrote:
From: Chris Wilson
By tracking the iomapping on the VMA itself, we can share that ar
This function is useful for gen2 intel devices which have no frame
counter, but need a way to determine the current vblank count without
racing with the vblank interrupt handler.
intel_pipe_update_start checks if no vblank interrupt will occur
during vblank evasion, but cannot check whether the vb
With the removal of cs flips this is always force enabled.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_params.c | 5 -
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_lrc.c | 3 +--
3 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/driver
Do it in 1 step instead, use atomic_read since INTEL_FLIP_COMPLETE
is no longer useful.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 --
drivers/gpu/drm/i915/i915_irq.c | 18 ++-
drivers/gpu/drm/i915/intel_display.c | 96 ++--
This will be required to allow more than 1 update in the future.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_debugfs.c | 90 -
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 107 +++---
Re-use unpin_work->pending, but also set vblank count before
intel_mark_page_flip_active to be sure.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 ++-
drivers/gpu/drm/i915/intel_display.c | 31 ---
drivers/gpu/drm/i915/intel_d
Rename intel_unpin_work to intel_flip_work and use it for mmio flips
and unpinning. Use flip_queued_req to hold the wait request in the
mmio case and allow the vblank interrupt to complete mmio work to
have mmio flips run correctly on g4 and earlier.
Changes since v1:
- Add smp_mb__after_atomic()
Create a work structure that will be used for all changes. This will
be used later on in the atomic commit function.
Changes since v1:
- Free old_crtc_state from unpin_work_fn properly.
Changes since v2:
- Add hunk for calling hw state verifier.
- Add missing support for color spaces.
Signed-off-
Set plane_state->base.fence to the dma_buf exclusive fence,
and add a wait to the mmio function. This will make it easier
to unify plane updates later on.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 54 +++
With mmio flips now available on all platforms it's time to remove
support for cs flips.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +--
drivers/gpu/drm/i915/intel_display.c | 273 +--
drivers/gpu/drm/i915/intel_drv.h | 6
With the removal of cs support this is no longer reachable.
Can be revived if needed.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 5 -
drivers/gpu/drm/i915/intel_display.c | 259 ---
2 files changed, 264 deletions(-)
diff --git a
This uses the newly created drm_accurate_vblank_count_and_time to accurately
get a vblank count when the hw counter is unavailable.
---
drivers/gpu/drm/i915/intel_display.c | 10 ++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
drivers/gpu/drm/i915/intel_sprite.c | 8 ++--
3 files c
This patch first adds drm_accurate_vblank_count, which needs an ack from
airlied to get through dinq.
After adding support for mmio updates on all platforms support for cs flips is
removed.
It's hard to test properly and makes async atomic commit harder to get right.
Maarten Lankhorst (11):
d
On Tue, Apr 12, 2016 at 09:03:05PM +0100, Chris Wilson wrote:
> Two concurrent writes into the same register cacheline has the chance of
> killing the machine on Ivybridge and other gen7. This includes LRI
> emitted from the command parser. The MI_SET_CONTEXT itself serves as
> serialising barrier
On Tue, Apr 12, 2016 at 09:03:06PM +0100, Chris Wilson wrote:
> For reasons unknown Sandybridge GT1 (at least) will eventually hang when
> it encounters a ring wraparound at offset 0. The test case that
> reproduces the bug reliably forces a large number of interrupted context
> switches, thereby c
On 12/04/16 17:54, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915: Split execlists hardware status
page initialisation from setup
URL : https://patchwork.freedesktop.org/series/5596/
State : failure
== Summary ==
Series 5596v1 Series without cover letter
When setting up the overlay page, we pin it into the GGTT (when using
virtual addresses) and store the offset as overlay->flip_addr. Rather
than doing a lookup of the GGTT address everytime, we can use the known
address instead.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm
By tracking the iomapping on the VMA itself, we can share that area
between multiple users. Also by only revoking the iomapping upon
unbinding from the mappable portion of the GGTT, we can keep that iomap
across multiple invocations (e.g. execlists context pinning).
Note that by moving the iounnma
The ioremap() hidden behind the io_mapping_map_wc() convenience helper
can be used for remapping multiple pages. Extend the helper so that
future callers can use it for larger ranges.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: David Airlie
Cc: Yishai
On Wed, Apr 13, 2016 at 10:14:50AM +0100, Tvrtko Ursulin wrote:
> On 13/04/16 10:04, Chris Wilson wrote:
> >On Wed, Apr 13, 2016 at 09:45:03AM +0100, Tvrtko Ursulin wrote:
> >>I could have two separate series to simplify dependencies a bit:
> >>
> >> 1. GuC premature unpin and
> >> 2. execlist no
On Tue, Apr 12, 2016 at 09:03:09PM +0100, Chris Wilson wrote:
> Conceptually, each request is a record of a hardware transaction - we
> build up a list of pending commands and then either commit them to
> hardware, or cancel them. However, whilst building up the list of
> pending commands, we may m
Seems to be in-line with the spec, so with Chris' comment addressed
and s/idi has mask/idi hash mask/:
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, Apr 12, 2016 at 09:03:08PM +0100, Chris Wilson wrote:
> After mi_set_context() succeeds, we need to update the state of the
> engine's last_context. This ensures that we hold a pin on the context
> whilst the hardware may write to it. However, since we didn't complete
> the post-switch setu
On Tue, Apr 05, 2016 at 11:30:19AM +0300, Jani Nikula wrote:
> On Mon, 04 Apr 2016, Ramalingam C wrote:
> > On Thursday 31 March 2016 12:34 AM, Daniel Vetter wrote:
> >> On Wed, Mar 30, 2016 at 07:49:40PM +0530, Ramalingam C wrote:
> >>> On Wednesday 30 March 2016 05:02 PM, Daniel Vetter wrote:
>
On Wed, Apr 13, 2016 at 11:59:06AM +0200, Daniel Vetter wrote:
> On Tue, Apr 12, 2016 at 09:03:08PM +0100, Chris Wilson wrote:
> > After mi_set_context() succeeds, we need to update the state of the
> > engine's last_context. This ensures that we hold a pin on the context
> > whilst the hardware ma
On Tue, Apr 05, 2016 at 03:10:39PM +0530, Ramalingam C wrote:
>
> On Tuesday 05 April 2016 02:00 PM, Jani Nikula wrote:
> >On Mon, 04 Apr 2016, Ramalingam C wrote:
> >>On Thursday 31 March 2016 12:34 AM, Daniel Vetter wrote:
> >>>On Wed, Mar 30, 2016 at 07:49:40PM +0530, Ramalingam C wrote:
> >>>
On Tue, Apr 12, 2016 at 12:18:43PM -0700, Alexandra Yates wrote:
> This project is explained in detail on the HAS
> https://docs.google.com/a/intel.com/document/d/1E-en_xqfHgCnhD1Tes3f08UYrOc-etv2W-pU0ZErKdE/edit?usp=sharing
>
>
> Summary:
> Permits the user to identify and toggle values for P
On Tue, 12 Apr 2016, Alexandra Yates wrote:
> Permits the user to identify and toggle values for PSR, FBC, RC6,
> DRRS, and IPS under /sys/class/drm/card0/power/. By enabling these
> features I'm looking to empower our customers, such as, power team,
> chrome OS, and platform integration teams to
Looks good, so with s/INTEL_INFO/INTEL_GEN/:
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, 13 Apr 2016, Daniel Vetter wrote:
> On Tue, Apr 05, 2016 at 03:10:39PM +0530, Ramalingam C wrote:
>>
>> On Tuesday 05 April 2016 02:00 PM, Jani Nikula wrote:
>> >On Mon, 04 Apr 2016, Ramalingam C wrote:
>> >>On Thursday 31 March 2016 12:34 AM, Daniel Vetter wrote:
>> >>>On Wed, Mar 30, 2
On Wed, Apr 13, 2016 at 1:06 PM, Jani Nikula wrote:
>> Then fix adjusted_mode to have the timings in terms of txbyteclkhs
>> already. Problem solved.
>
> I let Ville convince me there would be problems with that. Ville, care
> to fill in the details?
If we change them too hard the accurate vblank
On Wed, Apr 13, 2016 at 1:48 PM, Daniel Vetter wrote:
> On Wed, Apr 13, 2016 at 1:06 PM, Jani Nikula wrote:
>>> Then fix adjusted_mode to have the timings in terms of txbyteclkhs
>>> already. Problem solved.
>>
>> I let Ville convince me there would be problems with that. Ville, care
>> to fill i
On Fri, Apr 01, 2016 at 09:48:50PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Eliminate the duplicate code for pipe timing readout in
> intel_crtc_mode_get() by using the functions we use for the normal state
> readout.
I also forgot to point out here that this should
On 04/12/2016 04:51 PM, Michał Winiarski wrote:
> We started to use PIPE_CONTROL to write render ring seqno in order to
> combat seqno write vs interrupt generation problems. This was introduced
> by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt
> generation on gen8+ execlists
On 13/04/16 10:52, Chris Wilson wrote:
When setting up the overlay page, we pin it into the GGTT (when using
virtual addresses) and store the offset as overlay->flip_addr. Rather
than doing a lookup of the GGTT address everytime, we can use the known
address instead.
Signed-off-by: Chris Wilson
Hello,
As we have new laptops on the Skylake platform in our company i would like
to know a bit more about the firmware needed(or is it only recommended?),
more specifically about what actually happens when it is not installed.
I looked around and read informations such as
https://01.org/linuxgra
On 13/04/16 10:52, Chris Wilson wrote:
By tracking the iomapping on the VMA itself, we can share that area
between multiple users. Also by only revoking the iomapping upon
unbinding from the mappable portion of the GGTT, we can keep that iomap
across multiple invocations (e.g. execlists context
On Thu, 07 Apr 2016, Jani Nikula wrote:
> On Thu, 07 Apr 2016, Chris Wilson wrote:
>> On Thu, Apr 07, 2016 at 12:48:17PM +0300, Jani Nikula wrote:
>>> Sudden realization:
>>>
>>> $ grep -ho "INTEL_INFO([^)]*)->[a-zA-Z0-9_]*" *.[ch] | sed 's/.*->//' |\
>>> sort | uniq -c | sort -rn | head -5
>>
On Wed, Apr 13, 2016 at 01:30:39PM +0100, Tvrtko Ursulin wrote:
> As long as it remains hidden in here, otherwise is a bit heavy and
> rude (BUG_ON), or weak as API (if converted to GEM_BUG_ON and return
> pointer undocumented). And if it stays here BUG_ON is redundant.
> Hm.. leaning towards the d
Ben Widawsky writes:
> [ text/plain ]
> On Tue, Apr 05, 2016 at 03:56:17PM +0300, Mika Kuoppala wrote:
>> Experiments with heaven 4.0 benchmark and skylake gt3e (rev 0xa)
>> suggest that WaForceContextSaveRestoreNonCoherent is needed for all
>> revs. Extending this to all revs cures a gpu hang wi
On 4/8/2016 6:25 PM, David Weinehall wrote:
On Fri, Apr 08, 2016 at 12:00:22PM +0300, Jani Nikula wrote:
On Thu, 07 Apr 2016, Animesh Manna wrote:
Guid is changed for bxt platform, so corrected the guid for bxt.
Signed-off-by: Ananth Krishna R
Signed-off-by: Bharath K Veera
Signed-off-by:
Em Ter, 2016-04-12 às 12:18 -0700, Alexandra Yates escreveu:
> This interface allows an immediate enabling of FBC feature. What
> allow us
> to see immediately the FBC
There's no way to guarantee the user will immediately see any FBC
savings. FBC depends on a lot of conditions (e.g., X tiling, cor
Abdiel Janulgue writes:
> [ text/plain ]
>
>
> On 04/12/2016 04:51 PM, Michał Winiarski wrote:
>> We started to use PIPE_CONTROL to write render ring seqno in order to
>> combat seqno write vs interrupt generation problems. This was introduced
>> by commit 7c17d377374d ("drm/i915: Use ordered seq
Em Ter, 2016-04-12 às 12:18 -0700, Alexandra Yates escreveu:
> This project is explained in detail on the HAS
> https://docs.google.com/a/intel.com/document/d/1E-en_xqfHgCnhD1Tes3f0
> 8UYrOc-etv2W-pU0ZErKdE/edit?usp=sharing
>
> Summary:
> Permits the user to identify and toggle values for PSR,
On Tue, 12 Apr 2016, Jani Nikula wrote:
> On Tue, 12 Apr 2016, Chris Wilson wrote:
>> On Fri, Apr 08, 2016 at 05:59:49PM +0300, Jani Nikula wrote:
>>> The whole file is ignored on CONFIG_ACPI=n.
>>
>> That's an issue as we can't then acquire the opregion->vbt (which itself
>> is not acpi dependen
On Wednesday 13 April 2016 05:27 PM, Daniel Vetter wrote:
On Wed, Apr 13, 2016 at 1:48 PM, Daniel Vetter wrote:
On Wed, Apr 13, 2016 at 1:06 PM, Jani Nikula wrote:
Then fix adjusted_mode to have the timings in terms of txbyteclkhs
already. Problem solved.
I let Ville convince me there would
Em Ter, 2016-04-12 às 12:18 -0700, Alexandra Yates escreveu:
> This interface allows an immediate enabling of PSR feature. What
> allow us
> to see immediately the PSR savings and will allow us to expose this
> through sysfs interface for powertop to leverage its functionality.
>
> Signed-off-by:
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 47 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 --
2 files changed, 16 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6e158b3d3ea0..dff14343a
From: Peter Antoine
Allow for the MOCS to be programmed for all engines.
Currently we program the MOCS when the first render batch
goes through. This works on most platforms but fails on
platforms that do not run a render batch early,
i.e. headless servers. The patch now programs all initialised
On Tue, Apr 12, 2016 at 12:52:24PM +0100, Peter Antoine wrote:
> Chris,
>
> If the test is ok, can you review-by this patch.
Yup, my box decided that was good time to suffer fs corruption. Patched
up and resent for CI with my r-b.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
From: Praveen Paneri
When the system is running low on memory, gem shrinker is invoked.
In this process objects will be unbounded from GTT and unbinding process
will require access to GTT(GTTADR) and also to fence register potentially.
That requires a resume of gfx device, if suspended, in the sh
Praveen Paneri (2):
drm/i915: Unbind objects in shrinker only if device is runtime active
drm/i915: Add rpm get/put in i915_shrinker_oom
drivers/gpu/drm/i915/i915_gem_shrinker.c | 14 ++
1 file changed, 14 insertions(+)
--
2.5.0
___
From: Praveen Paneri
i915_gem_shrink_all() will scan the bound list only if device is not
suspended but in OOM scenarios it becomes absolutely necessary to
release as much memory as possible. So, adding rpm get/put in
i915_shrinker_oom() to ensure shrinking of bound objects in OOM
scenario.
Sign
On 4/8/2016 2:35 AM, Imre Deak wrote:
On Thu, 2016-04-07 at 20:22 +0530, Animesh Manna wrote:
Along with below patches sharing some background details/design.
- On BXT, Display cannot generate an interrupt when in D3.
- Without display in D3, S0ix can be achieved, Power impact
will be zero if
On 4/13/2016 7:17 PM, Animesh Manna wrote:
On 4/8/2016 2:35 AM, Imre Deak wrote:
On Thu, 2016-04-07 at 20:22 +0530, Animesh Manna wrote:
Along with below patches sharing some background details/design.
- On BXT, Display cannot generate an interrupt when in D3.
- Without display in D3, S0ix
On Wed, Apr 13, 2016 at 04:54:07PM +0300, Mika Kuoppala wrote:
> From: Praveen Paneri
>
> i915_gem_shrink_all() will scan the bound list only if device is not
> suspended but in OOM scenarios it becomes absolutely necessary to
> release as much memory as possible. So, adding rpm get/put in
> i915
From: Peter Antoine
Allow for the MOCS to be programmed for all engines.
Currently we program the MOCS when the first render batch
goes through. This works on most platforms but fails on
platforms that do not run a render batch early,
i.e. headless servers. The patch now programs all initialised
Having the !RCS legacy context switch threaded through the RCS switching
code makes it much harder to follow and understand. In the next patch, I
want to fix a bug handling the incomplete switch, this is made much
simpler if we segregate the two paths now.
Signed-off-by: Chris Wilson
Cc: Daniel V
After mi_set_context() succeeds, we need to update the state of the
engine's last_context. This ensures that we hold a pin on the context
whilst the hardware may write to it. However, since we didn't complete
the post-switch setup of the context, we need to force the subsequent
use of the same cont
On 13/04/2016 10:57, Daniel Vetter wrote:
On Tue, Apr 12, 2016 at 09:03:09PM +0100, Chris Wilson wrote:
Conceptually, each request is a record of a hardware transaction - we
build up a list of pending commands and then either commit them to
hardware, or cancel them. However, whilst building up t
With gen9+ the edram capabilities are defined so
that we can calculate the edram (ellc) size accordingly.
Note that there are undefined combinations for some subset of
edram capability bits. Return the closest size for undefined indexes.
Even if we get it wrong with beginning of future gen enablin
Store the edram capabilities instead of only the size of
edram. This is preparatory patch to allow edram size calculation
based on edram capability bits for gen9+. With gen9 the
edram is behind llc and is a separate entity. With hsw/bdw
it was more of a victim cache for LLC so the name 'eLLC' might
For gen9 onwards, eDRAM is a true memory side cache. So
there is no need to program idi hash mask as it is for eLLC
only.
v2: INTEL_GEN (Chris), s/has/hash (Matthew)
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+
Mika Kuoppala (3):
drm/i915: Don't program eLLC IDI hash mask for gen9+
drm/i915: Store and use edram capabilities
drm/i915: Calculate edram size
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_drv.h | 7 +++--
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drive
== Series Details ==
Series: series starting with [1/5] drm/i915: use dev_priv directly in
gen8_ppgtt_notify_vgt
URL : https://patchwork.freedesktop.org/series/5601/
State : failure
== Summary ==
Series 5601v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/5601/re
On Wed, Apr 13, 2016 at 06:34:25PM +0530, Ramalingam C wrote:
>
> On Wednesday 13 April 2016 05:27 PM, Daniel Vetter wrote:
> >On Wed, Apr 13, 2016 at 1:48 PM, Daniel Vetter wrote:
> >>On Wed, Apr 13, 2016 at 1:06 PM, Jani Nikula wrote:
> Then fix adjusted_mode to have the timings in terms o
By tracking the iomapping on the VMA itself, we can share that area
between multiple users. Also by only revoking the iomapping upon
unbinding from the mappable portion of the GGTT, we can keep that iomap
across multiple invocations (e.g. execlists context pinning).
Note that by moving the iounnma
On Wed, Apr 13, 2016 at 12:59:18PM +, Zanoni, Paulo R wrote:
> Em Ter, 2016-04-12 às 12:18 -0700, Alexandra Yates escreveu:
> > This project is explained in detail on the HAS
> > https://docs.google.com/a/intel.com/document/d/1E-en_xqfHgCnhD1Tes3f0
> > 8UYrOc-etv2W-pU0ZErKdE/edit?usp=sharing
On Wed, Apr 13, 2016 at 03:16:30PM +0100, Chris Wilson wrote:
> Having the !RCS legacy context switch threaded through the RCS switching
> code makes it much harder to follow and understand. In the next patch, I
> want to fix a bug handling the incomplete switch, this is made much
> simpler if we s
Rebased the patches to apply against drm-intel-nightly
Lyude (4):
drm/dp_helper: Always wait before retrying native aux transactions
drm/dp_helper: Retry aux transactions on all errors
drm/dp_helper: Perform throw-away read before actual read in
drm_dp_dpcd_read()
drm/i915: Get rid of
This is part of a patch series to migrate all of the workarounds for
commonly seen behavior from bad sinks in intel_dp_dpcd_read_wake() to
drm's DP helper.
Some sinks need some time during the process of resuming the system from
sleep before they're ready to handle transactions. While it would be
This is part of a patch series to migrate all of the workarounds for
commonly seen behavior from bad sinks in intel_dp_dpcd_read_wake() to drm's
DP helper.
Some sinks will just return garbage for the first aux tranaction they
receive when coming out of sleep mode, so we need to perform an addition
Since we've fixed up drm_dp_dpcd_read() to allow for retries when things
timeout, there's no use for having this function anymore. Good riddens.
Signed-off-by: Lyude
---
drivers/gpu/drm/i915/intel_dp.c | 81 -
1 file changed, 23 insertions(+), 58 deletions
== Series Details ==
Series: Gen8 Execlist based Engine reset and recovery support
URL : https://patchwork.freedesktop.org/series/5603/
State : failure
== Summary ==
Series 5603v1 Gen8 Execlist based Engine reset and recovery support
http://patchwork.freedesktop.org/api/1.0/series/5603/revisio
On Wed, Apr 13, 2016 at 04:56:05PM +0200, Daniel Vetter wrote:
> On Wed, Apr 13, 2016 at 03:16:30PM +0100, Chris Wilson wrote:
> > + if (needs_pd_load_pre(engine, to)) {
>
> Hm, I'd inline this condition now since it's a bit confusing if there's no
> POST. Assuming I read code correctly
hw_flags)
> return ret;
> }
>
> -static inline bool skip_rcs_switch(struct intel_engine_cs *engine,
> -struct intel_context *from,
> +static inline bool skip_rcs_switch(struct intel_context *from,
> struct intel_context *to)
This is part of a patch series to migrate all of the workarounds for
commonly seen behavior from bad sinks in intel_dp_dpcd_read_wake() to
drm's DP helper.
We cannot rely on sinks NACKing or deferring when they can't receive
transactions, nor can we rely on any other sort of consistent error to
kn
Hi Chris,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20160413]
[cannot apply to v4.6-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson
On Wed, Apr 13, 2016 at 03:47:58PM +0100, Chris Wilson wrote:
> + /* We also want to clear any cached iomaps as they wrap vmap */
> + list_for_each_entry_safe(vma, next,
> + &dev_priv->ggtt.base.inactive_list, vm_link)
> + if (vma->iomap && i915_vma_
On Wed, Apr 13, 2016 at 05:05:05PM +0200, Daniel Vetter wrote:
> > static bool
> > -needs_pd_load_post(struct intel_engine_cs *engine, struct intel_context
> > *to,
> > - u32 hw_flags)
> > +needs_pd_load_post(struct intel_context *to, u32 hw_flags)
> > {
> > - struct drm_i915_priv
== Series Details ==
Series: series starting with [1/5] drm/i915: Add sys PSR toggle interface
URL : https://patchwork.freedesktop.org/series/5609/
State : failure
== Summary ==
Series 5609v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/5609/revisions/1/mbox/
Te
The two behavioral changes here are the correct detection of the eDRAM size on
gen9 (SKL + KBL), and unconditional printing of the eLLC size.
Cc: Eero Tamminen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_uncore.c | 16 +---
1 file changed, 13 insertions(+), 3 deletion
== Series Details ==
Series: drm/i915: Rest of my DSI and DPLL stuff
URL : https://patchwork.freedesktop.org/series/5610/
State : failure
== Summary ==
Series 5610v1 drm/i915: Rest of my DSI and DPLL stuff
http://patchwork.freedesktop.org/api/1.0/series/5610/revisions/1/mbox/
Test drv_hangman
== Series Details ==
Series: drm/i915: Get audio power domain during initial hw readout
URL : https://patchwork.freedesktop.org/series/5622/
State : failure
== Summary ==
Series 5622v1 drm/i915: Get audio power domain during initial hw readout
http://patchwork.freedesktop.org/api/1.0/series/56
On Wed, Apr 13, 2016 at 04:02:17PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Rest of my DSI and DPLL stuff
> URL : https://patchwork.freedesktop.org/series/5610/
> State : failure
>
> == Summary ==
>
> Series 5610v1 drm/i915: Rest of my DSI and DPLL stuff
> http://pa
== Series Details ==
Series: series starting with [RESEND,FOR,CI,1/2] drm/i915/dp/mst: Fix MST logic
in intel_dp_long_pulse()
URL : https://patchwork.freedesktop.org/series/5642/
State : failure
== Summary ==
Series 5642v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/s
For debug and development purposes only.
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +++
drivers/gpu/drm/i915/i915_params.c | 6 ++
drivers/gpu/drm/i915/i915_params.h |
== Series Details ==
Series: drm/i915: Fix eDP low vswing for Broadwell (rev3)
URL : https://patchwork.freedesktop.org/series/4499/
State : failure
== Summary ==
CC drivers/usb/host/xhci-trace.o
CC drivers/usb/storage/usual-tables.o
CC drivers/usb/host/xhci-pci.o
CONMK
On 13/04/16 17:57, Ben Widawsky wrote:
For debug and development purposes only.
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +++
drivers/gpu/drm/i915/i915_params.c | 6 +
Hi,
Here's an updated series with comments addressed. It alsos gives VLV
code the same treatment.
Thanks,
Ander
Cc: Ville Syrjälä
Ander Conselvan de Oliveira (10):
drm/i915: Set crtc_state->lane_count for HDMI
drm/i915: Unduplicate CHV signal level code
drm/i915: Unduplicate chv_data_lan
The code for programming voltage swing and emphasis was duplicated
between DP and HDMI code. Move that to a new file, intel_dpio_phy.c.
v2: Keep the "Use 800mV-0dB" comment in the HDMI code. (Ville)
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/Makefile | 1 +
dr
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