On Tue, Apr 12, 2016 at 03:40:42PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> We can use the new pin/lazy unpin API for simplicity
> and more performance in the execlist submission paths.
>
> v2:
> * Fix error handling and convert more users.
> * Compact some names for readabili
On Fri, Apr 01, 2016 at 04:02:34PM +0300, Imre Deak wrote:
> This register is read-only, so we have never actually set
> OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a code
> comment about this. I filed a specification update request to clarify
> this there.
>
> CC: Arthur J R
On Fri, Apr 01, 2016 at 04:02:40PM +0300, Imre Deak wrote:
> For internal APIs passing dev_priv is preferred to reduce indirections,
> so convert over a few DDI PHY, CDCLK helpers.
>
> No functional change.
>
> Signed-off-by: Imre Deak
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i91
On Tue, Apr 12, 2016 at 04:58:07PM +0300, Mika Kuoppala wrote:
> Michał Winiarski writes:
>
> > [ text/plain ]
> > We started to use PIPE_CONTROL to write render ring seqno in order to
> > combat seqno write vs interrupt generation problems. This was introduced
> > by commit 7c17d377374d ("drm/i9
On Tue, Apr 12, 2016 at 02:32:31PM +0100, Chris Wilson wrote:
> When reviewing some of Tvrtko's usage for i915_gem_object_pin_map(), he
> suggested replacing some use of kmap(i915_gem_object_get_dirty_page())
> with a plain i915_gem_object_pin_map(). This raised the question of who
> should mark th
On Mon, Apr 04, 2016 at 05:27:10PM +0300, Imre Deak wrote:
> I caught a few errors in our current PHY/CDCLK programming by sanity
> checking the actual programmed state, so I thought it would be also
> useful for the future. In addition to verifying the state after
> programming it also verify it a
On Fri, Apr 01, 2016 at 04:02:46PM +0300, Imre Deak wrote:
> With the preceding fixes power well support should be functional on
> Broxton, I could enter/exit DC5 without problems.
>
> This reverts commit 18024199579882265653bfe9e2b1a3dcb5697cd9.
>
> CC: Matt Roper
> Signed-off-by: Imre Deak
R
On Fri, Apr 01, 2016 at 04:02:47PM +0300, Imre Deak wrote:
> With the preceding fixes runtime PM should be functional, I could
> runtime suspend/resume the device without problems.
>
> Signed-off-by: Imre Deak
Reviewed-by: David Weinehall
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 1 fi
From: Ville Syrjälä
The vlv/chv display irq setup was a bit of mess after I ran out of steam
when working on it last. Fix it up so that we just have a _reset() and
_postinstall() hooks for the display irqs, and use those consistently.
v2: Clear out pipestat_irq_mask[] and PIPE_FIFO_UNDERRUN_STAT
From: Tvrtko Ursulin
Similarly to i915_gem_object_pin_map on LLC platforms, we can
use the new VMA based io mapping on !LLC to decrease the cost
of ringbuf pinning and unpinning.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
drivers/gpu/drm/i915/intel_ringb
From: Chris Wilson
By tracking the iomapping on the VMA itself, we can share that area
between multiple users. Also by only revoking the iomapping upon
unbinding from the mappable portion of the GGTT, we can keep that iomap
across multiple invocations (e.g. execlists context pinning).
v2:
* Re
From: Ville Syrjälä
Reshuffle the code a bit to move the vlv/chv display irq functions away
from the main irq hooks, next to the other sub (de,gt,etc.) hooks.
v2: Rebased due to changes in vlv_display_irq_reset()
Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak (v1)
---
drivers/gpu/drm/i9
Remove dev local and use to_i915() in gen8_ppgtt_notify_vgt.
v2: use dev_priv directly for QUESTION_MACROS (Joonas Lahtinen)
Cc: Joonas Lahtinen
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/
For the gen6/gen8_allocate_va_range functions remove the WARN_ON range
sanity checks in favour of simply hardening the allocation paths. This
also fixes the inconsistency in which we don't always handle the
potential overflow in our checks.
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-by: Mat
We need to kunmap pt_vaddr and not pt itself, otherwise we end up
mapping a bunch of pages without ever unmapping them.
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
From: Chris Wilson
From: Chris Wilson
Propagate the real error from drm_gem_object_init(). Note this also
fixes some confusion in the error return from i915_gem_alloc_object...
v2:
(Matthew Auld)
- updated new users of gem_alloc_object from latest drm-nightly
- replaced occurrences of IS_E
If we are not in FULL_48BIT_PPGTT mode then we really shouldn't
continue on with our allocations, given that the call to free_dpd would
bail early without freeing everything, thus leaking memory.
Cc: Chris Wilson
Cc: Joonas Lahtinen
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem
Sounds good, I'll have the rebased versions posted in a bit
On Tue, 2016-04-12 at 13:17 +0300, Jani Nikula wrote:
> On Mon, 28 Mar 2016, Lyude wrote:
> >
> > Resending this because it looks like replying to my previous series
> > of patches
> > causes patchwork to pick up patches from the origin
== Series Details ==
Series: series starting with drm/i915: check for ERR_PTR from
i915_gem_object_pin_map() (rev2)
URL : https://patchwork.freedesktop.org/series/5591/
State : failure
== Summary ==
Series 5591v2 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/5591
== Series Details ==
Series: drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
(rev4)
URL : https://patchwork.freedesktop.org/series/4446/
State : success
== Summary ==
Series 4446v4 drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno
write
http://patchwork.
On Tue, Apr 12, 2016 at 01:51:02PM +0100, Lionel Landwerlin wrote:
> On 12/04/16 12:57, Daniel Vetter wrote:
> >On Mon, Apr 11, 2016 at 02:43:39PM +0100, Lionel Landwerlin wrote:
> >>Color management properties are a bit of an odd use case because
> >>they're not marked as atomic properties. Curren
On 12/04/16 14:51, Michał Winiarski wrote:
We started to use PIPE_CONTROL to write render ring seqno in order to
combat seqno write vs interrupt generation problems. This was introduced
by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt
generation on gen8+ execlists").
On gen8+
On Mon, Apr 11, 2016 at 02:30:51PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Fix VLV/CHV unclaimed register errors
> URL : https://patchwork.freedesktop.org/series/5531/
> State : failure
>
> == Summary ==
>
> Series 5531v1 drm/i915: Fix VLV/CHV unclaimed register er
On Tue, Apr 12, 2016 at 04:56:51PM +0100, Tvrtko Ursulin wrote:
> From: Chris Wilson
>
> By tracking the iomapping on the VMA itself, we can share that area
> between multiple users. Also by only revoking the iomapping upon
> unbinding from the mappable portion of the GGTT, we can keep that iomap
On Tue, Apr 12, 2016 at 04:56:52PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Similarly to i915_gem_object_pin_map on LLC platforms, we can
> use the new VMA based io mapping on !LLC to decrease the cost
> of ringbuf pinning and unpinning.
If you are going to mention pin_map, you op
On 12/04/16 17:03, Patchwork wrote:
== Series Details ==
Series: series starting with drm/i915: check for ERR_PTR from
i915_gem_object_pin_map() (rev2)
URL : https://patchwork.freedesktop.org/series/5591/
State : failure
== Summary ==
Series 5591v2 Series without cover letter
http://patchwo
Hi Maarten,
[auto build test WARNING on drm/drm-next]
[also build test WARNING on v4.6-rc3 next-20160412]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Maarten-Lankhorst/drm-core-Add
== Series Details ==
Series: drm/i915/gen9: implement WaEnableSamplerGPGPUPreemptionSupport (rev3)
URL : https://patchwork.freedesktop.org/series/5367/
State : failure
== Summary ==
Series 5367v3 drm/i915/gen9: implement WaEnableSamplerGPGPUPreemptionSupport
http://patchwork.freedesktop.org/ap
== Series Details ==
Series: series starting with [1/2] drm/i915: Split execlists hardware status
page initialisation from setup
URL : https://patchwork.freedesktop.org/series/5596/
State : failure
== Summary ==
Series 5596v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.
This change extends the idea of reset_counter variable to engine reset by
creating additional variables for each engine. Least significant bit is set
to mark the engine reset is pending and once reset is successful it is
incremented again, this is further used to count the no of engine resets.
Sig
From: Tomas Elf
There used to be a work queue separating the error handler from the hang
recovery path, which was removed a while back in this commit:
commit b8d24a06568368076ebd5a858a011699a97bfa42
Author: Mika Kuoppala
Date: Wed Jan 28 17:03:14 2015 +0200
drm/i915: Remove nested work i
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_params.c | 6 +++---
drivers/gpu/drm/i915/i915_params.h
To resume execution after engine reset we resubmit the context and this
needs to be treated differently otherwise we would count it as a completely
new submission. This change modifies the submission path to account for
this.
During resubmission we only submit the head request that caused the hang
From: Mika Kuoppala
To perform engine reset we first disable engine to capture its state. This
is done by issuing a reset request. Because we are reusing existing
infrastructure, again when we actually reset an engine, reset function
checks engine mask and issues reset request again which is unne
This is a preparatory patch which modifies error handler to do per engine
hang recovery. The actual patch which implements this sequence follows
later in the series. The aim is to prepare existing recovery function to
adapt to this new function where applicable (which fails at this point
because co
This change implements support for per-engine reset as an initial, less
intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset recovery mode if necessary. This is only supported
from Gen8 onwards.
Hangchecker determines which engines are hung and invokes er
Everything in place, flip the switch.
This feature is available only from Gen8, for previous gen devices driver
falls back to legacy full gpu reset.
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h| 4
drivers/gpu/drm/i915/i915_params.c | 4 ++-
This is a partial port of the following patch from John Harrison's GPU
scheduler patch series: (patch sent to Intel-GFX with the subject line
"[Intel-gfx] [RFC 19/39] drm/i915: Added scheduler support to __wait_request()
calls" on Fri 17 July 2015)
Author: John Harrison
Date: Th
A new variable is added to export the reset counts to debugfs, this
includes full gpu reset and engine reset count. This is useful for tests
where they areexpected to trigger reset; these counts are checked before
and after the test to ensure the same.
Signed-off-by: Arun Siluvery
---
drivers/gp
Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
driv
i915_gem_check_wedge now returns a non-zero result in three different cases:
1. Legacy: A hang has been detected and full GPU reset is in progress.
2. Per-engine recovery:
a. A single engine reference can be passed to the function, in which
case only that engine will be checked. If that par
Minimal state of engine is saved before resetting it, this state includes
head, current active request.
A consistency check is performed on the active request to make sure that
the context HW is executing is same as the one for the active request. This
check is important because engine recovery in
We capture the state of an engine before resetting it, once the reset is
successful engine is restored with the same state and restarted.
The state includes head register and active request. We also nudge the head
forward if it hasn't advanced, otherwise when the engine is restarted HW
executes th
On Tue, Apr 12, 2016 at 10:16:26AM +0200, Patrik Jakobsson wrote:
> On Fri, Apr 01, 2016 at 09:53:19PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > The underruns we were seeing when enabling eDP port A on ILK seem to
> > have been caused by prematurely clearing the
This series for Engine reset functionality from Gen8 onwards. Some of the
prep patches are already sent and merged, now follows more of them and
implementation patches.
Many many thanks to Mika and Chris for their time in review, these patches
have become much more simpler than they were originall
On Tue, Apr 12, 2016 at 03:04:10PM +0300, Imre Deak wrote:
> On ma, 2016-04-11 at 16:56 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Enable the unclaimd register detection stuff on vlv/chv since we've
> > now
> > fixed the known problems during suspend.
> >
> > Thi
On Tue, Mar 15, 2016 at 04:39:53PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Here's a pile of pending VLV/CHV DSI and DPLL patches I had lying around.
> Most of these have been posted before. Would be nice to finally get them
> in.
>
> I've tried to rebase things to a
This project is explained in detail on the HAS
https://docs.google.com/a/intel.com/document/d/1E-en_xqfHgCnhD1Tes3f08UYrOc-etv2W-pU0ZErKdE/edit?usp=sharing
Summary:
Permits the user to identify and toggle values for PSR, FBC, RC6, DRRS, and IPS
under /sys/class/drm/card0/power/. By enabling t
This interface allows enabling/disabling of RC6 feature. It allows
to see immediately the RC6 power management savings and will allow
to expose this through sysfs interface for powertop to leverage its
functionality.
Signed-off-by: Alexandra Yates
---
drivers/gpu/drm/i915/i915_drv.c | 5 +
From: Ville Syrjälä
Here is the remainder of my DSI/DPLL series [1]. Everything else got merged
already. The first patch in the series is the only one to lack an r-b.
Tested on BYT FFRD8 only, BXT stuff is not tested.
[1] https://lists.freedesktop.org/archives/intel-gfx/2016-March/089782.html
From: Ville Syrjälä
Fold the DSI PLL configuration functions into the DSI PLL
enable functions since they are small and not called from anywhere else.
Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 28 ++--
1 file chang
From: Ville Syrjälä
Set up DPLL and DPLL_MD even when driving DSI output on VLV/CHV. While
the DPLL isn't used to provide the clock we still need the refclock, and
it appears that the pixel repeat factor also has an effect on DSI
output. So set up eveyrhing in DPLL and DPLL_MD as we would do for
This interface allows enabling/disabling of DRRS feature. It allows
to see immediately the power management savings and will allow
to expose this through sysfs interface for powertop to leverage its
functionality.
Signed-off-by: Alexandra Yates
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
driv
This interface allows an immediate enabling of FBC feature. What allow us
to see immediately the FBC power management savings and will allow us to
expose this through sysfs interface for powertop to leverage its
functionality.
Signed-off-by: Alexandra Yates
---
drivers/gpu/drm/i915/i915_drv.h
This interface allows an immediate enabling of PSR feature. What allow us
to see immediately the PSR savings and will allow us to expose this
through sysfs interface for powertop to leverage its functionality.
Signed-off-by: Alexandra Yates
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/g
This interface allows enabling/disabling of IPS feature. It allows
to see immediately the power management savings and will allow
to expose this through sysfs interface for powertop to leverage its
functionality.
Signed-off-by: Alexandra Yates
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-
From: Ville Syrjälä
Add the scaling mode property to DSI connectors, handle changes in the
property value, and compute the panel fitter state during
.compute_config().
v2: Handle BXT as well
Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 73 +
From: Ville Syrjälä
Compute the DSI PLL parameters during .compute_config() rather than
.pre_pll_enable() so that we can fail gracefully if we can't find
suitable parameters.
In order to do that we need to store the DSI PLL parameters in
pipe_config.
v2: Handle BXT too
Signed-off-by: Ville Syr
From: Ville Syrjälä
We don't have a LVDS_BORDER_ENABLE type of bit for either eDP or DSI,
and just trying to frob the display timings to include borders results
in a corrupted picture. So reject the 'Center' scaling mode on GMCH
platforms for eDP and DSI.
TODO: Should really filter out the unsup
On Tue, Apr 12, 2016 at 08:08:01PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 12, 2016 at 03:04:10PM +0300, Imre Deak wrote:
> > On ma, 2016-04-11 at 16:56 +0300, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä
> > >
> > > Enable the unclaimd register detection stuff on vlv/chv sinc
After mi_set_context() succeeds, we need to update the state of the
engine's last_context. This ensures that we hold a pin on the context
whilst the hardware may write to it. However, since we didn't complete
the post-switch setup of the context, we need to force the subsequent
use of the same cont
As paranoia, we want to ensure that the CPU's PTEs have been revoked for
the object before we return from i915_gem_release_mmap(). This allows us
to rely on there being no outstanding memory accesses and guarantees
serialisation of the code against concurrent access just by calling
i915_gem_release
Currently there is a #define to enable extra BUG_ON for debugging
requests and associated activities. I want to expand its use to cover
all of GEM internals (so that we can saturate the code with asserts).
We can add a Kconfig option to make it easier to enable - with the usual
caveats of not enabl
This is principally a little bit of syntatic sugar to hide the
atomic_read()s throughout the code to retrieve the current reset_counter.
It also provides the other utility functions to check the reset state on the
already read reset_counter, so that (in later patches) we can read it once
and do mul
Our driver compiles clean (nowadays thanks to 0day) but for me, at least,
it would be beneficial if the compiler threw an error rather than a
warning when it found a piece of suspect code. (I use this to
compile-check patch series and want to break on the first compiler error
in order to fix the pa
Separate out the layers of includes (linux, drm, intel, i915) so that it
is a little easier to order our definitions between our multiple
reentrant headers. A couple of headers needed fixes to make them more
standalone (forgotten includes, forward declarations etc).
Signed-off-by: Chris Wilson
Re
As the request is only valid during the same global reset epoch, we can
record the current reset_counter when constructing the request and reuse
it when waiting upon that request in future. This removes a very hairy
atomic check serialised by the struct_mutex at the time of waiting and
allows us to
Conceptually, each request is a record of a hardware transaction - we
build up a list of pending commands and then either commit them to
hardware, or cancel them. However, whilst building up the list of
pending commands, we may modify state outside of the request and make
references to the pending
If we, when we store the reset_counter for the operation, we ensure that
it is not in a wedged or in the middle of a reset, we can then assert that
if any reset occurs the reset_counter must change. Later we can just
compare the operation's reset epoch against the current counter to see
if we need
In the reset_counter, we use two bits to track a GPU hang and reset. The
low bit is a "reset-in-progress" flag that we set to signal when we need
to break waiters in order for the recovery task to grab the mutex. As
soon as the recovery task has the mutex, we can clear that flag (which
we do by inc
Now that the reset_counter is stored on the request, we can rearrange
the code to handle reading the counter versus waiting during the atomic
modesetting for readibility (by deleting the hairiest of codes).
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Reviewed-by: Daniel Vetter
---
drivers/gp
Two concurrent writes into the same register cacheline has the chance of
killing the machine on Ivybridge and other gen7. This includes LRI
emitted from the command parser. The MI_SET_CONTEXT itself serves as
serialising barrier and prevents the pair of register writes in the first
packet from tri
I'm going to take back the NAK on this, apparently this hotplugging
issue has been around longer then this patchset.
Reviewed-by: Lyude
On Tue, 2016-04-12 at 10:11 +0300, Ander Conselvan De Oliveira wrote:
> On Mon, 2016-04-11 at 10:11 -0700, Jim Bride wrote:
> >
> > In commit 7d23e3c3 ("drm/i
If we do not have lowlevel support for reseting the GPU, or if the user
has explicitly disabled reseting the device, the failure is expected.
Since it is an expected failure, we should be using a lower priority
message than *ERROR*, perhaps NOTICE. In the absence of DRM_NOTICE, just
emit the expect
For reasons unknown Sandybridge GT1 (at least) will eventually hang when
it encounters a ring wraparound at offset 0. The test case that
reproduces the bug reliably forces a large number of interrupted context
switches, thereby causing very frequent ring wraparounds, but there are
similar bug repor
Reporting -EIO from i915_wait_request() has proven very troublematic
over the years, with numerous hard-to-reproduce bugs cropping up in the
corner case of where a reset occurs and the code wasn't expecting such
an error.
If the we reset the GPU or have detected a hang and wish to reset the
GPU, t
On Tue, Apr 12, 2016 at 07:39:35AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dp/mst: Fix MST logic in intel_dp_long_pulse() (rev3)
> URL : https://patchwork.freedesktop.org/series/5390/
> State : failure
>
> == Summary ==
>
> Series 5390v3 drm/i915/dp/mst: Fix MST log
if the crtc has audio is enabled. Otherwise, when the first atomic
modeset happens it will warn when trying to drop the audio power
domain.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_display.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_displ
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: Move ioremap_wc tracking onto
VMA
URL : https://patchwork.freedesktop.org/series/5599/
State : failure
== Summary ==
Series 5599v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/5599/revisions/1
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