From: Tom O'Rourke
v2: Add mutex lock/unlock
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_slpc.c | 5 +
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_
From: Dave Gordon
DO NOT MERGE: This patch is added for convenience in
reviewing SLPC patch series. This patch should be
merged as part of a separate series to enable guc
submission by default.
v5:
Rebased
Signed-off-by: Dave Gordon
Acked-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_p
From: Tom O'Rourke
Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC). SLPC is
a replacement for some host-based power management
features.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertions(+)
diff
From: Tom O'Rourke
Expose host2guc_action for use by SLPC in intel_slpc.c.
Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_guc_submission.c | 6 +++---
drivers/gpu/drm/i915/intel_g
From: Tom O'Rourke
SLPC shared data is used to pass information
to/from SLPC firmware.
For Skylake, platform sku type and slice count
are identified from device id and fuse values.
Support for other platforms needs to be added.
v2: Update for SLPC interface version 2015.2.4
intel_slpc_acti
From: Tom O'Rourke
On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.
v2: return void instead of ignored error code (Paulo)
enable/disable RC6 in SLPC flows (Sagar)
replace HAS_SLPC() use with i
From: Tom O'Rourke
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index 06f1b28..de2df0c 100644
--- a/drivers/gpu/drm/i915/i
From: Tom O'Rourke
Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.
v2: return void instead of ignored error code (Paulo)
Signed-off-by: Tom O'Rourke
---
drivers/gpu/drm/i915/intel_slpc.c | 28 +++
On 06/04/16 22:24, tom.orou...@intel.com wrote:
From: Tom O'Rourke
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v2: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
Thanks for doin
Hi,
after updating to 4.6-rcX (where X is 1 or 2, doesn't really matter) on
thinkpad x200s notebook with
00:02.0 VGA compatible controller: Intel Corporation Mobile 4 Series
Chipset Integrated Graphics Controller (rev 07)
closing and opening the lid freezes the computer completely (aft
From: Dave Gordon
DO NOT MERGE: This patch is being sent for CI testing only
v5:
Rebased
Signed-off-by: Dave Gordon
Acked-by: Tom O'Rourke
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/
In commit 7d23e3c3 ("drm/i915: Cleaning up intel_dp_hpd_pulse") some
much needed clean-up was done, but unfortunately part of the change
broke DP MST. The real issue was setting the connector state to
disconnected in the MST case, which is good, but the code then (after
a goto) checks if the conne
On Wed, Apr 06, 2016 at 03:49:55PM +0100, Tvrtko Ursulin wrote:
> +static const i915_reg_t gen9_shadowed_regs[] = {
> + RING_TAIL(RENDER_RING_BASE),
> + RING_TAIL(GEN6_BSD_RING_BASE),
> + RING_TAIL(VEBOX_RING_BASE),
> + RING_TAIL(BLT_RING_BASE),
It occurs to me that we will never u
Jiri Kosina writes:
> Hi,
>
> after updating to 4.6-rcX (where X is 1 or 2, doesn't really matter) on
> thinkpad x200s notebook with
>
> 00:02.0 VGA compatible controller: Intel Corporation Mobile 4 Series
> Chipset Integrated Graphics Controller (rev 07)
>
> closing and opening the lid f
On ke, 2016-04-06 at 13:33 +0100, Chris Wilson wrote:
> An oversight is that when we wrap the seqno, we need to reset the hw
> semaphore counters to 0. We did this for gen6 and gen7 and forgot to do
> so for the new implementation required for gen8 (legacy).
>
> Signed-off-by: Chris Wilson
> Cc:
On ke, 2016-04-06 at 13:33 +0100, Chris Wilson wrote:
> We reuse the same calculation into two macros, and I want to add a third
> user. Time to refactor.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.h | 11 +--
> 1 file ch
On ke, 2016-04-06 at 13:33 +0100, Chris Wilson wrote:
> Since we are setting engine local values that are tied to the hardware,
> move it out of i915_gem_init_seqno() into the intel_ring_init_seqno()
> backend, next to where the other hw semaphore registers are written.
>
> v2: Make the explanator
BXT Shared DPLL hw_state config uses values that are
different from other platforms. This patch prints the
right values for BXT through debugfs which helps during
debug.
Signed-off-by: Durgadoss R
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 --
1 file changed, 20 inserti
After the GPU reset and we discard all of the incomplete requests, mark
the GPU as having advanced to the last_submitted_seqno (as having
completed the requests and ready for fresh work). The impact of this is
negligible, as all the requests will be considered completed by this
point, it just bring
An oversight is that when we wrap the seqno, we need to reset the hw
semaphore counters to 0. We did this for gen6 and gen7 and forgot to do
so for the new implementation required for gen8 (legacy).
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
When we change the current seqno, we also need to remember to reset the
last_submitted_seqno for the engine.
Testcase: igt/gem_exec_whisper
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Reviewed-by: Mika Kuoppala
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel
We reuse the same calculation into two macros, and I want to add a third
user. Time to refactor.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_ringbuffer.h | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i
It's useful to look at the last seqno submitted on a particular engine
and compare it against the HWS value to check for irregularities.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Reviewed-by: Mika Kuoppala
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_deb
Having fixed the tracking of the engine's last_submitted_seqno, we can
now rely on it for detecting when the engine is idle (and not have to
touch the requests pointer).
Testcase: igt/gem_exec_whisper
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i9
Seal the request and mark it as pending execution before we submit it to
hardware. We assume that the actual submission cannot fail (that
guarantee is provided by preallocating space in the request for the
submission). As we may inspect this state without holding any locks
during hangcheck we shoul
We only use drm_i915_private within the function, so delete the unneeded
drm_device local.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
d
Since we are setting engine local values that are tied to the hardware,
move it out of i915_gem_init_seqno() into the intel_ring_init_seqno()
backend, next to where the other hw semaphore registers are written.
v2: Make the explanatory comment about always resetting the semaphores to
0 irrespectiv
Tom,
Might be worth taking the "Do Not Merge" message out.
Peter.
On Wed, 6 Apr 2016, tom.orou...@intel.com wrote:
From: Peter Antoine
This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.
DO NOT MERGE: This patch is expected as part of another
serie
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