Re: [Intel-gfx] Discuss GVT context hacks in i915

2016-02-15 Thread Wang, Zhi A
Pretty clear. Thanks for the ideas! They really inspire me. :) -Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Tuesday, February 16, 2016 1:20 AM To: Wang, Zhi A Cc: Vetter, Daniel; Joonas Lahtinen; Chris Wilson; Lv, Zhiyuan; Tian, Ke

Re: [Intel-gfx] [PATCH] drm/i915: Use SWF06 to figure out max cdclk for BDW

2016-02-15 Thread Thulasimani, Sivakumar
On 2/12/2016 8:36 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Bspec tells us that we can allow cdclk up to 540Mhz on BDW ULX, or up to 675 MHz on ULT, bu only if extra cooling is provided. There don't seem to be any strap or VBT bits to tells us this however. But I did spot

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Set invert bit for hpd based on VBT

2016-02-15 Thread Thulasimani, Sivakumar
On 2/12/2016 7:38 PM, Ville Syrjälä wrote: On Fri, Feb 12, 2016 at 06:39:44PM +0530, Shubhangi Shrivastava wrote: This patch sets the invert bit for hpd detection for each port based on VBT configuration. Since each AOB can be designed to depend on invert bit or not, it is expected if an AOB r

Re: [Intel-gfx] [PATCH V5] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

2016-02-15 Thread Thulasimani, Sivakumar
On 2/15/2016 6:46 PM, Ville Syrjälä wrote: On Fri, Feb 12, 2016 at 06:06:10PM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor Set cdclk based on the max required pixel clock based on VCO selected. Track boot vco instead of boot cdclk. The vco is now tracked at the atomic level a

Re: [Intel-gfx] 4.3.3 / skylake / dual graphics: multiple CSR errors at boot from i915 driver

2016-02-15 Thread Marc MERLIN
On Mon, Feb 15, 2016 at 11:07:23PM +0100, Daniel Vetter wrote: > On Mon, Feb 15, 2016 at 02:11:24PM +0800, Zhi Wang wrote: > > From SKL, i915 will try to load DMC firmware when system is starting up. You > > can find it from 01.org. Personally, it looks without the firmware, the > > system is also

Re: [Intel-gfx] Discuss GVT context hacks in i915

2016-02-15 Thread Tian, Kevin
> From: Wang, Zhi A > Sent: Tuesday, February 16, 2016 12:04 AM > > The better design idea is to reuse the data structures and helper > functions, but have new top-level entry functions for creating e.g. a > xengt lrc context. So e.g. have a lrc init function for xengt which > takes the setup stuf

Re: [Intel-gfx] Discuss GVT context hacks in i915

2016-02-15 Thread Zhi Wang
Hi: Thanks Kevin! See my comments below. On 02/16/16 11:11, Tian, Kevin wrote: From: Wang, Zhi A Sent: Tuesday, February 16, 2016 12:04 AM The better design idea is to reuse the data structures and helper functions, but have new top-level entry functions for creating e.g. a xengt lrc contex

[Intel-gfx] [PATCH 02/11] drm/i915: Constrain intel_context::global_id to 20 bits

2016-02-15 Thread sourab . gupta
From: Robert Bragg This will allow the ID to be given to the HW as the unique context identifier that's written, for example, to the context status buffer on preemption and included in reports written by the OA unit. Cc: Sourab Gupta Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_g

[Intel-gfx] [PATCH 00/11] Framework to collect gpu metrics using i915 perf infrastructure

2016-02-15 Thread sourab . gupta
From: Sourab Gupta This series adds framework for collection of gpu performance metrics associated with the command stream of a particular engine. These metrics include OA reports, timestamps, mmio metrics, etc. These metrics are are collected around batchbuffer boundaries. This work utilizes th

[Intel-gfx] [PATCH 01/11] drm/i915: Introduce global id for contexts

2016-02-15 Thread sourab . gupta
From: Sourab Gupta The current context user handles are specific to drm file instance. There are some usecases, which may require a global id for the contexts. For e.g. a system level GPU profiler tool may lean upon the global context ids to associate the performance snapshots with individual con

[Intel-gfx] [PATCH 03/11] drm/i915: return ctx->global_id from intel_execlists_ctx_id()

2016-02-15 Thread sourab . gupta
From: Robert Bragg The newly added intel_context::global_id is suitable (a globally unique 20 bit ID) for giving to the hardware as a unique context identifier. Compared to using the pinned address of a logical ring context these IDs are constant for the lifetime of a context whereas a context c

[Intel-gfx] [PATCH 04/11] drm/i915: Add ctx getparam ioctl parameter to retrieve ctx global id

2016-02-15 Thread sourab . gupta
From: Sourab Gupta This patch adds a new ctx getparam ioctl parameter, which can be used to retrieve ctx global_id for any particular ctx by userspace. This can be used by userspace to map the i915 perf samples with their particular ctx's, since those would be having ctx global_id's. Otherwise t

[Intel-gfx] [PATCH 10/11] drm/i915: Support opening multiple concurrent perf streams

2016-02-15 Thread sourab . gupta
From: Sourab Gupta This patch adds support for opening multiple concurrent perf streams for different gpu engines, while having the restriction to open only a single stream open for a particular gpu engine. This enables userspace client to open multiple streams, one per engine, at any time to cap

[Intel-gfx] [PATCH 07/11] drm/i915: Add support for having pid output with OA report

2016-02-15 Thread sourab . gupta
From: Sourab Gupta This patch introduces flags and adds support for having pid output with the OA reports generated through the RCS commands. When the stream is opened with pid sample type, the pid information is also captured through the command stream samples and forwarded along with the OA re

[Intel-gfx] [PATCH 05/11] drm/i915: Expose OA sample source to userspace

2016-02-15 Thread sourab . gupta
From: Sourab Gupta This patch exposes a new sample source field to userspace. This field can be populated to specify the origin of the OA report. For e.g. for internally triggerred reports (non MI_RPC reports), the RPT_ID field has bitfields for specifying the origin such as timer, or render ctx

[Intel-gfx] [PATCH 09/11] drm/i915: Extend i915 perf framework for collecting timestamps on all gpu engines

2016-02-15 Thread sourab . gupta
From: Sourab Gupta This patch extends the i915 perf framework to handle the perf sample collection for any given gpu engine. Particularly, the support for collecting timestamp sample type is added, which can be requested for any engine. The thing to note is that, still only a single stream insta

[Intel-gfx] [PATCH 06/11] drm/i915: Framework for capturing command stream based OA reports

2016-02-15 Thread sourab . gupta
From: Sourab Gupta This patch introduces a framework to enable OA counter reports associated with Render command stream. We can then associate the reports captured through this mechanism with their corresponding context id's. This can be further extended to associate any other metadata informatio

[Intel-gfx] [PATCH 08/11] drm/i915: Add support to add execbuffer tags to OA counter reports

2016-02-15 Thread sourab . gupta
From: Sourab Gupta This patch enables userspace to specify tags (per workload), provided via execbuffer ioctl, which could be added to OA reports, to help associate reports with the corresponding workloads. There may be multiple stages within a single context, from a userspace perspective. An ab

[Intel-gfx] [PATCH 11/11] drm/i915: Support for capturing MMIO register values

2016-02-15 Thread sourab . gupta
From: Sourab Gupta This patch adds support for capturing MMIO register values through i915 perf interface. The userspace can request upto 8 MMIO register values to be dumped. The addresses of these registers can be passed through the corresponding property 'value' field while opening the stream.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Hide GEM shutdown in i915_gem_fini

2016-02-15 Thread Patchwork
== Summary == Series 3296v1 drm/i915: Hide GEM shutdown in i915_gem_fini 2016-02-11T15:39:33.521840 http://patchwork.freedesktop.org/api/1.0/series/3296/revisions/1/mbox/ Applying: drm/i915: Hide GEM shutdown in i915_gem_fini Repository lacks necessary blobs to fall back on 3-way merge. Cannot fa

Re: [Intel-gfx] [PATCH v8 1/1] drm/i915/bxt: Check BIOS RC6 setup before enabling RC6

2016-02-15 Thread Tomi Sarvela
On Monday 15 February 2016 18:07:47 Daniel Vetter wrote: > On Mon, Feb 08, 2016 at 05:08:03PM +0200, Jani Nikula wrote: > > On Mon, 08 Feb 2016, Imre Deak wrote: > > >> > Thanks for the patch, I pushed it to -dinq. > > >> > > >> The rule is, we should wait for the CI results before pushing. > > >

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