On Wed, Jan 20, 2016 at 06:49:49PM +, Belgaumkar, Vinay wrote:
> Hi Chris,
> These tests were developed for testing buffered SVM(using userptr
> and soft pinning API). I think Dan wanted me to rename the tests to
> gem_softpin, since they were being checked in as tests which
> v
On Wed, Jan 20, 2016 at 05:31:00PM +, Dave Gordon wrote:
> On 20/01/16 07:49, Patchwork wrote:
> >== Summary ==
> >
> >Built on 7d26528d30b0d8119c858115b6e5e22deb74ec71 drm-intel-nightly:
> >2016y-01m-19d-19h-38m-52s UTC integration manifest
> >
> >Test gem_storedw_loop:
> > Subgroup b
On Tue, Jan 19, 2016 at 07:02:52PM +, Dave Gordon wrote:
> During startup, the driver creates a unique "intel_context" that will
> provide a home for orphan requests (i.e. those generated by the driver
> internally, not associated with user batchbuffers).
>
> However, one of the infelicities o
No functional changes.
While I'm here, let's also rename gem_uses_aliasing_ppgtt (since it's
being used to indicate if we are using ANY kind of ppgtt) and introduce
gem_uses_full_ppgtt to drop some unnecessary code from tests that were
previously calling getparam directly instead of using ioctl wra
On Tue, 19 Jan 2016, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Having this on stack triggers the -Wframe-larger-than=1024 and
> is not nice to put such big things on the kernel stack anyway.
>
> This required a little bit of refactoring to handle the new
> failure path from vlv_force_pll_o
Mika Kuoppala writes:
> Daniel Vetter writes:
>
>> We've had this since forever, and's randomly reporting issues and as
>> such causing piles&piles of CI noise. Mika is working on proper debug
>> infrastructure for this, and on fixing this properly.
>>
>> Meanwhile make CI more useful for everyo
Daniel Vetter writes:
> On Wed, Jan 20, 2016 at 12:32:23PM +0200, Mika Kuoppala wrote:
>> The capability to detect unclaimed register access was
>> recently introduced for vlv/chv platforms. Apparently
>> there are plenty of unclaimed access on these platforms,
>> resulting in new dmesg warns. Bu
From: Tvrtko Ursulin
Will simplify the following fix and sounds logical.
v2: Add some whitespace to separate logic better. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
Cc: Chris Wilson
Cc: Nick Hoath
---
drivers/gpu/drm/i915/intel_lrc.c | 4
1 file changed, 4
From: Tvrtko Ursulin
Previously intel_lr_context_(un)pin were operating on requests
which is in conflict with their names.
If we make them take a context and an engine, it makes the names
make more sense and it also makes future fixes possible.
v2: Rebase for default_context/kernel_context chan
From: Tvrtko Ursulin
In GuC mode LRC pinning lifetime depends exclusively on the
request liftime. Since that is terminated by the seqno update
that opens up a race condition between GPU finishing writing
out the context image and the driver unpinning the LRC.
To extend the LRC lifetime we will e
On Thu, Jan 21, 2016 at 10:27:26AM +0100, Michał Winiarski wrote:
> No functional changes.
> While I'm here, let's also rename gem_uses_aliasing_ppgtt (since it's
> being used to indicate if we are using ANY kind of ppgtt) and introduce
> gem_uses_full_ppgtt to drop some unnecessary code from tests
Patchwork writes:
> == Summary ==
>
> Built on e9545b0b60b73d8be3d41048af5b8f2c1e2fc4c1 drm-intel-nightly:
> 2016y-01m-20d-13h-55m-37s UTC integration manifest
>
> Test gem_storedw_loop:
> Subgroup basic-render:
> dmesg-warn -> PASS (bdw-ultra) UNSTABLE
> Test gem_s
On Fri, Jan 15, 2016 at 03:12:50PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> At the moment execbuf ring selection is fully coupled to
> internal ring ids which is not a good thing on its own.
>
> This dependency is also spread between two source files and
> not spelled out at eithe
On Fri, Jan 15, 2016 at 04:51:46PM +, Chris Wilson wrote:
> Tvrtko was looking through the execbuffer-ioctl and noticed that the
> uABI was tightly coupled to our internal engine identifiers. Close
> inspection also revealed that we leak those internal engine identifiers
> through the busy-ioct
== Summary ==
Built on c783b5011894af49992f2095cb2848b6cf8ebc57 drm-intel-nightly:
2016y-01m-20d-10h-12m-03s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (bdw-ultra) UNSTABLE
Test gem_sync:
Subgroup basic-render:
On Thu, Jan 21, 2016 at 10:10:42AM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In GuC mode LRC pinning lifetime depends exclusively on the
> request liftime. Since that is terminated by the seqno update
> that opens up a race condition between GPU finishing writing
> out the context i
On 15/01/16 17:20, Patchwork wrote:
== Summary ==
Built on 615fbad7f4cea73b1a8eccdcc942c8ca1a708dab drm-intel-nightly:
2016y-01m-15d-09h-46m-32s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
On 15/01/16 11:24, Patchwork wrote:
== Summary ==
Built on 615fbad7f4cea73b1a8eccdcc942c8ca1a708dab drm-intel-nightly:
2016y-01m-15d-09h-46m-32s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
On Thu, Jan 21, 2016 at 11:02:50AM +, Chris Wilson wrote:
> intel_gpu_reset();
> for_each_engine() unpin(engine->last_context);
> unpin(dev_priv->default_context);
>
> After a few more passes, we should be able to call the reset and cleanup
> functions higher up (as part of the stopping the GP
Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> Extract all the code that checks if the FBC configuration is valid to
> its own function, making __intel_fbc_update() much simpler.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_fbc.c | 92
> ++-
On 13/01/2016 10:06, Arun Siluvery wrote:
Required for WaEnablePreemptionGranularityControlByUMD:skl,bxt
Signed-off-by: Arun Siluvery
Reviewed-by: Nick Hoath
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++
2 files changed, 8 inser
On to, 2016-01-14 at 18:50 +0200, Imre Deak wrote:
> On la, 2015-12-19 at 09:58 +, Chris Wilson wrote:
> > Once all the preparations are complete, we are ready to write the
> > modesetting to the hardware. During this phase, we will be making
> > lots
> > of HW register access, so take a top le
On 13/01/2016 10:06, Arun Siluvery wrote:
Required for WaAllowUMDToModifyHDCChicken1:skl,bxt
Signed-off-by: Arun Siluvery
Reviewed-by: Nick Hoath
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
2 files changed, 7 insertions(+)
dif
On 13/01/2016 10:06, Arun Siluvery wrote:
Required for,
WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt
WaDisableObjectLevelPreemptionForInstancedDraw:bxt
WaDisableObjectLevelPreemtionForInstanceId:bxt
According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares
Em Qui, 2016-01-21 às 08:35 +0530, Thulasimani, Sivakumar escreveu:
>
> On 1/20/2016 10:32 PM, Zanoni, Paulo R wrote:
> > Em Sex, 2015-12-11 às 08:39 -0800, Rodrigo Vivi escreveu:
> > > Unfortunately we don't know all panels and platforms out there
> > > and we
> > > found internal prototypes with
On Wed, Jan 20, 2016 at 09:08:50PM +, Chris Wilson wrote:
> On Wed, Jan 20, 2016 at 09:05:35PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Instead of repopulatin the rotation_info struct for the fb every time
> > we try to use the fb, we can just populate it on
Em Qui, 2016-01-21 às 12:35 +0100, Maarten Lankhorst escreveu:
> Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> > Extract all the code that checks if the FBC configuration is valid
> > to
> > its own function, making __intel_fbc_update() much simpler.
> >
> > Signed-off-by: Paulo Zanoni
> > ---
> >
On Thu, Jan 21, 2016 at 02:06:27PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 20, 2016 at 09:08:50PM +, Chris Wilson wrote:
> > On Wed, Jan 20, 2016 at 09:05:35PM +0200, ville.syrj...@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä
> > >
> > > Instead of repopulatin the rotation_info str
From: Tvrtko Ursulin
Will enable cleaner implementation of a following fix and
easier code unification in the future.
Idea and code by Chris Wilson.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 25 +++--
1 file changed, 11 i
From: Tvrtko Ursulin
Previously intel_lr_context_(un)pin were operating on requests
which is in conflict with their names.
If we make them take a context and an engine, it makes the names
make more sense and it also makes future fixes possible.
v2: Rebase for default_context/kernel_context chan
From: Tvrtko Ursulin
Will simplify the following fix and sounds logical.
v2: Add some whitespace to separate logic better. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
Cc: Chris Wilson
Cc: Nick Hoath
---
drivers/gpu/drm/i915/intel_lrc.c | 4
1 file changed, 4
From: Tvrtko Ursulin
In GuC mode LRC pinning lifetime depends exclusively on the
request liftime. Since that is terminated by the seqno update
that opens up a race condition between GPU finishing writing
out the context image and the driver unpinning the LRC.
To extend the LRC lifetime we will e
On 13/01/2016 10:06, Arun Siluvery wrote:
Required for WaDisableLSQCROPERFforOCL:bxt
According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares the same GT these are extended for A1 as well.
Signed-off-by: Arun Siluvery
Reviewed-by: Nick Hoath
---
drivers/g
On 13/01/2016 10:06, Arun Siluvery wrote:
Required for WaDisableLSQCROPERFforOCL:skl
Signed-off-by: Arun Siluvery
Reviewed-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drive
On 1/20/2016 5:06 AM, Ville Syrjälä wrote:
On Wed, Jan 20, 2016 at 03:29:00PM +0530, Kumar, Shobhit wrote:
On 01/20/2016 02:30 PM, Daniel Vetter wrote:
On Tue, Jan 19, 2016 at 02:37:55PM -0800, Kumar, Abhay wrote:
On 1/12/2016 5:57 PM, Kumar, Abhay wrote:
From: Abhay Kumar
Make resume/on
On 1/21/2016 5:26 PM, Zanoni, Paulo R wrote:
Em Qui, 2016-01-21 às 08:35 +0530, Thulasimani, Sivakumar escreveu:
On 1/20/2016 10:32 PM, Zanoni, Paulo R wrote:
Em Sex, 2015-12-11 às 08:39 -0800, Rodrigo Vivi escreveu:
Unfortunately we don't know all panels and platforms out there
and we
found
On Thu, Jan 21, 2016 at 12:14:10PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> In GuC mode LRC pinning lifetime depends exclusively on the
> request liftime. Since that is terminated by the seqno update
> that opens up a race condition between GPU finishing writing
> out the context i
Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> The early return inside __intel_fbc_update does not completely check
> all the parameters that affect the FBC register values. For example,
> we currently lack looking at crtc->adjusted_y (for the fence Y offset)
> and all the parameters that affect the
Em Qui, 2016-01-21 às 13:48 +0100, Maarten Lankhorst escreveu:
> Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> > The early return inside __intel_fbc_update does not completely
> > check
> > all the parameters that affect the FBC register values. For
> > example,
> > we currently lack looking at crtc
Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> We unconditionally disable/update FBC even during the page flip
> IOCTLs, and an unconditional disable/update at every atomic commit
> touching the primary plane shouldn't impact PC state residency
> noticeably. Besides, the code that checks for rotation
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly:
2016y-01m-21d-11h-02m-42s UTC integration manifest
bdw-nuci7total:140 pass:131 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultratotal:143 pass:137 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2
Em Qua, 2016-01-20 às 18:26 -0800, tom.orou...@intel.com escreveu:
> From: Sagar Arun Kamble
>
> GuC SLPC need to be sent data related to Active pipes, refresh rates,
> widi pipes, fullscreen pipes related via host to GuC display mode
> change event.
> This patch defines the event and implements
Em Qui, 2016-01-21 às 14:04 +0100, Maarten Lankhorst escreveu:
> Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> > We unconditionally disable/update FBC even during the page flip
> > IOCTLs, and an unconditional disable/update at every atomic commit
> > touching the primary plane shouldn't impact PC s
Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> Older FBC platforms have this restriction where FBC can't be enabled
> if multiple pipes are enabled. In the current code, we disable FBC
> before the second pipe becomes visible.
>
> One of the problems with this code is that the current
> multiple_pipe
Op 21-01-16 om 14:27 schreef Zanoni, Paulo R:
> Em Qui, 2016-01-21 às 14:04 +0100, Maarten Lankhorst escreveu:
>> Op 19-01-16 om 14:35 schreef Paulo Zanoni:
>>> We unconditionally disable/update FBC even during the page flip
>>> IOCTLs, and an unconditional disable/update at every atomic commit
>>>
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly:
2016y-01m-21d-11h-02m-42s UTC integration manifest
bdw-nuci7total:140 pass:131 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultratotal:143 pass:137 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly:
2016y-01m-21d-11h-02m-42s UTC integration manifest
Test drv_getparams_basic:
Subgroup basic-eu-total:
pass -> DMESG-FAIL (skl-i5k-2)
Subgroup basic-subslice-total:
On 21/01/16 12:32, Chris Wilson wrote:
On Thu, Jan 21, 2016 at 12:14:10PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
In GuC mode LRC pinning lifetime depends exclusively on the
request liftime. Since that is terminated by the seqno update
that opens up a race condition between GPU fini
Resending all patches as told by Daniel because I didn't use correct
message-id while replying updated version of Patch1 before which means
patchwork won't pickup and we won't have CI results. Previous updates
regarding Patch1 are available at https://patchwork.freedesktop.org/patch/70527/
Some of
Required for WaEnablePreemptionGranularityControlByUMD:skl,bxt
Reviewed-by: Nick Hoath
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_re
Required for WaDisableLSQCROPERFforOCL:bxt
According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares the same GT these are extended for A1 as well.
Reviewed-by: Nick Hoath
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file
Required for WaAllowUMDToModifyHDCChicken1:skl,bxt
Reviewed-by: Nick Hoath
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
Some of the HW registers are privileged and cannot be written to from
non-privileged batch buffers coming from userspace unless they are added to
the HW whitelist. This whitelist is maintained by HW and it is different from
SW whitelist. Userspace need write access to them to implement preemption
r
This is mainly required for preemption.
Cc: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e91fb70..f26f274 1006
Per context preemption granularity control is only available from SKL:E0+
Cc: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i
Required for WaDisableLSQCROPERFforOCL:skl
Reviewed-by: Nick Hoath
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1decaf1..
Required for,
WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt
WaDisableObjectLevelPreemptionForInstancedDraw:bxt
WaDisableObjectLevelPreemtionForInstanceId:bxt
According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares the same GT these are extended for A1 as wel
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly:
2016y-01m-21d-11h-02m-42s UTC integration manifest
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (ilk-hp8440p)
bdw-nuci7total:140 pass:131 dwarn:0 dfail:
On Thu, Jan 21, 2016 at 01:51:30PM +, Tvrtko Ursulin wrote:
> But I can't really figure where would you put this poisoning? You
> could put something in in exec list mode after context complete and
> check it before it is used next time,
I was thinking just in context-free. Move the pages to a
Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> Instead of waiting for 50ms, just wait until the next vblank, since
> it's the minimum requirement. The whole infrastructure of FBC is based
> on vblanks, so waiting for X vblanks instead of X milliseconds sounds
> like the correct way to go. Besides, 50
Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> Hi
>
> Here's yet another patch series randomly modifying the FBC code. We
> start by refactoring things in order to fix the locking problems, then
> fix a few other smaller problems and apply some polishing.
>
> Just to keep the tradition of the past 10
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly:
2016y-01m-21d-11h-02m-42s UTC integration manifest
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (ilk-hp8440p)
bdw-nuci7total:140 pass:131 dwarn:0 dfail:
On 21/01/2016 14:25, Patchwork wrote:
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly:
2016y-01m-21d-11h-02m-42s UTC integration manifest
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (ilk-hp8440p)
bdw-nuci7
On 13/01/2016 10:06, Arun Siluvery wrote:
Per context preemption granularity control is only available from SKL:E0+
Cc: Dave Gordon
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++
2 files changed, 1
On 21/01/2016 14:00, Arun Siluvery wrote:
Per context preemption granularity control is only available from SKL:E0+
Cc: Dave Gordon
Signed-off-by: Arun Siluvery
Reviewed-by: Nick Hoath
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++
On 21/01/2016 14:00, Arun Siluvery wrote:
This is mainly required for preemption.
Cc: Dave Gordon
Signed-off-by: Arun Siluvery
Reviewed-by: Nick Hoath
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuff
On 21/01/2016 14:00, Arun Siluvery wrote:
Required for,
WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt
WaDisableObjectLevelPreemptionForInstancedDraw:bxt
WaDisableObjectLevelPreemtionForInstanceId:bxt
According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares
Op 14-01-16 om 13:07 schreef Chris Wilson:
> On Thu, Jan 14, 2016 at 11:47:17AM +, John Harrison wrote:
>> On 13/01/2016 18:43, Chris Wilson wrote:
>>> Use the upper s32 for the output, so again you are not overwriting user
>>> state without good reason.
>>>
>> Makes sense. Will do.
> It would
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.c| 3 +
drivers/gpu/drm/i915/i915_reg.h| 40 +++
drivers/gpu/drm/i915/intel_color.c | 139 -
3 files changed, 180 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 63c4283..46143f8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i9
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_reg.h | 40 +++-
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a98889..63c4283 100644
--- a/drivers/gpu/drm
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/intel_color.c | 174 +++
drivers/gpu/drm/i915/intel_display.c | 163 +++-
drivers/gpu/drm/i915/intel_drv.h | 10 ++
4 files ch
Hi,
This serie introduces pipe level color management through a set of properties
attached to the CRTC. It also provides an implementation for some Intel
platforms.
This serie is based of a previous set of patches by Shashank Sharma and takes
into account of the comments by Daniel Stone & Daniel
Hi,
I got this message in reply to this patch
(https://patchwork.freedesktop.org/patch/60736/).
It looks like most of the warnings are related to 'PWM1 enabled' warnings that
happen when the hardware is going into some power management state and
BLM_PWM_ENABLE and/or BLM_PCH_PWM_ENABLE are e
On Thu, Jan 21, 2016 at 03:47:40PM +0100, Maarten Lankhorst wrote:
> Op 14-01-16 om 13:07 schreef Chris Wilson:
> > On Thu, Jan 14, 2016 at 11:47:17AM +, John Harrison wrote:
> >> On 13/01/2016 18:43, Chris Wilson wrote:
> >>> Use the upper s32 for the output, so again you are not overwriting u
Signed-off-by: Lionel Landwerlin
---
Documentation/DocBook/gpu.tmpl | 48 +
drivers/gpu/drm/drm_atomic.c| 102 +++-
drivers/gpu/drm/drm_atomic_helper.c | 10
drivers/gpu/drm/drm_crtc.c | 35 +
drivers/gpu/dr
Signed-off-by: Lionel Landwerlin
---
Documentation/DocBook/gpu.tmpl | 12 +-
drivers/gpu/drm/i915/i915_drv.c | 24 ++-
drivers/gpu/drm/i915/i915_drv.h | 9 +
drivers/gpu/drm/i915/i915_reg.h | 22 +++
drivers/gpu/drm/i915/intel_color.c | 345
Signed-off-by: Lionel Landwerlin
---
lib/igt_kms.c | 1 +
lib/igt_kms.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 497118a..f5eef82 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1004,6 +1004,7 @@ void igt_display_init(igt_display_t *display, int
Signed-off-by: Lionel Landwerlin
---
lib/igt_kms.c | 74 +++
lib/igt_kms.h | 17 +-
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index f5eef82..984d2ea 100644
--- a/lib/igt_kms.c
++
This is a helper to draw a gradient between 2 colors.
Signed-off-by: Lionel Landwerlin
---
lib/igt_fb.c | 34 ++
lib/igt_fb.h | 3 +++
2 files changed, 37 insertions(+)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index c985824..2d5cf7a 100644
--- a/lib/igt_fb.c
+++
This test enables testing of :
* degamma LUTs
* csc matrix
* gamma LUTs
* legacy gamma LUTs
Signed-off-by: Lionel Landwerlin
---
tests/Makefile.sources | 1 +
tests/kms_pipe_color.c | 986 +
2 files changed, 987 insertions(+)
Hi,
This series enables testing pipe level color management using kernel patches
from this serie :
http://lists.freedesktop.org/archives/intel-gfx/2016-January/085922.html
Most of the tests use pipe CRCs to check the results by comparing the output
with the expected output drawn using cairo.
Ch
Hi Lionel,
On 21 January 2016 at 15:03, Lionel Landwerlin
wrote:
> + /* Workaround : Do not read or write the pipe palette/gamma data while
> +* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS
> enabled.
> +*/
> + if (IS_HASWELL(dev) && intel_crtc->config
On Thu, Jan 21, 2016 at 02:00:39PM +, Arun Siluvery wrote:
> Resending all patches as told by Daniel because I didn't use correct
> message-id while replying updated version of Patch1 before which means
> patchwork won't pickup and we won't have CI results. Previous updates
> regarding Patch1 a
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly:
2016y-01m-21d-11h-02m-42s UTC integration manifest
Test drv_module_reload_basic:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> DMESG-WARN (skl-i5k-2)
pass
On 21/01/2016 15:17, Chris Wilson wrote:
On Thu, Jan 21, 2016 at 02:00:39PM +, Arun Siluvery wrote:
Resending all patches as told by Daniel because I didn't use correct
message-id while replying updated version of Patch1 before which means
patchwork won't pickup and we won't have CI results.
Dave Gordon writes:
> On 11/01/16 09:16, Chris Wilson wrote:
>> In order to ensure seqno/irq coherency, we current read a ring register.
>> We are not sure quite how it works, only that is does. Experiments show
>> that e.g. doing a clflush(seqno) instead is not sufficient, but we can
>> remove t
Em Qui, 2016-01-21 às 15:17 +0100, Maarten Lankhorst escreveu:
> Op 19-01-16 om 14:35 schreef Paulo Zanoni:
> > Instead of waiting for 50ms, just wait until the next vblank, since
> > it's the minimum requirement. The whole infrastructure of FBC is
> > based
> > on vblanks, so waiting for X vblanks
On Thu, Jan 21, 2016 at 04:07:22PM +, Arun Siluvery wrote:
> On 21/01/2016 15:17, Chris Wilson wrote:
> >On Thu, Jan 21, 2016 at 02:00:39PM +, Arun Siluvery wrote:
> >>Resending all patches as told by Daniel because I didn't use correct
> >>message-id while replying updated version of Patch
The generic interval tree we use to speed up range invalidation is an
augmented rbtree that can report all overlapping intervals for a given
range. Therefore we do not need to degrade to a linear list if we find
overlapping objects. Oops.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michał
On 21/01/2016 16:56, Chris Wilson wrote:
On Thu, Jan 21, 2016 at 04:07:22PM +, Arun Siluvery wrote:
On 21/01/2016 15:17, Chris Wilson wrote:
On Thu, Jan 21, 2016 at 02:00:39PM +, Arun Siluvery wrote:
Resending all patches as told by Daniel because I didn't use correct
message-id while
This commits adds the Broxton target to the GuC loader
Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/g
This set of patches will enable the GuC loading for BXT.
There is also a fix that is required for GuC submission with the BXT GuC
to make it reliable.
v2: Remove patch that is to be added with a later patchset.
remove erroneous write (merge error) - Jeff McGee
Peter Antoine (2):
drm/i915:
This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.
Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_guc_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
2 files cha
On Fri, Jan 15, 2016 at 11:06:24AM +0200, Marius Vlad wrote:
> So far, we had only COMMIT_UNIVERSAL and COMMIT_LEGACY, using
> drmModeSetPlane()/drmSetCrtc(). This patch adds COMMIT_ATOMIC
> to igt_display_commit2() that makes use of drmModeAtomicCommit().
>
> Signed-off-by: Marius Vlad
Hmm, thi
On Thu, Jan 21, 2016 at 03:03:49PM +, Lionel Landwerlin wrote:
...
> diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
> index 351e801..d2f682c 100644
> --- a/Documentation/DocBook/gpu.tmpl
> +++ b/Documentation/DocBook/gpu.tmpl
> @@ -2092,6 +2092,54 @@ void intel_crt
Existing code did a kunmap() on the wrong page, and didn't account for the
fact that the HWSP and the default context are different offsets within the
same GEM object.
This patch improves symmetry by creating lrc_teardown_hardware_status_page()
to complement lrc_setup_hardware_status_page(), makin
Also includes Nick Hoath's patch to swap context/engine teardown.
In-Reply-To:
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1. add call to i915_gem_context_fini() to deallocate the default
context(s) if the call to init_rings() fails, so that we don't
leak the context in that situation.
2. remove useless code in intel_logical_ring_cleanup(), presumably
copypasted from legacy ringbuffer version at creation.
Si
1. Fix intel_cleanup_ring_buffer() to handle the error cleanup
case where the ringbuffer has been allocated but map-and-pin
failed. Unpin it iff it's previously been mapped-and-pinned.
2. Fix the error path in intel_init_ring_buffer(), which already
called intel_destroy_ringbuffer_obj(),
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