This patch adds support for eDP backlight control using DPCD registers to
backlight hooks in intel_panel.
It checks for backlight control over AUX channel capability and sets up
function pointers to get and set the backlight brightness level if
supported.
v2: Moved backlight functions from intel_
On Tue, Jan 12, 2016 at 05:59:46PM +0200, Imre Deak wrote:
> On ti, 2016-01-12 at 16:35 +0100, Daniel Vetter wrote:
> > On Tue, Jan 12, 2016 at 02:21:51PM +, John Harrison wrote:
> > > On 12/01/2016 14:04, Daniel Vetter wrote:
> > > > On Tue, Jan 12, 2016 at 11:50:34AM +, John Harrison wrot
On 12 January 2016 at 15:59, Yetunde Adebisi wrote:
> + memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
gcc should've warned you about this; you're memsetting too small a size.
Cheers,
Daniel
___
Intel-gfx mailing list
Intel-gf
On Mon, Jan 11, 2016 at 09:51:38AM +, Tvrtko Ursulin wrote:
>
> On 11/01/16 08:43, Daniel Vetter wrote:
> > On Fri, Jan 08, 2016 at 01:29:14PM +, Tvrtko Ursulin wrote:
> >>
> >> On 08/01/16 11:29, Tvrtko Ursulin wrote:
> >>> From: Tvrtko Ursulin
> >>>
> >>> Purpose is to catch places whic
== Summary ==
Built on 37f6c2ae666fbba9eff4355115252b8b0fd43050 drm-intel-nightly:
2016y-01m-12d-14h-25m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
dmesg-warn -> PASS (bdw-
On Mon, Jan 11, 2016 at 10:13:53AM -, Patchwork wrote:
> == Summary ==
>
> Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly:
> 2016y-01m-11d-07h-30m-16s UTC integration manifest
>
> Test gem_storedw_loop:
> Subgroup basic-render:
> pass -> DME
On Mon, Jan 11, 2016 at 11:20:21AM -, Patchwork wrote:
> == Summary ==
>
> HEAD is now at ff88655 drm-intel-nightly: 2016y-01m-11d-07h-30m-16s UTC
> integration manifest
> Applying: drm: kerneldoc for drm_fops.c
> Repository lacks necessary blobs to fall back on 3-way merge.
> Cannot fall bac
On Mon, Jan 11, 2016 at 02:50:28PM +0200, Mika Kuoppala wrote:
> Patchwork writes:
>
> > == Summary ==
> >
> > Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly:
> > 2016y-01m-11d-07h-30m-16s UTC integration manifest
> >
> > Test gem_storedw_loop:
> > Subgroup basic-ren
On 12/01/16 13:11, Chris Wilson wrote:
On Tue, Jan 12, 2016 at 12:54:25PM +, Tvrtko Ursulin wrote:
On 12/01/16 12:12, Chris Wilson wrote:
On Tue, Jan 12, 2016 at 11:56:11AM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
LRC lifetime is well defined so we can cache the page pointing
t
On Tue, Jan 12, 2016 at 05:28:24PM +0200, Mika Kuoppala wrote:
> The most common thing on normal operation is ring tail
> pointer update. Put it first in the shadow register list for
> gen8, like we do with gen9.
With execlists it is not. Also BSD2?
Do you have the complete list of shadowed regs
== Summary ==
Built on 37f6c2ae666fbba9eff4355115252b8b0fd43050 drm-intel-nightly:
2016y-01m-12d-14h-25m-44s UTC integration manifest
Test drv_module_reload_basic:
Subgroup none:
dmesg-warn -> PASS (skl-i5k-2)
dmesg-warn -> PASS (skl-i7k-2)
Tes
On Mon, Jan 11, 2016 at 11:53:53AM -, Patchwork wrote:
> == Summary ==
>
> Built on ff88655b3a5467bbc3be8c67d3e05ebf182557d3 drm-intel-nightly:
> 2016y-01m-11d-07h-30m-16s UTC integration manifest
>
> Test gem_storedw_loop:
> Subgroup basic-render:
> dmesg-warn -> PAS
Op 12-01-16 om 17:19 schreef Daniel Vetter:
> On Mon, Jan 11, 2016 at 09:51:38AM +, Tvrtko Ursulin wrote:
>> On 11/01/16 08:43, Daniel Vetter wrote:
>>> On Fri, Jan 08, 2016 at 01:29:14PM +, Tvrtko Ursulin wrote:
On 08/01/16 11:29, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
On Tue, Jan 12, 2016 at 04:55:24PM +0100, Daniel Vetter wrote:
> On Tue, Jan 12, 2016 at 05:28:16PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > commit 10afa0b65fe2 ("drm/i915: Reject >9 ddi translation entried if port
> > != A/E on SKL")
> > added sanity checks to
On Tue, Jan 12, 2016 at 05:11:00PM +0100, Daniel Vetter wrote:
> On Tue, Jan 12, 2016 at 05:59:46PM +0200, Imre Deak wrote:
> > On ti, 2016-01-12 at 16:35 +0100, Daniel Vetter wrote:
> > > On Tue, Jan 12, 2016 at 02:21:51PM +, John Harrison wrote:
> > > > On 12/01/2016 14:04, Daniel Vetter wrot
On 01/12/2016 05:21 AM, Ville Syrjälä wrote:
On Mon, Jan 11, 2016 at 01:52:17PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Add reboot notifier for all platforms. This guarantees T12 delay
compliance during reboot cycles when pre-os enables the panel within
500ms.
Signed-off-b
On 11/01/16 09:17, Chris Wilson wrote:
If is simpler and leads to more readable code through the callstack if
the allocation returns the allocated struct through the return value.
The importance of this is that it no longer looks like we accidentally
allocate requests as side-effect of calling c
On Tue, Jan 12, 2016 at 04:04:06PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> One bugfix and a few tidy-ups:
>
> * Pipe fault logging was broken on Gen9+.
> * Removed some unnecessary local variables.
> * Removed unnecessary initializers.
> * Decreased pipe iir block indentation
On Tue, Jan 12, 2016 at 04:04:07PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Tidy quite long interrupt service routine by factoring out
> the display part.
>
> This simplifies the exit path a little bit, makes the code
> a bit more readable, and potentialy makes code reuse in the
>
On Tue, Jan 12, 2016 at 03:52:36PM +, Dave Gordon wrote:
> On 11/01/16 15:04, Tvrtko Ursulin wrote:
> >
> >On 11/01/16 14:36, Chris Wilson wrote:
> >>On Mon, Jan 11, 2016 at 02:08:40PM +, Tvrtko Ursulin wrote:
> >>>From: Tvrtko Ursulin
> >>>
> >>>No need to call ktime_get_raw_ns twice per
On Tue, 12 Jan 2016, Daniel Stone wrote:
> On 12 January 2016 at 15:59, Yetunde Adebisi
> wrote:
>> + memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
>
> gcc should've warned you about this; you're memsetting too small a size.
Really? I think it's fine.
BR,
Jani.
--
Hi Shobhit,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.4 next-20160112]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Shobhit-Kumar/LPSS-PWM-support-for
On 12 January 2016 at 17:18, Jani Nikula wrote:
> On Tue, 12 Jan 2016, Daniel Stone wrote:
>> On 12 January 2016 at 15:59, Yetunde Adebisi
>> wrote:
>>> + memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
>>
>> gcc should've warned you about this; you're memsetting too sm
On 11/01/16 09:17, Chris Wilson wrote:
Both perform the same actions with more or less indirection, so just
unify the code.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c| 2 +-
drivers/gpu/drm/i915/i915_gem_context.c| 8 +-
drivers/gpu/drm/i915/i915_gem
On Tue, 12 Jan 2016, Daniel Stone wrote:
> On 12 January 2016 at 17:18, Jani Nikula wrote:
>> On Tue, 12 Jan 2016, Daniel Stone wrote:
>>> On 12 January 2016 at 15:59, Yetunde Adebisi
>>> wrote:
+ memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
>>>
>>> gcc should'
From: Tvrtko Ursulin
Chris Wilson noticed the "bds2" typo.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4a6ba0a4
From: Tvrtko Ursulin
Majority of them was duplicated code and only render ring
currently overrides some of them. We can save some lines of
code and also take away the confusion on why bsd2 did not
do the seqno coherency workaround. (VCS2 ring does not exist
on platforms where workaround is needed
From: Tvrtko Ursulin
Identically to vfuncs interrupt mask initialization can also be
compacted for more readable code.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 33 +
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/driv
On 12/01/16 17:12, Chris Wilson wrote:
On Tue, Jan 12, 2016 at 04:04:06PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
One bugfix and a few tidy-ups:
* Pipe fault logging was broken on Gen9+.
* Removed some unnecessary local variables.
* Removed unnecessary initializers.
* Decre
On Tue, Jan 12, 2016 at 11:06:17AM +, Graham Whaley wrote:
> On Tue, 2016-01-12 at 09:34 +0100, Daniel Vetter wrote:
> > On Mon, Jan 11, 2016 at 06:12:12PM -0700, Jonathan Corbet wrote:
> > > On Sat, 12 Dec 2015 12:13:45 +0100
> > > Daniel Vetter wrote:
> > >
> > > > I just figured there's no
On 11/01/16 09:16, Chris Wilson wrote:
Currently there is a #define to enable extra BUG_ON for debugging
requests and associated activities. I want to expand its use to cover
all of GEM internals (so that we can saturate the code with asserts).
We can add a Kconfig option to make it easier to ena
On Tue, Dec 01, 2015 at 05:43:33PM +0200, Jani Nikula wrote:
> On Tue, 01 Dec 2015, Ville Syrjälä wrote:
> > On Tue, Dec 01, 2015 at 02:47:41PM +0200, Jani Nikula wrote:
> >> On Mon, 30 Nov 2015, ville.syrj...@linux.intel.com wrote:
> >> > From: Ville Syrjälä
> >> >
> >> > Generalize rawclk handl
== Summary ==
Built on 9a47f23e3744929b9b222cb750994723fff0e5ee drm-intel-nightly:
2016y-01m-12d-16h-55m-40s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
pass -> DMESG-WARN (bdw-
On 11/01/16 09:16, Chris Wilson wrote:
As we add the VMA to the request early, it may be cancelled during
execbuf reservation. This will leave the context object pointing to a
dangling request; i915_wait_request() simply skips the wait and so we
may unbind the object whilst it is still active.
From: Ville Syrjälä
In preparation for handling more than X tiling, pass the fb modifier to
gen4_compute_page_offset() instead of the obj->tiling_mode.
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
drivers/gpu/drm/i915/inte
From: Ville Syrjälä
Pull the tile width calculations from intel_fb_stride_alignment() into a
new function intel_tile_width().
Also take the opportunity to pass aroun dev_priv instead of dev to
intel_fb_stride_alignment().
v2: Reorder argumnents to be more consistent with other functions
Cha
From: Ville Syrjälä
Here's a repost of some already reviewed patches from my larger fb
offsets[] series [1] from last year, for the sake of the CI system.
[1] http://lists.freedesktop.org/archives/intel-gfx/2015-October/078050.html
Ville Syrjälä (7):
drm/i915: Pass modifier instead of tiling
From: Ville Syrjälä
Make intel_gen4_compute_page_offset() ready for other tiling formats
besied X-tile by getting the tile dimensions through
intel_tile_{size,width,height}().
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 15 ++-
From: Ville Syrjälä
Pull the code to determine the surface alignment for both linear and
tiled surfaces into a separate function intel_surf_alignment(). This
will be used not only for the vma alignment but actually aligning
the plane SURF once SKL+ starts using intel_compute_page_offset()
(since
From: Ville Syrjälä
Use the actual tile size as to compute stuff in
intel_fill_fb_ggtt_view() instead of assuming it's PAGE_SIZE. I suppose
it doesn't matter since we don't use the results on gen2 platforms
where the tile size is 2k.
v2: Update due to CbCr plane
Signed-off-by: Ville Syrjälä
Re
From: Ville Syrjälä
Since intel_gen4_compute_page_offset() can now handle tiling formats
all the way down to gen2, rename it to intel_compute_tile_offset().
Not that we actually use it on gen2/3 since there's no DSPSURF etc.
registers which would take a page aligned address.
v2: s/page/tile/ (Da
From: Ville Syrjälä
I find more usual to think about tile widths than heights, so changing
the intel_tile_height() to calculate the tile height as
tile_size/tile_width is easier than the opposite to the poor brain.
v2: Reorder arguments for consistency
Constify dev_priv arguments
Signed-off
On 11/01/16 09:17, Chris Wilson wrote:
Rather than recomputing whether semaphores are enabled, we can do that
computation once during early initialisation as the i915.semaphores
module parameter is now read-only.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
On Tue, Jan 12, 2016 at 05:32:34PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Majority of them was duplicated code and only render ring
> currently overrides some of them. We can save some lines of
> code and also take away the confusion on why bsd2 did not
> do the seqno coherency w
On Tue, Jan 12, 2016 at 03:07:03PM +0100, Daniel Vetter wrote:
> On Tue, Jan 12, 2016 at 11:19:26AM +, John Harrison wrote:
> > On 11/01/2016 22:16, Chris Wilson wrote:
> > >On Mon, Jan 11, 2016 at 06:42:39PM +, john.c.harri...@intel.com wrote:
> > >>From: John Harrison
> > >>
> > >>MMIO f
On 01/12/2016 04:11 AM, Dave Gordon wrote:
On 06/01/16 20:53, yu@intel.com wrote:
> From: Alex Dai
>
> During driver unloading, the guc_client created for command submission
> needs to be released to avoid memory leak.
>
> Signed-off-by: Alex Dai
> ---
> drivers/gpu/drm/i915/i915_guc_su
From: Alex Dai
During driver unloading, the guc_client created for command submission
needs to be released to avoid memory leak.
The struct_mutex needs to be held before tearing down GuC.
v1: Move i915_guc_submission_disable out of i915_guc_submission_fini and
take struct_mutex lock before
commit 033908aed5a596f6202c848c6bbc8a40fb1a8490
Author: Dave Gordon
Date: Thu Dec 10 18:51:23 2015 +
drm/i915: mark GEM object pages dirty when mapped & written by the CPU
introduced a check into i915_gem_object_get_dirty_pages() that returned
a NULL pointer when called with a bad obje
On Tue, Jan 12, 2016 at 11:40:06PM +, Chris Wilson wrote:
> struct drm_i915_gem_object_ops {
> + const unsigned int flags;
Bleh, const is redundant as the definitions should be const themselves.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
On Tue, Jan 12, 2016 at 04:45:02PM +, Dave Gordon wrote:
> On 12/01/16 13:11, Chris Wilson wrote:
> >On Tue, Jan 12, 2016 at 12:54:25PM +, Tvrtko Ursulin wrote:
> >>
> >>On 12/01/16 12:12, Chris Wilson wrote:
> >>>On Tue, Jan 12, 2016 at 11:56:11AM +, Tvrtko Ursulin wrote:
> From: T
From: Abhay Kumar
Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.
v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
delay calculation(Ville).
v3: Addressed below comments
1. Tracking time from
> From: Gordon, David S
> Sent: Tuesday, January 12, 2016 9:49 PM
>
> On 12/01/2016 11:43, John Harrison wrote:
> > On 12/01/2016 04:37, Tian, Kevin wrote:
> >>> From: john.c.harri...@intel.com
> >>> Sent: Tuesday, January 12, 2016 2:42 AM
> >>>
> >>> From: John Harrison
> >>>
> >>> Implemented a
On 12 January 2016 at 08:59, Shobhit Kumar wrote:
> Not sending yet to pwm mailing list as this is all untested. C.B. please
> test the patches and see if they work at all for you. For testing Please
> enable -
>
> CONFIG_PWM_LPSS=y
> CONFIG_PWM_LPSS_PLATFORM=y
I applied these patches to 4.4-rc8
On 01/13/2016 11:00 AM, C. B. wrote:
On 12 January 2016 at 08:59, Shobhit Kumar wrote:
Not sending yet to pwm mailing list as this is all untested. C.B. please
test the patches and see if they work at all for you. For testing Please
enable -
CONFIG_PWM_LPSS=y
CONFIG_PWM_LPSS_PLATFORM=y
I ap
== Summary ==
Built on 06d0112e293dfdea7f796d4085f755898850947b drm-intel-nightly:
2016y-01m-12d-21h-16m-40s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (bdw-nuci7)
dmesg-warn -> PASS (bdw-ultra)
Te
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