On Mon, 2016-01-11 at 21:29 +, Chris Wilson wrote:
> On Mon, Jan 11, 2016 at 05:15:54PM +, Tvrtko Ursulin wrote:
> > > Is that not what was written? I take it my telepathy isn't working
> > > again.
> >
> > Sorry not a new loop, new case in a old loop. This is the hunk I think
> > is not h
== Summary ==
Built on a90796840c30dac6d9907439bf98d1d08046c49d drm-intel-nightly:
2016y-01m-11d-17h-22m-54s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup susp
== Summary ==
HEAD is now at a907968 drm-intel-nightly: 2016y-01m-11d-17h-22m-54s UTC
integration manifest
Applying: drm: kerneldoc for drm_fops.c
Repository lacks necessary blobs to fall back on 3-way merge.
Cannot fall back to three-way merge.
Patch failed at 0001 drm: kerneldoc for drm_fops.c
On 11/01/16 19:41, Dave Gordon wrote:
On 11/01/16 08:38, Daniel Vetter wrote:
On Fri, Jan 08, 2016 at 11:29:44AM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We are not allowed to call i915_gem_obj_ggtt_offset from irq
context without the big kernel lock held.
LRCA lifetime is well def
On Tue, Jan 12, 2016 at 11:11:20AM +, John Harrison wrote:
> On 12/01/2016 00:20, Chris Wilson wrote:
> >On Mon, Jan 11, 2016 at 06:42:31PM +, john.c.harri...@intel.com wrote:
> >>From: John Harrison
> >>
> >>A later patch in this series re-organises the batch buffer submission
> >>code. P
== Summary ==
Built on a90796840c30dac6d9907439bf98d1d08046c49d drm-intel-nightly:
2016y-01m-11d-17h-22m-54s UTC integration manifest
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
pass -> DMESG-WARN (byt-nuc)
Test pm_rpm:
Subgroup basic-r
On Mon, Jan 11, 2016 at 10:41 PM, Daniel Vetter wrote:
> I'm auditing them all, empty ones just confuse ...
>
> Cc: Patrik Jakobsson
> Acked-by: Daniel Stone
> Reviewed-by: Alex Deucher
> Signed-off-by: Daniel Vetter
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/psb_drv.c | 9 -
On Mon, Jan 11, 2016 at 06:12:12PM -0700, Jonathan Corbet wrote:
> On Sat, 12 Dec 2015 12:13:45 +0100
> Daniel Vetter wrote:
>
> > I just figured there's no way this could get it, and I'd
> > much rather improve the docs themselves than trying to convince core
> > kernel folks that this might be
On Mon, Jan 11, 2016 at 09:54:37PM +0200, Jani Nikula wrote:
> Hide knowledge about VBT child devices in intel_bios.c.
>
> Signed-off-by: Jani Nikula
Assuming you copypasted correctly ;-)
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/inte
On 11/01/16 22:49, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 05:32:27PM +, Tvrtko Ursulin wrote:
+struct i915_gem_active {
+ struct drm_i915_gem_request *request;
+};
+
+static inline void
+i915_gem_request_mark_active(struct drm_i915_gem_request *request,
+
Chris Wilson writes:
> Now that we have split out the seqno-barrier from the
> engine->get_seqno() callback itself, we can move the users of the
> seqno-barrier to the required callsites simplifying the common code and
> making the required workaround handling much more explicit.
>
> Signed-off-b
On 11/01/2016 22:58, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 02:47:33PM -0800, Jesse Barnes wrote:
On 01/11/2016 11:03 AM, John Harrison wrote:
On 08/01/2016 22:05, Chris Wilson wrote:
On Fri, Jan 08, 2016 at 06:47:24PM +, john.c.harri...@intel.com wrote:
From: John Harrison
The fen
From: Tvrtko Ursulin
Purpose is to avoid calling i915_gem_obj_ggtt_offset from the
interrupt context without the big lock held.
v2: Renamed gtt_start to gtt_offset. (Daniel Vetter)
v3: Cache the VMA instead of address. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Cc: Daniel Vetter
Cc: Chris W
On 12/01/2016 00:20, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 06:42:31PM +, john.c.harri...@intel.com wrote:
From: John Harrison
A later patch in this series re-organises the batch buffer submission
code. Part of that is to reduce the scope of a pm_get/put pair.
Specifically, they previ
On Mon, 2016-01-11 at 17:53 +, R, Durgadoss wrote:
> > -Original Message-
> > From: Ander Conselvan De Oliveira [mailto:conselv...@gmail.com]
> > Sent: Monday, January 11, 2016 8:46 PM
> > To: R, Durgadoss; intel-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH 7/7] drm/i915/dp: Enable
On Tue, Jan 12, 2016 at 10:04:20AM +, Tvrtko Ursulin wrote:
> Perhaps then leave the structure name as is and just rename the
> function to i915_gem_request_assign_active? I think that describes
> better what is actually happening.
i915_gem_request_update_active()?
request_assign_active() say
== Summary ==
Built on a90796840c30dac6d9907439bf98d1d08046c49d drm-intel-nightly:
2016y-01m-11d-17h-22m-54s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i7k-2) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup read
On Tue, Jan 12, 2016 at 11:34:45AM +, John Harrison wrote:
> On 11/01/2016 22:24, Chris Wilson wrote:
> >On Mon, Jan 11, 2016 at 06:42:50PM +, john.c.harri...@intel.com wrote:
> >>From: John Harrison
> >>
> >>It can be useful to be able to disable certain features (e.g. the
> >>entire sche
Chris Wilson writes:
> By using the same address for storing the HWS on every platform, we can
> remove the platform specific vfuncs and reduce the get-seqno routine to
> a single read of a cached memory location.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_debugfs.c
On 11/01/2016 22:24, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 06:42:50PM +, john.c.harri...@intel.com wrote:
From: John Harrison
It can be useful to be able to disable certain features (e.g. the
entire scheduler) via a module parameter for debugging purposes. A
parameter has the advanta
On Tue, Jan 12, 2016 at 12:27:05PM +0200, Mika Kuoppala wrote:
> > for_each_ring(ring, dev_priv, i) {
> > - seqno[i] = ring->get_seqno(ring);
> > acthd[i] = intel_ring_get_active_head(ring);
> > + seqno[i] = ring->get_seqno(ring);
>
> Oh! Perhaps I am overly opt
drm_atomic_set_crtc_for_connector should be used,
and crtc->primary->crtc is assigned by atomic_commit.
Rely on the helpers for setting this correctly, so
connector_mask gets updated too.
Signed-off-by: Maarten Lankhorst
---
Should this be applied to topic/drm-misc since atomic connector_masks a
On 11/01/2016 22:04, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 06:42:35PM +, john.c.harri...@intel.com wrote:
From: John Harrison
The seqno value cannot always be used when debugging issues via trace
points. This is because it can be reset back to start, especially
during TDR type tests.
On 11/01/16 14:33, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 02:08:39PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We can avoid open-coding the schedule wake-up since
commit 9cff8adeaa34b5d2802f03f89803da57856b3b72
Author: NeilBrown
Date: Fri Feb 13 15:49:17 2015 +110
On 11/01/2016 22:14, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 06:42:41PM +, john.c.harri...@intel.com wrote:
From: John Harrison
The scheduler needs to know when requests have completed so that it
can keep its own internal state up to date and can submit new requests
to the hardware fro
On 06/01/16 20:53, yu@intel.com wrote:
From: Alex Dai
During driver unloading, the guc_client created for command submission
needs to be released to avoid memory leak.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_submission.c | 3 +++
1 file changed, 3 insertions(+)
diff
On 11/01/2016 22:16, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 06:42:39PM +, john.c.harri...@intel.com wrote:
From: John Harrison
MMIO flips are the preferred mechanism now but more importantly,
Says who?
I asked this exact question at the linux architecture forum quite some
time ago
On Tue, Jan 12, 2016 at 12:35:59PM +0100, Maarten Lankhorst wrote:
> drm_atomic_set_crtc_for_connector should be used,
> and crtc->primary->crtc is assigned by atomic_commit.
>
> Rely on the helpers for setting this correctly, so
> connector_mask gets updated too.
>
> Signed-off-by: Maarten Lankh
On Tue, Jan 12, 2016 at 11:56:11AM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> LRC lifetime is well defined so we can cache the page pointing
> to the object backing store in the context in order to avoid
> walking over the object SG page list from the interrupt context
> without the
On 12/01/2016 11:28, Chris Wilson wrote:
On Tue, Jan 12, 2016 at 11:11:20AM +, John Harrison wrote:
On 12/01/2016 00:20, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 06:42:31PM +, john.c.harri...@intel.com wrote:
From: John Harrison
A later patch in this series re-organises the batch
On Tue, Dec 22, 2015 at 11:50:47AM +0530, ankitprasad.r.sha...@intel.com wrote:
> @@ -456,6 +457,21 @@ struct drm_i915_gem_create {
>*/
> __u32 handle;
> __u32 pad;
> + /**
> + * Requested flags (currently used for placement
> + * (which memory domain))
> + *
On Tue, 2016-01-12 at 09:34 +0100, Daniel Vetter wrote:
> On Mon, Jan 11, 2016 at 06:12:12PM -0700, Jonathan Corbet wrote:
> > On Sat, 12 Dec 2015 12:13:45 +0100
> > Daniel Vetter wrote:
> >
> > > I just figured there's no way this could get it, and I'd
> > > much rather improve the docs themselv
On Tue, Jan 12, 2016 at 11:51:58AM +, Russell King - ARM Linux wrote:
> On Mon, Jan 11, 2016 at 10:41:01PM +0100, Daniel Vetter wrote:
> > The compiler will do this, but the void hits when grepping all the
> > hooks for a subsystem wide audit are slightly annoying. So remove them
> > for next t
On Mon, Jan 11, 2016 at 02:13:06PM -0800, Matt Roper wrote:
> On Mon, Jan 11, 2016 at 09:31:03PM +0200, Ville Syrjälä wrote:
> > On Mon, Dec 21, 2015 at 07:31:17AM -0800, Matt Roper wrote:
> > > In commit
> > >
> > > commit 024c9045221fe45482863c47c4b4c47d37f97cbf
> > > Author: Mat
On 11/01/2016 22:07, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 06:43:07PM +, john.c.harri...@intel.com wrote:
From: John Harrison
The scheduler has always tracked batch buffer dependencies based on
DRM object usage. This means that it will not submit a batch on one
ring that has outstand
From: Tvrtko Ursulin
LRC lifetime is well defined so we can cache the page pointing
to the object backing store in the context in order to avoid
walking over the object SG page list from the interrupt context
without the big lock held.
v2: Also cache the mapping. (Chris Wilson)
v3: Unmap on the
From: Tvrtko Ursulin
LRC code was calling GEM API like i915_gem_obj_ggtt_offset from
places where the struct_mutex cannot be grabbed (irq handlers).
To avoid that this patch caches some interesting bits and values
in the engine and context structures.
Some usages are also removed where they are
On Tue, Jan 12, 2016 at 11:42:39AM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Purpose is to avoid calling i915_gem_obj_ggtt_offset from the
> interrupt context without the big lock held.
>
> v2: Renamed gtt_start to gtt_offset. (Daniel Vetter)
> v3: Cache the VMA instead of address.
On Tue, Jan 12, 2016 at 11:03:08AM +, John Harrison wrote:
> On 11/01/2016 22:58, Chris Wilson wrote:
> >On Mon, Jan 11, 2016 at 02:47:33PM -0800, Jesse Barnes wrote:
> >>On 01/11/2016 11:03 AM, John Harrison wrote:
> >>>On 08/01/2016 22:05, Chris Wilson wrote:
> On Fri, Jan 08, 2016 at 06:
From: Tvrtko Ursulin
LRC lifetime is well defined so we can cache the page pointing
to the object backing store in the context in order to avoid
walking over the object SG page list from the interrupt context
without the big lock held.
v2: Also cache the mapping. (Chris Wilson)
Signed-off-by: T
On 12/01/16 12:12, Chris Wilson wrote:
On Tue, Jan 12, 2016 at 11:56:11AM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
LRC lifetime is well defined so we can cache the page pointing
to the object backing store in the context in order to avoid
walking over the object SG page list from the
On 11/01/2016 23:14, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 06:42:47PM +, john.c.harri...@intel.com wrote:
From: John Harrison
The scheduler can cause batch buffers, and hence requests, to be
submitted to the ring out of order and asynchronously to their
submission to the driver. Thus
On Mon, Jan 11, 2016 at 08:37:09PM +, Daniel Stone wrote:
> Hi,
>
> On 5 January 2016 at 10:23, Daniel Vetter wrote:
> > On Wed, Dec 23, 2015 at 09:47:00AM +, Daniel Stone wrote:
> >> It's not even a legacy vs. atomic thing, this can happen in
> >> pure-atomic as well. Same as the render-
On 12/01/2016 04:37, Tian, Kevin wrote:
From: john.c.harri...@intel.com
Sent: Tuesday, January 12, 2016 2:42 AM
From: John Harrison
Implemented a batch buffer submission scheduler for the i915 DRM driver.
The general theory of operation is that when batch buffers are
submitted to the driver,
On Tue, Jan 12, 2016 at 12:05:06PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
> > - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
> > - PIPE_CONTROL_WRITE_FLUSH |
> > - PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
> > - intel_ring
On Mon, Jan 11, 2016 at 10:41:01PM +0100, Daniel Vetter wrote:
> The compiler will do this, but the void hits when grepping all the
> hooks for a subsystem wide audit are slightly annoying. So remove them
> for next time around.
I'll try to remember to queue this after -rc1, though a reminder
afte
On 07/01/16 16:53, Chris Wilson wrote:
On Thu, Jan 07, 2016 at 08:49:38AM -0800, Jesse Barnes wrote:
On 01/07/2016 03:58 AM, Chris Wilson wrote:
On Thu, Jan 07, 2016 at 10:20:50AM +, Dave Gordon wrote:
There are a number of places where the driver needs a request, but isn't
working on beha
On Mon, Jan 11, 2016 at 08:48:32PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Restore the lost phys status page cleanup.
>
> Fixes the following splat with DMA_API_DEBUG=y:
Oh, we should enable this in our CI. Can you please shoot a mail to Tomi?
>
> WARNING: CPU: 0
On Tue, Jan 12, 2016 at 12:54:25PM +, Tvrtko Ursulin wrote:
>
> On 12/01/16 12:12, Chris Wilson wrote:
> >On Tue, Jan 12, 2016 at 11:56:11AM +, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>
> >>LRC lifetime is well defined so we can cache the page pointing
> >>to the object backing
Op 12-01-16 om 13:34 schreef Daniel Vetter:
> On Tue, Jan 12, 2016 at 12:35:59PM +0100, Maarten Lankhorst wrote:
>> drm_atomic_set_crtc_for_connector should be used,
>> and crtc->primary->crtc is assigned by atomic_commit.
>>
>> Rely on the helpers for setting this correctly, so
>> connector_mask g
On Mon, Jan 11, 2016 at 01:52:17PM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Add reboot notifier for all platforms. This guarantees T12 delay
> compliance during reboot cycles when pre-os enables the panel within
> 500ms.
>
> Signed-off-by: Clint Taylor
> ---
> drivers/
On ma, 2016-01-11 at 11:00 +, Chris Wilson wrote:
> Since
>
> commit 43566dedde54f9729113f5f9fde77d53e75e61e9
> Author: Chris Wilson
> Date: Fri Jan 2 16:29:29 2015 +0530
>
> drm/i915: Broaden application of set-domain(GTT)
>
> we allowed objects to be in the GTT domain, but unbound.
Hi,
Can someone review the patches in the below mail?
PFB the link to the same:
https://patchwork.freedesktop.org/series/369/#rev5
Thanks and Regards,
Shubhangi Shrivastava.
On Tuesday 05 January 2016 06:28 PM,
intel-gfx-requ...@lists.freedesktop.org wrote:
Send Intel-gfx mail
On 12/01/16 11:01, Chris Wilson wrote:
On Tue, Jan 12, 2016 at 10:04:20AM +, Tvrtko Ursulin wrote:
Perhaps then leave the structure name as is and just rename the
function to i915_gem_request_assign_active? I think that describes
better what is actually happening.
i915_gem_request_update
On 12/01/16 11:01, Chris Wilson wrote:
On Tue, Jan 12, 2016 at 10:04:20AM +, Tvrtko Ursulin wrote:
Perhaps then leave the structure name as is and just rename the
function to i915_gem_request_assign_active? I think that describes
better what is actually happening.
i915_gem_request_update_
On 11/01/16 09:17, Chris Wilson wrote:
We use "list" to denote the list and "link" to denote an element on that
list. Rename request->list to match this idiom.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_gem.c | 12 +++
On Mon, Jan 11, 2016 at 02:55:37PM -0800, abhay.ku...@intel.com wrote:
> From: Abhay Kumar
>
> Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
> if this time is already spent in suspend/poweron time.
>
> v2: Use CLOCK_BOOTTIME and remove jiffies for panel power cycle
>
On 12/01/2016 11:43, John Harrison wrote:
On 12/01/2016 04:37, Tian, Kevin wrote:
From: john.c.harri...@intel.com
Sent: Tuesday, January 12, 2016 2:42 AM
From: John Harrison
Implemented a batch buffer submission scheduler for the i915 DRM
driver.
The general theory of operation is that whe
On 11/01/16 09:17, Chris Wilson wrote:
Elsewhere we have adopted the convention of using '_link' to denote
elements in the list (and '_list' for the actual list_head itself), and
that the name should indicate which list the link belongs to (and
preferrably not just where the link is being store
On Thu, Jan 07, 2016 at 10:20:50AM +, Dave Gordon wrote:
> There are a number of places where the driver needs a request, but isn't
> working on behalf of any specific user or in a specific context. At
> present, we associate them with the per-engine default context. A future
> patch will aboli
On Thu, Jan 07, 2016 at 10:20:51AM +, Dave Gordon wrote:
> Now that we've eliminated a lot of uses of ring->default_context,
> we can eliminate the pointer itself.
>
> All the engines share the same default intel_context, so we can just
> keep a single reference to it in the dev_priv structure
On Thu, Jan 07, 2016 at 10:20:52AM +, Dave Gordon wrote:
> There are a few bits of code which the transformations implemented by
> the previous patch reveal to be suboptimal, once the notion of a per-
> ring default context has gone away. So this tidies up the leftovers.
>
> It could have been
On Tue, Jan 12, 2016 at 02:50:28PM +0100, Daniel Vetter wrote:
> On Thu, Jan 07, 2016 at 10:20:50AM +, Dave Gordon wrote:
> > There are a number of places where the driver needs a request, but isn't
> > working on behalf of any specific user or in a specific context. At
> > present, we associat
On Tue, Jan 12, 2016 at 11:50:34AM +, John Harrison wrote:
> On 12/01/2016 11:28, Chris Wilson wrote:
> >On Tue, Jan 12, 2016 at 11:11:20AM +, John Harrison wrote:
> >>On 12/01/2016 00:20, Chris Wilson wrote:
> >>>On Mon, Jan 11, 2016 at 06:42:31PM +, john.c.harri...@intel.com wrote:
>
On Tue, Jan 12, 2016 at 11:19:26AM +, John Harrison wrote:
> On 11/01/2016 22:16, Chris Wilson wrote:
> >On Mon, Jan 11, 2016 at 06:42:39PM +, john.c.harri...@intel.com wrote:
> >>From: John Harrison
> >>
> >>MMIO flips are the preferred mechanism now but more importantly,
> >Says who?
>
On Tue, Jan 12, 2016 at 01:44:13PM +, Tvrtko Ursulin wrote:
>
> On 12/01/16 11:01, Chris Wilson wrote:
> >On Tue, Jan 12, 2016 at 10:04:20AM +, Tvrtko Ursulin wrote:
> >>Perhaps then leave the structure name as is and just rename the
> >>function to i915_gem_request_assign_active? I think
On 11/01/16 23:41, Daniel Vetter wrote:
> Again since the core takes care of this we can remove them. While at
> it also remove the postclose hook, it's empty.
>
> v2: Laurent pointed me at even more code to delete.
>
> Cc: Laurent Pinchart
> Cc: Tomi Valkeinen
> Acked-by: Daniel Stone
> Revie
Chris Wilson writes:
> When reading from the HWS page, we use barrier() to prevent the compiler
> optimising away the read from the volatile (may be updated by the GPU)
> memory address. This is more suited to READ_ONCE(); make it so.
>
> Signed-off-by: Chris Wilson
> Cc: Daniel Vetter
After r
On 12/01/2016 14:04, Daniel Vetter wrote:
On Tue, Jan 12, 2016 at 11:50:34AM +, John Harrison wrote:
On 12/01/2016 11:28, Chris Wilson wrote:
On Tue, Jan 12, 2016 at 11:11:20AM +, John Harrison wrote:
On 12/01/2016 00:20, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 06:42:31PM +, j
On 11/01/16 23:41, Daniel Vetter wrote:
> Again since the drm core takes care of event unlinking/disarming this
> is now just needless code.
>
> v2: Fixup misplaced hunks.
>
> Cc: Rob Clark
> Acked-by: Daniel Stone
> Reviewed-by: Alex Deucher (v1)
> Signed-off-by: Daniel Vetter
> ---
> driv
On Tue, Jan 12, 2016 at 01:56:48PM +, Chris Wilson wrote:
> But we were removing the engine->default_context as it complicated the
> rest of the code. I strongly prefer keeping the contexts explicit as
> context separation should be first and foremost in the driver.
$ git grep kernel_context -
Chris Wilson writes:
> On Tue, Jan 12, 2016 at 12:05:06PM +0200, Mika Kuoppala wrote:
>> Chris Wilson writes:
>> > - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
>> > - PIPE_CONTROL_WRITE_FLUSH |
>> > - PIPE_CONTROL_TEXTURE_CACHE_INVAL
On Tue, Jan 12, 2016 at 04:30:03PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > On Tue, Jan 12, 2016 at 12:05:06PM +0200, Mika Kuoppala wrote:
> >> Chris Wilson writes:
> >> > -intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) |
> >> > PIPE_CONTROL_QW_WRITE |
> >> > -
On Tue, Dec 08, 2015 at 07:59:35PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> While debugging problems on DDI platforms I got tired of the crap
> caused by the the dual personality DDI encoders, so I went ahead
> and split them into separate HDMI and DP encoders.
>
> A
On 11.01.2016 19:56, Ville Syrjälä wrote:
On Mon, Dec 21, 2015 at 01:57:22PM +0200, Gabriel Feceoru wrote:
On some HSW boards all pipeC tests fail with various dmesg errors.
This seems to be caused by Pipe C beeing disabled in FUSE_STRAP and
thus reading back the PIPECONF register is always ze
On Mon, Dec 14, 2015 at 06:23:39PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> It's been a while since I last ran igt on gen2, so I figured I'd
> give it a shot. 855 had some failures, 830 no longer worked at
> all. So I went ahead and fixed them, and here's the result.
pwm_info helps in encapsulating the PWM period_ns values and will form
basis of adding new pwm devices which can then be genrically used by
initializing proper pwm_info structure in the backlight setup call.
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.com
Signed-off-by: Shobhit Kumar
---
Hi,
This is an untested attempt to enable LPSS PWM in the driver. As part
of this did some restructuring for encapsulating the pwm_info inside the
panel->backlight itself. This makes enabling LPSS PWM clean and simple.
Not sending yet to pwm mailing list as this is all untested. C.B. please
test t
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.com
Signed-off-by: Shobhit Kumar
---
drivers/pwm/pwm-lpss-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pwm/pwm-lpss-platform.c b/drivers/pwm/pwm-lpss-platform.c
index 54433fc..910bc14 100644
--- a/drivers/pwm/pwm
Syncs with:
commit 15620206ae87ba9643ffa6f5ddb5471be7192006
Author: Mika Kuoppala
Date: Fri Nov 6 14:11:16 2015 +0200
drm/i915/skl: Add SKL GT4 PCI IDs
Signed-off-by: Damien Lespiau
---
src/i915_pciids.h | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff
Cc: cbroo...@gmail.com
Cc: jani.nik...@linux.intel.com
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_panel.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 9e24c59..1
Hello,
-mmots 4.4.0-mm1-dbg-00602-g776bd09
[ 5331.509087] WARNING: CPU: 0 PID: 359 at
drivers/gpu/drm/i915/intel_drv.h:1446 gen6_read32+0x7b/0x253 [i915]()
[ 5331.509091] RPM wakelock ref not held during HW access
[ 5331.509093] Modules linked in:
[ 5331.509182] CPU: 0 PID: 359 Comm: Xorg Not t
On Tue, Jan 12, 2016 at 05:00:16PM +0200, Gabriel Feceoru wrote:
>
>
> On 11.01.2016 19:56, Ville Syrjälä wrote:
> > On Mon, Dec 21, 2015 at 01:57:22PM +0200, Gabriel Feceoru wrote:
> >> On some HSW boards all pipeC tests fail with various dmesg errors.
> >> This seems to be caused by Pipe C beei
On Tue, Jan 12, 2016 at 04:19:39PM +0200, Tomi Valkeinen wrote:
>
> On 11/01/16 23:41, Daniel Vetter wrote:
> > Again since the drm core takes care of event unlinking/disarming this
> > is now just needless code.
> >
> > v2: Fixup misplaced hunks.
> >
> > Cc: Rob Clark
> > Acked-by: Daniel Ston
sanitize_watermarks() does not properly handle errors returned by
drm_atomic_helper_duplicate_state(). Make failures drop locks before
returning. We also change the lock of connection_mutex to a
drm_modeset_lock_all_ctx() to make sure any EDEADLK's are handled
earlier.
v2: Change call to lock co
== Summary ==
Built on 37f6c2ae666fbba9eff4355115252b8b0fd43050 drm-intel-nightly:
2016y-01m-12d-14h-25m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS (bdw-nuci7)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe
The most common thing on normal operation is ring tail
pointer update. Put it first in the shadow register list for
gen8, like we do with gen9.
Also order the checks inside reg write paths so that
if register is shadowed, no additional checks need to be made.
Cc: Chris Wilson
Signed-off-by: Mika
On Wed, Jan 13, 2016 at 12:06:07AM +0900, Sergey Senozhatsky wrote:
> Hello,
>
> -mmots 4.4.0-mm1-dbg-00602-g776bd09
Patch to shut this up (rpm is disabled by default for a reason still) on
it's way into 4.5/-next.
Thanks anyway for the report.
-Daniel
>
>
> [ 5331.509087] WARNING: CPU: 0 PID:
From: Ville Syrjälä
commit 10afa0b65fe2 ("drm/i915: Reject >9 ddi translation entried if port !=
A/E on SKL")
added sanity checks to make sure we don't end up with too many ddi translation
values for eDP ports, but it actually failed to check if the port is eDP.
We still look up the edp translat
On Tue, Jan 12, 2016 at 02:21:51PM +, John Harrison wrote:
> On 12/01/2016 14:04, Daniel Vetter wrote:
> >On Tue, Jan 12, 2016 at 11:50:34AM +, John Harrison wrote:
> >>On 12/01/2016 11:28, Chris Wilson wrote:
> >>>On Tue, Jan 12, 2016 at 11:11:20AM +, John Harrison wrote:
> On 12/0
On 12/01/16 11:41, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
LRC code was calling GEM API like i915_gem_obj_ggtt_offset from
places where the struct_mutex cannot be grabbed (irq handlers).
To avoid that this patch caches some interesting bits and values
in the engine and context structures.
== Summary ==
Built on 37f6c2ae666fbba9eff4355115252b8b0fd43050 drm-intel-nightly:
2016y-01m-12d-14h-25m-44s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
Test kms_flip:
Subgroup basic-flip-vs-
On 11/01/16 15:04, Tvrtko Ursulin wrote:
On 11/01/16 14:36, Chris Wilson wrote:
On Mon, Jan 11, 2016 at 02:08:40PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
No need to call ktime_get_raw_ns twice per unlimited wait and can
also elimate a local variable.
But we could eliminate both,
On Tue, Jan 12, 2016 at 05:28:16PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> commit 10afa0b65fe2 ("drm/i915: Reject >9 ddi translation entried if port !=
> A/E on SKL")
> added sanity checks to make sure we don't end up with too many ddi translation
> values for eDP p
These patches add support for Backlight Control using DPCD registers on eDP
displays.
- Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h
A copy of this patch has also been sent to dri-devel list.
- Patch 2 Implements functionaly for DPCD Backlight Control
Yetunde Adebisi
On Tue, Jan 12, 2016 at 04:54:27PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 14, 2015 at 06:23:39PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > It's been a while since I last ran igt on gen2, so I figured I'd
> > give it a shot. 855 had some failures, 830 no longer
This is used when reading Display Control capability Registers on the sink
device.
cc: Jani Nikula
cc: dri-de...@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm
From: Tvrtko Ursulin
One bugfix and a few tidy-ups:
* Pipe fault logging was broken on Gen9+.
* Removed some unnecessary local variables.
* Removed unnecessary initializers.
* Decreased pipe iir block indentation level.
* Grouped variable initialization close to use sites.
Signed-off-by: T
From: Tvrtko Ursulin
Tidy quite long interrupt service routine by factoring out
the display part.
This simplifies the exit path a little bit, makes the code
a bit more readable, and potentialy makes code reuse in the
future easier.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_i
On ti, 2016-01-12 at 16:35 +0100, Daniel Vetter wrote:
> On Tue, Jan 12, 2016 at 02:21:51PM +, John Harrison wrote:
> > On 12/01/2016 14:04, Daniel Vetter wrote:
> > > On Tue, Jan 12, 2016 at 11:50:34AM +, John Harrison wrote:
> > > > On 12/01/2016 11:28, Chris Wilson wrote:
> > > > > On Tu
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