Hi all,
New -testing cycle with cool stuff:
- fix atomic watermark recomputation logic (Maarten)
- modeset sequence fixes for LPT (Ville)
- more kbl enabling&prep work (Rodrigo, Wayne)
- first bits for mst audio
- page dirty tracking fixes from Dave Gordon
- new get_eld hook from Takashi, also inc
From: Abhay Kumar
Make resume/on codepath not to wait for panel_power_cycle_delay(t11_t12)
if this time is already spent in suspend/poweron time.
Change-Id: Ied0f10f82776af8e6e8ff561bb4e5c0ce1dad4b3
Signed-off-by: Abhay Kumar
---
drivers/gpu/drm/i915/intel_ddi.c | 3 +++
drivers/gpu/drm/i915/
According to bspec, some parts of HW require the addresses to be in
a canonical form, where bits [63:48] == [47]. Let's convert addresses to
canonical form prior to relocating and return converted offsets to
userspace. We also need to make sure that userspace is using addresses
in canonical form in
From: Alex Dai
GuC needs to know which registers and how they will be saved and
restored during event such as engine reset or power state changes.
For now only the base address of reg state is initialized. The
detail register table probably will be setup in future GuC TDR or
Preemption patch seri
From: Alex Dai
The GuC firmware uses this for various purposes. The ADS itself is a chunk of
memory created by driver to share with GuC. This series creates the GuC ADS
object and setup some basic settings for it.
This version addresses some comments from Chris W. Tidy up some code; replace
kmap
From: Alex Dai
GuC supports different scheduling policies for its four internal
queues. Currently these have been set to the same default values
as KMD_NORMAL queue.
Particularly POLICY_MAX_NUM_WI is set to 15 to match GuC internal
maximum submit queue numbers to avoid an out-of-space problem.
T
From: Alex Dai
Set ADS enabling flag during GuC init.
Signed-off-by: Alex Dai
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 4740949..625272f4 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader
From: Alex Dai
The GuC firmware uses this for various purposes. The ADS itself is
a chunk of memory created by driver to share with GuC. Its members
are usually addresses telling where GuC to access them, including
things like scheduler policies, register list that will be saved
and restored duri
From: Dave Gordon
The GuC code needs to know the size of a logical context, so we
expose get_lr_context_size(), renaming it intel_lr_context__size()
to fit the naming conventions for nonstatic functions.
For: VIZ-2021
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
diff --git a/drivers/gpu
On 12/18/2015 01:55 AM, Jani Nikula wrote:
On Thu, 17 Dec 2015, yu@intel.com wrote:
> From: Alex Dai
>
> The device struct_mutex needs to be held before releasing any GEM
> objects allocated by GuC.
This is indeed so, but your patch subject needs to say it fixes an
actual bug rather than
On Fri, Dec 18, 2015 at 09:01:03PM +0100, Michał Winiarski wrote:
> According to bspec, some parts of HW require the addresses to be in
> a canonical form, where bits [63:48] == [47]. Let's convert addresses to
> canonical form prior to relocating and return converted offsets to
> userspace. We als
From: Alex Dai
The device struct_mutex needs to be held before releasing any GEM
objects allocated by GuC.
WARNING: CPU: 0 PID: 1575 at include/drm/drm_gem.h:217
gem_release_guc_obj+0x5f/0x70 [i915]()
Call Trace:
[] dump_stack+0x44/0x60
[] warn_slowpath_common+0x82/0xc0
[
Original value of 32 blocks is not sufficient when using cursor size of
256x256 causing FIFO underruns when the reworked wm
caluclations in
commit 024c9045221fe45482863c47c4b4c47d37f97cbf
Author: Matt Roper
Date: Thu Sep 24 15:53:11 2015 -0700
drm/i915/skl: Eliminate usage of pipe_wm_param
pan_display_atomic() calls drm_atomic_clean_old_fb() to sanitize the
legacy FB fields (plane->fb and plane->old_fb). However it was building
the plane mask to pass to this function incorrectly (the bitwise OR was
using plane indices rather than plane masks). The end result was that
sometimes the
On Fri, Dec 18, 2015 at 02:29:22PM +, Chris Wilson wrote:
> On Fri, Dec 18, 2015 at 01:51:38PM +, Tvrtko Ursulin wrote:
> > On 18/12/15 12:28, Chris Wilson wrote:
> > >An interesting igt experiement I think would be:
> > >
> > >thread A, keep queuing batches with just a single MI_STORE_DWOR
On Fri, Dec 18, 2015 at 03:58:52PM -0800, Radhakrishna Sripada wrote:
> Original value of 32 blocks is not sufficient when using cursor size of
> 256x256 causing FIFO underruns when the reworked wm
> caluclations in
>
> commit 024c9045221fe45482863c47c4b4c47d37f97cbf
> Author: Matt Roper
> Date:
== Summary ==
HEAD is now at 7cdc548 drm-intel-nightly: 2015y-12m-18d-19h-26m-21s UTC
integration manifest
Applying: drm/i915: edp resume/On time optimization.
Repository lacks necessary blobs to fall back on 3-way merge.
Cannot fall back to three-way merge.
Patch failed at 0001 drm/i915: edp res
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