There's plenty of drm/i915 related hardware and software documentation,
and firmware downloads for the latest platforms.
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5f467845ef72..95c6bcb6bf22 10
On Mon, Oct 12, 2015 at 09:12:57PM +, Williams, Dan J wrote:
> On Mon, 2015-10-12 at 09:01 +0200, Daniel Vetter wrote:
> > On Fri, Oct 09, 2015 at 06:16:25PM -0400, Dan Williams wrote:
> > > i915 expects the OpRegion to be cached (i.e. not __iomem), so explicitly
> > > map it with memremap rath
On Mon, Oct 12, 2015 at 02:29:19PM +0200, Takashi Iwai wrote:
> On Mon, 12 Oct 2015 09:04:20 +0200,
> Daniel Vetter wrote:
> >
> > Another pile of regressions for Jairo to track ...
> >
> > On Sat, Oct 10, 2015 at 11:46:29AM +0200, Takashi Iwai wrote:
> > > Hi,
> > >
> > > I noticed that a HSW l
On Tue, Oct 13, 2015 at 10:24:58AM +0200, Daniel Vetter wrote:
> On Mon, Oct 12, 2015 at 02:29:19PM +0200, Takashi Iwai wrote:
> > On Mon, 12 Oct 2015 09:04:20 +0200,
> > Daniel Vetter wrote:
> > >
> > > Another pile of regressions for Jairo to track ...
> > >
> > > On Sat, Oct 10, 2015 at 11:46:
On Sat, Oct 10, 2015 at 10:44:32AM +0100, Chris Wilson wrote:
> We should serialise access to the intel_crtc->unpin_work through the
> dev->event_lock spinlock. It should not be possible for it to disappear
> without severe error as the mmio_flip worker has not tagged the
> unpin_work pending flip-
On Mon, 12 Oct 2015 10:17:51 +0200,
David Henningsson wrote:
>
>
>
> On 2015-10-12 10:07, David Henningsson wrote:
> > To make kernel-doc happy, the i915_audio_component_audio_ops struct
> > cannot be nested.
> >
> > Signed-off-by: David Henningsson
> > ---
>
> Changes since v1:
>
> * Added
The PTE_map trace added in commit 4c06ec8d13d2 ("drm/i915/gen8: Add
dynamic page trace events") was using the full start and length values,
instead of the page directory ones.
Since this is just a trace, I don't think it requires cc'ing stable.
Cc: Akash Goel
Signed-off-by: Michel Thierry
---
Thanks for the review Rob.
Regards
Shashank
On 10/12/2015 11:38 PM, Rob Bradford wrote:
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
BDW/SKL/BXT supports Degamma color correction feature, which
linearizes the non-linearity due to gamma encoded color values.
This will be applied bef
Regards
Shashank
On 10/12/2015 11:39 PM, Rob Bradford wrote:
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
BDW/SKL/BXT platforms support various Gamma correction modes
which are:
1. Legacy 8-bit mode
2. 10-bit Split Gamma mode
3. 12-bit mode
This patch does the following:
1. Adds t
Regards
Shashank
On 10/12/2015 11:43 PM, Rob Bradford wrote:
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote:
I915 color manager registers pipe degamma correction as palette
correction before CTM, DRM property.
This patch adds the no of coefficients(65) for degamma correction
as "num_
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Monday, October 12, 2015 10:54 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit
>Subject: Re: [Intel-gfx] [BXT DSI timing fixes v1 2/3] drm/i915/bxt: Get pipe
>timing for BXT DS
On Tue, Oct 13, 2015 at 12:23:38PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 10, 2015 at 10:44:32AM +0100, Chris Wilson wrote:
> > We should serialise access to the intel_crtc->unpin_work through the
> > dev->event_lock spinlock. It should not be possible for it to disappear
> > without severe erro
On 28/09/15 22:30, yu@intel.com wrote:
From: Alex Dai
The size / offset information of all firmware ingredients are
now caculated from header. Driver will validate the header and
rsa key size. If any component is out of boundary, driver will
reject the loading too.
v4: Now using 'size_dw'
On Mon, Oct 12, 2015 at 09:12:09AM -0700, Jesse Barnes wrote:
> On 09/18/2015 10:03 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_uncore.c | 16
> > 1 file changed, 8 insertions(+), 8
On Mon, Oct 12, 2015 at 10:31:35AM +0100, Chris Wilson wrote:
> On Mon, Oct 12, 2015 at 10:06:23AM +0100, Tvrtko Ursulin wrote:
> >
> > On 09/10/15 18:26, Chris Wilson wrote:
> > >On Fri, Oct 09, 2015 at 07:14:02PM +0200, Daniel Vetter wrote:
> > >>On Fri, Oct 09, 2015 at 10:03:14AM +0100, Tvrtko
On Tue, Oct 13, 2015 at 11:03:27AM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Monday, October 12, 2015 10:54 PM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit
> >Subject: Re: [Inte
On Fri, Oct 09, 2015 at 06:23:50PM +0100, Chris Wilson wrote:
> On Fri, Oct 09, 2015 at 07:18:21PM +0200, Daniel Vetter wrote:
> > On Fri, Oct 09, 2015 at 10:45:35AM +0100, Chris Wilson wrote:
> > > On Fri, Oct 09, 2015 at 11:15:08AM +0200, Daniel Vetter wrote:
> > > > My idea was to create a new r
On Fri, Oct 09, 2015 at 12:40:51PM +0100, Tomas Elf wrote:
> On 09/10/2015 09:27, Daniel Vetter wrote:
> >On Thu, Oct 08, 2015 at 07:31:34PM +0100, Tomas Elf wrote:
> >>Using safe list iterators alleviates the problem of unsynchronized driver
> >>list
> >>manipulations while error state capture is
On Fri, Oct 09, 2015 at 12:25:26PM +0100, Tomas Elf wrote:
> On 09/10/2015 08:48, Chris Wilson wrote:
> >On Thu, Oct 08, 2015 at 07:31:35PM +0100, Tomas Elf wrote:
> >>Since we're not synchronizing the ring request list during error state
> >>capture
> >>the request list state might change between
On Tue, Oct 13, 2015 at 01:29:56PM +0200, Daniel Vetter wrote:
> On Fri, Oct 09, 2015 at 06:23:50PM +0100, Chris Wilson wrote:
> > On Fri, Oct 09, 2015 at 07:18:21PM +0200, Daniel Vetter wrote:
> > > On Fri, Oct 09, 2015 at 10:45:35AM +0100, Chris Wilson wrote:
> > > > On Fri, Oct 09, 2015 at 11:15
On Fri, Oct 09, 2015 at 12:45:07PM +0100, Tomas Elf wrote:
> On 09/10/2015 09:28, Daniel Vetter wrote:
> >On Thu, Oct 08, 2015 at 07:31:35PM +0100, Tomas Elf wrote:
> >>Since we're not synchronizing the ring request list during error state
> >>capture
> >>the request list state might change betwee
On Fri, Oct 09, 2015 at 12:59:44PM +0100, Chris Wilson wrote:
> On Fri, Oct 09, 2015 at 12:30:29PM +0100, Tomas Elf wrote:
> > On 09/10/2015 08:48, Chris Wilson wrote:
> > >On Thu, Oct 08, 2015 at 07:31:37PM +0100, Tomas Elf wrote:
> > >>Sometimes the iterated vma objects are NULL apparently. Be aw
On Fri, Oct 09, 2015 at 09:45:16AM +0100, Chris Wilson wrote:
> On Fri, Oct 09, 2015 at 10:38:18AM +0200, Daniel Vetter wrote:
> > On Thu, Oct 08, 2015 at 07:31:39PM +0100, Tomas Elf wrote:
> > > Grab execlist lock when cleaning up execlist queues after GPU reset to
> > > avoid
> > > concurrency p
On Tue, Oct 13, 2015 at 01:26:36PM +0200, Daniel Vetter wrote:
> On Mon, Oct 12, 2015 at 10:31:35AM +0100, Chris Wilson wrote:
> > On Mon, Oct 12, 2015 at 10:06:23AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 09/10/15 18:26, Chris Wilson wrote:
> > > >On Fri, Oct 09, 2015 at 07:14:02PM +0200, Dan
On Tue, Oct 13, 2015 at 01:46:38PM +0200, Daniel Vetter wrote:
> On Fri, Oct 09, 2015 at 09:45:16AM +0100, Chris Wilson wrote:
> > On Fri, Oct 09, 2015 at 10:38:18AM +0200, Daniel Vetter wrote:
> > > On Thu, Oct 08, 2015 at 07:31:39PM +0100, Tomas Elf wrote:
> > > > Grab execlist lock when cleaning
On Tue, Oct 13, 2015 at 01:37:32PM +0200, Daniel Vetter wrote:
> On Fri, Oct 09, 2015 at 12:40:51PM +0100, Tomas Elf wrote:
> > On 09/10/2015 09:27, Daniel Vetter wrote:
> > >On Thu, Oct 08, 2015 at 07:31:34PM +0100, Tomas Elf wrote:
> > >>Using safe list iterators alleviates the problem of unsynch
On Fri, Oct 09, 2015 at 01:06:24PM +0100, Tomas Elf wrote:
> On 09/10/2015 11:44, Chris Wilson wrote:
> >On Fri, Oct 09, 2015 at 11:30:34AM +0100, Tomas Elf wrote:
> >>On 09/10/2015 08:46, Chris Wilson wrote:
> >>>On Thu, Oct 08, 2015 at 07:31:40PM +0100, Tomas Elf wrote:
> Avoid NULL pointer e
On Fri, Oct 09, 2015 at 06:22:43PM -0300, Paulo Zanoni wrote:
> This is a squash of the following commits:
>
> Revert "drm/i915: Drop intel_update_sprite_watermarks"
> This reverts commit 47c99438b52d12df50e182583634a4cfede3c920.
>
> Revert "drm/i915/ivb: Move WaCxSRDisabledForSpriteScaling w/a t
On Sat, Oct 10, 2015 at 02:17:55PM +0100, David Woodhouse wrote:
> On Fri, 2015-10-09 at 00:50 +0100, David Woodhouse wrote:
> > This patch set enables PASID support for the Intel IOMMU, along with
> > page request support.
> >
> > Like its AMD counterpart, it exposes an IOMMU-specific API. I beli
On Fri, Oct 09, 2015 at 06:55:23PM +0100, Chris Wilson wrote:
> On Fri, Oct 09, 2015 at 07:33:23PM +0200, Daniel Vetter wrote:
> > On Fri, Oct 09, 2015 at 01:21:45PM +0100, Chris Wilson wrote:
> > > The error state is purposefully racy as we expect it to be called at any
> > > time and so have avoi
On Tue, 23 Jun 2015, Andreas Lampersperger
wrote:
> When the i915.ko identify an eDP output on a valleyview
> board, it should be more slackly. The reason for that is,
> that BIOS DATA TABLES generated with intel BMP (Binary
> Modification Program) do not set bits for NOT_HDMI or
> DIGITAL_OUTPUT
On ke, 2015-08-26 at 16:58 +0530, Animesh Manna wrote:
> Skl is fully dependent on dmc for going to low power state (dc5/dc6).
> This requires a trigger from rpm. To ensure the dmc firmware
> is available for runtime pm support rpm-reference-count is used
> by not releasing the rpm reference if fir
On Tue, Oct 13, 2015 at 12:44:05PM +0100, Chris Wilson wrote:
> On Tue, Oct 13, 2015 at 01:26:36PM +0200, Daniel Vetter wrote:
> > On Mon, Oct 12, 2015 at 10:31:35AM +0100, Chris Wilson wrote:
> > > On Mon, Oct 12, 2015 at 10:06:23AM +0100, Tvrtko Ursulin wrote:
> > > >
> > > > On 09/10/15 18:26,
On Tue, 13 Oct 2015, Ville Syrjälä wrote:
> On Tue, Oct 13, 2015 at 10:24:58AM +0200, Daniel Vetter wrote:
>> On Mon, Oct 12, 2015 at 02:29:19PM +0200, Takashi Iwai wrote:
>> > On Mon, 12 Oct 2015 09:04:20 +0200,
>> > Daniel Vetter wrote:
>> > >
>> > > Another pile of regressions for Jairo to tra
On Tue, Oct 13, 2015 at 02:09:59PM +0200, Daniel Vetter wrote:
> On Fri, Oct 09, 2015 at 06:55:23PM +0100, Chris Wilson wrote:
> > On Fri, Oct 09, 2015 at 07:33:23PM +0200, Daniel Vetter wrote:
> > > On Fri, Oct 09, 2015 at 01:21:45PM +0100, Chris Wilson wrote:
> > > > The error state is purposeful
On 08/10/15 15:45, Animesh Manna wrote:
On 10/8/2015 5:53 PM, Mika Kuoppala wrote:
Animesh Manna writes:
On 9/21/2015 2:00 PM, Mika Kuoppala wrote:
Jani Nikula writes:
On Fri, 18 Sep 2015, Mika Kuoppala
wrote:
If csr/dmc firmware is known to be outdated, notify
user.
What would break
Color Management is an extension to DRM framework. It allows
abstraction of hardware color correction and enhancement capabilities
by virtue of DRM properties.
There are two major types of color correction supported by DRM
color manager:
- CTM: color transformation matrix, properties where a corre
This patch adds new structures in DRM layer for Palette color
correction.These structures will be used by user space agents
to configure appropriate number of samples and Palette LUT for
a platform.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
include/uapi/drm/drm.h | 26 +++
This patch set adds Color Manager implementation in DRM layer. Color Manager
is an extension in DRM framework to support color correction/enhancement.
Various Hardware platforms can support several color correction capabilities.
Color Manager provides abstraction of these capabilities and allows a
As per the DRM get_property implementation for a blob, framework
is supposed to return the blob_id to the caller. All the color
management blobs are saved in CRTC state during the set call.
This patch adds get_property support for color management
properties, by referring to the existing blob for
Color Manager framework defines a DRM property for color
space transformation and Gamut mapping. This property is called
CTM (Color Transformation Matrix).
This patch adds a new structure in DRM layer for CTM.
This structure can be used by all user space agents to
configure CTM coefficients for co
This patch adds new variables in CRTC state, to hold respective color
correction blobs. These blobs will be required during the atomic commit
for writing the color correction values in correction registers.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/drm_ato
DRM color management is written to extract the color correction
capabilities of various platforms, and every platform can showcase
its capabilities using the query properties.
Different hardwares can have different no of coefficients for palette
correction. Also the correction can be applied after
As per DRM color manager design, if a userspace wants to set a correction
blob, it prepares it and sends the blob_id to kernel via set_property
call. DRM framework takes this blob_id, gets the blob, and saves it
in the CRTC state, so that, during the atomic_commit, the color correction
values from
From DRM color management:
DRM color manager supports these color properties:
1. "ctm": Color transformation matrix property, where a
color transformation matrix of 9 correction values gets
applied as correction.
2. "palette_before_ctm": for corrections which get
This patch create new files intel_color_manager.c which
will contain the core color correction code for I915 driver
and its header intel_color_manager.h
The per color property patches coming up in this patch series
will fill the appropriate functions in this file.
Signed-off-by: Shashank Sharma
This patch adds set property interface for intel CRTC. This
interface will be used for set operation on any DRM properties.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_after_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of coeffi
DRM color manager allows the driver to showcase its best color
correction capabilities using the specific query property
cm_coeff_before_ctm_property. The driver must loads the no. of
coefficients for color correction as per the platform capability
during the init time.
This patch adds no of coeff
The color correction blob values are loaded during set_property
calls. This patch adds a function to find the blob and apply the
correction values to the display registers, during the atomic
commit call.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
1. Attaches CSC property to CRTC
2. Adds the core function to program CSC correction values
3. Adds CSC correction macros
Signed-of
CHV/BSW supports Degamma color correction, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Attach deGamma property to CRTC
2. Add the core function to program DeGamma correction values for
CHV/BSW platform
2.
I915 color manager registers pipe gamma correction as palette
correction after CTM property.
For BDW and higher platforms, split gamma correction is the best
gamma correction. This patch adds the no of coefficients(512) for
split gamma correction as "num_samples_after_ctm" parameter in device
info
Function intel_attach_color_properties_to_crtc attaches a
color property to its CRTC object. This patch calls this
function from crtc initialization sequence.
Signed-off-by: Shashank Sharma
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_
CHV/BSW platform supports two different pipe level gamma
correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Attaches Gamma property to CRTC
3. Adds the core Gamma correction function for CHV/BSW
4. Adds Gamma correction macr
BDW/SKL/BXT supports Degamma color correction feature, which
linearizes the non-linearity due to gamma encoded color values.
This will be applied before Color Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
BDW/SKL/BXT platform
2
I915 color manager registers pipe degamma correction as palette
correction before CTM, DRM property.
This patch adds the no of coefficients(512) for degamma correction
as "num_samples_before_ctm" parameter in device info structures,
for BDW and higher platforms.
Signed-off-by: Shashank Sharma
Si
BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into respective CSC registers.
This patch does the following:
1. Adds the core function to program CSC correction values for
BDW/SKL/BXT platform
2. Adds CSC correction macros/defines
Signed-off-by:
On Tue, 22 Sep 2015, Maarten Lankhorst
wrote:
> Nothing good can come from detaching scalers or updating pipe config
> when the crtc is already disabled. Touching registers while the crtc
> and power wells are disabled causes unclaimed register access warnings.
>
> Reported-by: Mika Kuoppala
> S
BDW/SKL/BXT platforms support various Gamma correction modes
which are:
1. Legacy 8-bit mode
2. 10-bit mode
3. Split mode
4. 12-bit mode
This patch does the following:
1. Adds the core function to program Gamma correction values
for BDW/SKL/BXT platforms
2. Adds Gamma correction macros/defines
On Wed, 23 Sep 2015, Maarten Lankhorst
wrote:
> On skylake and broxton the old registers are no longer in use.
> Instead it uses universal planes, fix primary_get_hw to use the
> correct registers.
>
> Signed-off-by: Maarten Lankhorst
> Cc: sta...@vger.kernel.org #v4.2+
Maarten, this patch has
On Thu, 27 Aug 2015, Maarten Lankhorst
wrote:
> When reading out hw state for planes we disable inactive planes which in
> turn triggers an update of the watermarks. The update depends on the
> crtc_clock being set which is done when reading out encoders. Thus
> postpone the plane readout until a
On Wed, 26 Aug 2015, Maarten Lankhorst
wrote:
> This fixes kms_universal_plane.universal-plane-pipe-A-functional.
>
> IPS gets enabled even though the primary plane is disabled. This is
> not supported, and results in warnings like below:
>
> [ cut here ]
> WARNING: CPU: 0
On Wed, 26 Aug 2015, Chris Wilson wrote:
> On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
>> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
>> > In order to flush the results from in-batch pipecontrol writes (used for
>> > example in glQuery) before declaring the bat
Op 13-10-15 om 14:40 schreef Jani Nikula:
> On Thu, 27 Aug 2015, Maarten Lankhorst
> wrote:
>> When reading out hw state for planes we disable inactive planes which in
>> turn triggers an update of the watermarks. The update depends on the
>> crtc_clock being set which is done when reading out en
On Wed, 02 Sep 2015, Arun Siluvery wrote:
> On 20/08/2015 16:27, Chris Wilson wrote:
>> On Thu, Aug 20, 2015 at 05:34:59PM +0300, Mika Kuoppala wrote:
>>> If we leave the last_retired_head to pre-reset value, we might
>>> end up in a situation where intel_ring_space() returns wrong
>>> value on ne
On 10 October 2015 at 05:55, Sharma, Shashank wrote:
> On 10/10/2015 4:17 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:28, Shashank Sharma
>> wrote:
>> [snip]
>>>
>>> +
>>> +/* Color management bit utilities */
>>> +#define GET_BIT_MASK(n) ((1 << n) - 1)
>>> +
>>> +/*
On Tue, 01 Sep 2015, Imre Deak wrote:
> On pe, 2015-08-14 at 18:24 +0100, Chris Wilson wrote:
>> The PIPE.STAT register contains some interrupt status bits per pipe, and
>> if assert cause the corresponding bit in the IIR to be asserted (thus
>> raising an interrupt). When handling an interrupt, w
On 10 October 2015 at 06:01, Sharma, Shashank wrote:
> On 10/10/2015 3:51 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> From DRM color management:
>>>
>>> DRM color manager supports these color properti
On Mon, 12 Oct 2015, Mika Kuoppala wrote:
> Some registers are, naturally, lost in gpu reset/suspend cycle.
> And some registers, for example in display domain, are not subject
> to gpu reset so they retain their contents.
>
> As hang recovery triggers a reset, recoverable gpu hang can currently
>
On 10 October 2015 at 06:09, Sharma, Shashank wrote:
> On 10/10/2015 4:37 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> CHV/BSW platform supports two different pipe level gamma
>>> correction modes, which are:
>>> 1. Legacy 8-bit mo
On Thu, 08 Oct 2015, Ville Syrjälä wrote:
> On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote:
>> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrj...@linux.intel.com
>> wrote:
>> > From: Ville Syrjälä
>> >
>> > We accidentally lost the initial DPLL register write in
>> > 1c4e027
On Tue, Oct 13, 2015 at 02:23:57PM +0200, Daniel Vetter wrote:
> On Tue, Oct 13, 2015 at 12:44:05PM +0100, Chris Wilson wrote:
> > On Tue, Oct 13, 2015 at 01:26:36PM +0200, Daniel Vetter wrote:
> > > On Mon, Oct 12, 2015 at 10:31:35AM +0100, Chris Wilson wrote:
> > > > On Mon, Oct 12, 2015 at 10:06
On Wed, 07 Oct 2015, Jani Nikula wrote:
> On Tue, 06 Oct 2015, Ville Syrjälä wrote:
>> On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote:
>>> On Tue, 06 Oct 2015, Ville Syrjälä wrote:
>>> > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote:
>>> >> Prefer inclusive ranges for
On 10 October 2015 at 06:20, Sharma, Shashank wrote:
> On 10/10/2015 4:54 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> The color correction blob values are loaded during set_property
>>> calls. This patch adds a function to find th
Op 23-09-15 om 17:34 schreef Gabriel Feceoru:
> Using 2 connectors (DVI and VGA) will cause wrpll to be set for
> INTEL_OUTPUT_HDMI but never reset if switching to INTEL_OUTPUT_VGA
>
> Supresses errors like these:
> [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.wrpll
>
Lo
On Tue, Oct 13, 2015 at 04:16:47PM +0300, Jani Nikula wrote:
> On Wed, 07 Oct 2015, Jani Nikula wrote:
> > On Tue, 06 Oct 2015, Ville Syrjälä wrote:
> >> On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote:
> >>> On Tue, 06 Oct 2015, Ville Syrjälä wrote:
> >>> > On Tue, Oct 06, 2015 at 0
'relative_constants_mode' has always been tracked per-device, but this
is wrong in execlists (or GuC) mode, as INSTPM is saved and restored
with the logical context, and the per-context value could therefore get
out of sync with the tracked value. This patch moves the tracking
element from the dev_
Pinning a userptr onto the hardware raises interesting questions about
the lifetime of such a surface as the framebuffer extends that life
beyond the client's address space. That is the hardware will need to
keep scanning out from the backing storage even after the client wants
to remap its address
On 10 October 2015 at 06:21, Sharma, Shashank wrote:
> On 10/10/2015 5:09 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
[snip]
>>> + switch (num_samples) {
>>> + case GAMMA_DISABLE_VALS:
>>> +
>>> + /* Disable Gamma function
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, October 13, 2015 4:54 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit
>Subject: Re: [Intel-gfx] [BXT DSI timing fixes v1 2/3] drm/i915/bxt: Get pipe
>timing for BXT DS
On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst wrote:
> Op 23-09-15 om 17:34 schreef Gabriel Feceoru:
> > Using 2 connectors (DVI and VGA) will cause wrpll to be set for
> > INTEL_OUTPUT_HDMI but never reset if switching to INTEL_OUTPUT_VGA
> >
> > Supresses errors like these:
> > [drm
On 10 October 2015 at 06:26, Sharma, Shashank wrote:
> On 10/10/2015 5:13 AM, Emil Velikov wrote:
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
>>> that needs to be programmed into CGM (Color Gamut Mapping) reg
Regards
Shashank
On 10/13/2015 6:33 PM, Emil Velikov wrote:
On 10 October 2015 at 06:01, Sharma, Shashank wrote:
On 10/10/2015 3:51 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
From DRM color management:
DRM color
On Tue, Oct 13, 2015 at 02:09:48PM +0100, Chris Wilson wrote:
> On Tue, Oct 13, 2015 at 02:23:57PM +0200, Daniel Vetter wrote:
> > On Tue, Oct 13, 2015 at 12:44:05PM +0100, Chris Wilson wrote:
> > > On Tue, Oct 13, 2015 at 01:26:36PM +0200, Daniel Vetter wrote:
> > > > On Mon, Oct 12, 2015 at 10:31
On 10 October 2015 at 06:31, Sharma, Shashank wrote:
> On 10/10/2015 5:19 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> BDW/SKL/BXT supports Degamma color correction feature, which
>>> linearizes the non-linearity due to gamma encod
On Tue, Oct 13, 2015 at 03:35:01PM +0200, Daniel Vetter wrote:
> On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst wrote:
> > Op 23-09-15 om 17:34 schreef Gabriel Feceoru:
> > > Using 2 connectors (DVI and VGA) will cause wrpll to be set for
> > > INTEL_OUTPUT_HDMI but never reset if swit
Regards
Shashank
On 10/13/2015 6:38 PM, Emil Velikov wrote:
On 10 October 2015 at 06:09, Sharma, Shashank wrote:
On 10/10/2015 4:37 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
CHV/BSW platform supports two different pipe level gamma
correction
Thanks for the review Emil.
Please find my comments inline
Regards
Shashank
On 10/13/2015 6:29 PM, Emil Velikov wrote:
On 10 October 2015 at 05:55, Sharma, Shashank wrote:
On 10/10/2015 4:17 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:28, Shashank Sharma
wrote:
[snip]
+
On Tue, Oct 13, 2015 at 03:45:58PM +0300, Jani Nikula wrote:
> On Wed, 26 Aug 2015, Chris Wilson wrote:
> > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
> >> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> >> > In order to flush the results from in-batch pipecontr
Op 13-10-15 om 15:35 schreef Daniel Vetter:
> On Tue, Oct 13, 2015 at 03:18:16PM +0200, Maarten Lankhorst wrote:
>> Op 23-09-15 om 17:34 schreef Gabriel Feceoru:
>>> Using 2 connectors (DVI and VGA) will cause wrpll to be set for
>>> INTEL_OUTPUT_HDMI but never reset if switching to INTEL_OUTPUT_VG
Regards
Shashank
On 10/13/2015 6:47 PM, Emil Velikov wrote:
On 10 October 2015 at 06:20, Sharma, Shashank wrote:
On 10/10/2015 4:54 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
The color correction blob values are loaded during set_property
call
Regards
Shashank
On 10/13/2015 6:53 PM, Emil Velikov wrote:
On 10 October 2015 at 06:21, Sharma, Shashank wrote:
On 10/10/2015 5:09 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
[snip]
+ switch (num_samples) {
+ case GAMMA_DISABLE_VALS:
+
+
On Tue, Oct 13, 2015 at 01:24:53PM +0100, Chris Wilson wrote:
> On Tue, Oct 13, 2015 at 02:09:59PM +0200, Daniel Vetter wrote:
> > On Fri, Oct 09, 2015 at 06:55:23PM +0100, Chris Wilson wrote:
> > > On Fri, Oct 09, 2015 at 07:33:23PM +0200, Daniel Vetter wrote:
> > > > On Fri, Oct 09, 2015 at 01:21
Regards
Shashank
On 10/13/2015 7:03 PM, Emil Velikov wrote:
On 10 October 2015 at 06:26, Sharma, Shashank wrote:
On 10/10/2015 5:13 AM, Emil Velikov wrote:
On 9 October 2015 at 20:29, Shashank Sharma
wrote:
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be
On Fri, Oct 09, 2015 at 02:43:21PM +0100, Tvrtko Ursulin wrote:
>
> On 09/10/15 14:11, Chris Wilson wrote:
> >Since the remove of the pin-ioctl, we only care about not changing the
> >cache level on buffers pinned to the hardware as indicated by
> >obj->pin_display. By knowing that only objects pi
On 10 October 2015 at 06:34, Sharma, Shashank wrote:
> On 10/10/2015 5:24 AM, Emil Velikov wrote:
>>
>> Hi Shashank,
>>
>> On 9 October 2015 at 20:29, Shashank Sharma
>> wrote:
>>>
>>> BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
>>> that needs to be programmed into respect
On Tue, Oct 13, 2015 at 03:52:08PM +0200, Daniel Vetter wrote:
> On Tue, Oct 13, 2015 at 01:24:53PM +0100, Chris Wilson wrote:
> > On Tue, Oct 13, 2015 at 02:09:59PM +0200, Daniel Vetter wrote:
> > > On Fri, Oct 09, 2015 at 06:55:23PM +0100, Chris Wilson wrote:
> > > > On Fri, Oct 09, 2015 at 07:33
On 13 October 2015 at 14:36, Sharma, Shashank wrote:
> On 10/13/2015 6:33 PM, Emil Velikov wrote:
>>
>> On 10 October 2015 at 06:01, Sharma, Shashank
>> wrote:
>>>
>>> On 10/10/2015 3:51 AM, Emil Velikov wrote:
Hi Shashank,
On 9 October 2015 at 20:29, Shashank Sharma
>>>
On Tue, Oct 13, 2015 at 04:10:19PM +0300, Jani Nikula wrote:
> On Thu, 08 Oct 2015, Ville Syrjälä wrote:
> > On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote:
> >> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrj...@linux.intel.com
> >> wrote:
> >> > From: Ville Syrjälä
> >> >
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