Make the alternatives stand out better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_ddi.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fdcb4562c8ce..2b5a29817e2e
It's more useful to limp on than bring the kernel down. Hitting this is
a more likely event with BXT DSI, although care should be taken not to
call the function for DSI.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_ddi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
On Mon, 28 Sep 2015, "Shankar, Uma" wrote:
>>-Original Message-
>>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>>Sent: Monday, September 28, 2015 6:58 PM
>>To: Shankar, Uma; intel-gfx@lists.freedesktop.org
>>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>>Subject
This removes the last depency of radeon for dev->struct_mutex!
Also the locking scheme for hyperz/cmask owners seems a bit unsound,
there's no protection in the preclose handler (and that never did hold
dev->struct_mutex while being called). So grab the same lock there,
too.
There's also all the
With atomic drivers we need to make sure that (at least in general)
property reads hold the right locks. But the legacy dpms property is
special and can be read locklessly. Since userspace loves to just
randomly look at that all the time (like with "status") do that.
To make it clear that we play
On Tue, 29 Sep 2015, Rasmus Villemoes wrote:
> ->stolen->start has type u64 aka unsigned long long; relying on the
> difference (effectively cast to int) for sorting is wrong.
>
> It wouldn't be a problem in practice if the values compared are always
> within INT_MAX of each other (so that the dif
On Tue, Sep 29, 2015 at 09:30:49AM +0200, Daniel Vetter wrote:
> This removes the last depency of radeon for dev->struct_mutex!
>
> Also the locking scheme for hyperz/cmask owners seems a bit unsound,
> there's no protection in the preclose handler (and that never did hold
> dev->struct_mutex whil
On Tue, Sep 29, 2015 at 10:37:30AM +0300, Jani Nikula wrote:
> On Tue, 29 Sep 2015, Rasmus Villemoes wrote:
> > ->stolen->start has type u64 aka unsigned long long; relying on the
> > difference (effectively cast to int) for sorting is wrong.
> >
> > It wouldn't be a problem in practice if the val
On Mon, Sep 28, 2015 at 04:54:15PM -0700, Rafael Antognolli wrote:
> This new test makes some basic testing on the proposed drm_dp_aux_dev
> interface. If the feature is enabled and the drm_dp_aux_dev class is
> present, it will check for available DP aux channels and test them for:
> - basic
On Tue, 29 Sep 2015, Rafael Antognolli wrote:
> This new test makes some basic testing on the proposed drm_dp_aux_dev
> interface. If the feature is enabled and the drm_dp_aux_dev class is
> present, it will check for available DP aux channels and test them for:
> - basic seek to 0 and read
With atomic drivers we need to make sure that (at least in general)
property reads hold the right locks. But the legacy dpms property is
special and can be read locklessly. Since userspace loves to just
randomly look at that all the time (like with "status") do that.
To make it clear that we play
This goes all the way back to the original KMS commit aeons ago
commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef
Author: Dave Airlie
Date: Fri Nov 7 14:05:41 2008 -0800
DRM: add mode setting support
But it seems to be completely unused. Only i915 and nouveau even
register these properties,
We chase pointers/lists without taking the locks protecting them,
which isn't that good.
Fix it.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_sysfs.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_s
For documentation and paranoia.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_sysfs.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index 615b7e667320..7506de0a75b4 100644
--- a/drivers/gpu/drm/drm
On Wed, 2015-09-23 at 11:38 +0200, Daniel Vetter wrote:
> On Wed, Sep 23, 2015 at 11:18 AM, Ander Conselvan De Oliveira
> wrote:
> > On Wed, 2015-09-23 at 10:24 +0200, Daniel Vetter wrote:
> > > On Tue, Sep 15, 2015 at 04:08:53PM +0300, Ander Conselvan De Oliveira
> > > wrote:
> > > > On Mon, 20
On Tue, Sep 29, 2015 at 01:54:53AM +0200, Rafael J. Wysocki wrote:
> On 9/28/2015 8:52 AM, Daniel Vetter wrote:
> >On Wed, Sep 23, 2015 at 10:49:36PM +0200, Rafael J. Wysocki wrote:
> >>On 9/23/2015 7:17 PM, Daniel Vetter wrote:
> >>>acpi_target_system_state() seems to be almost the thing we're loo
On Tue, Sep 29, 2015 at 11:08:25AM +0530, Animesh Manna wrote:
>
>
> On 09/28/2015 12:51 PM, Daniel Vetter wrote:
> >On Wed, Aug 26, 2015 at 01:36:07AM +0530, Animesh Manna wrote:
> >>Mmio register access after dc6/dc5 entry is not allowed when
> >>DC6 power states are enabled according to bspec
On Tue, Sep 29, 2015 at 09:43:10AM +0530, Jindal, Sonika wrote:
>
>
> On 9/28/2015 7:04 PM, Daniel Vetter wrote:
> >On Mon, Sep 28, 2015 at 02:26:04PM +0530, Sonika Jindal wrote:
> >>This patch adds a separate probe function for HDMI
> >>EDID read over DDC channel. This function has been
> >>regi
On Mon, Sep 28, 2015 at 04:48:32PM +, R, Durgadoss wrote:
> Hi Daniel,
>
> >-Original Message-
> >From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> >Vetter
> >Sent: Monday, September 28, 2015 1:50 PM
> >To: R, Durgadoss
> >Cc: Daniel Vetter; Jani Nikula; intel-
Pulled in entire series, thanks.
-Daniel
On Tue, Sep 29, 2015 at 12:46:20AM +0300, Imre Deak wrote:
> On Mon, 2015-09-28 at 23:47 +0300, Imre Deak wrote:
> > On Thu, 2015-09-24 at 23:29 +0300, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä
> > >
> > > Replace the use of mem_freq/
On Tue, Sep 29, 2015 at 10:24:26AM +0300, Jani Nikula wrote:
> Make the alternatives stand out better.
>
> Signed-off-by: Jani Nikula
Both applied to dinq.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 20 +---
> 1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, September 14, 2015 12:04 PM
> To: Deepak, M; Adebisi, YetundeX; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [PATCH 1/1] drm/i915: make backlight hooks connector specific
>
> Previously we've relied on having basi
>-Original Message-
>From: Nikula, Jani
>Sent: Tuesday, September 15, 2015 12:31 PM
>To: Daniel Vetter
>Cc: Deepak, M; Adebisi, YetundeX; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915: make backlight hooks
>connector specific
>
>On Mon, 14 Sep 2015, Daniel
The RC6 residency time unit is 833.33ns on BXT according to the
specification, so update the calculation accordingly. Use the same way
as CHV/VLV to divide by the corresponding frequency, as I think this is
the more natural unit for what the HW does internally.
Testcase: igt/pm_rc6_residency
Signe
On Mon, Sep 28, 2015 at 11:47:15PM +0300, Imre Deak wrote:
> On Thu, 2015-09-24 at 23:29 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Replace the use of mem_freq/4 with czclk_freq in the vlv c0 residency
> > calculations.
> >
> > Also deal with VLV_COUNT_RANGE_HIGH
On Tue, Sep 29, 2015 at 11:01:35AM +0200, Daniel Vetter wrote:
> On Tue, Sep 29, 2015 at 11:08:25AM +0530, Animesh Manna wrote:
> >
> >
> > On 09/28/2015 12:51 PM, Daniel Vetter wrote:
> > >On Wed, Aug 26, 2015 at 01:36:07AM +0530, Animesh Manna wrote:
> > >>Mmio register access after dc6/dc5 ent
Also adding Cc: intel-gfx, please include that in follow-ups.
Thanks,
Jani.
On Tue, 29 Sep 2015, Jani Nikula wrote:
> Although we don't support or enable CPU PWM with LPT/SPT based systems,
> it may have been enabled prior to loading the driver. Disable the CPU
> PWM on LPT/SPT backlight disabl
Hi Rafael,
On Mon, Sep 28, 2015 at 04:45:35PM -0700, Rafael Antognolli wrote:
> This is useful to determine which connector owns this AUX channel.
WTF? I posted a patch in August which does exactly that:
http://lists.freedesktop.org/archives/dri-devel/2015-August/088172.html
Can also be pulled i
On Tue, Sep 29, 2015 at 2:35 PM, Patrik Jakobsson
wrote:
> On Tue, Sep 29, 2015 at 11:01:35AM +0200, Daniel Vetter wrote:
>> On Tue, Sep 29, 2015 at 11:08:25AM +0530, Animesh Manna wrote:
>> >
>> >
>> > On 09/28/2015 12:51 PM, Daniel Vetter wrote:
>> > >On Wed, Aug 26, 2015 at 01:36:07AM +0530, An
On Tue, Sep 29, 2015 at 03:07:59PM +0300, Imre Deak wrote:
> The RC6 residency time unit is 833.33ns on BXT according to the
> specification, so update the calculation accordingly. Use the same way
> as CHV/VLV to divide by the corresponding frequency, as I think this is
> the more natural unit for
On Tue, Sep 29, 2015 at 03:01:57PM +0200, Daniel Vetter wrote:
> On Tue, Sep 29, 2015 at 2:35 PM, Patrik Jakobsson
> wrote:
> > On Tue, Sep 29, 2015 at 11:01:35AM +0200, Daniel Vetter wrote:
> >> On Tue, Sep 29, 2015 at 11:08:25AM +0530, Animesh Manna wrote:
> >> >
> >> >
> >> > On 09/28/2015 12:5
On Tue, 29 Sep 2015, Daniel Vetter wrote:
> With atomic drivers we need to make sure that (at least in general)
> property reads hold the right locks. But the legacy dpms property is
> special and can be read locklessly. Since userspace loves to just
> randomly look at that all the time (like with
Hi Daniel,
Thank you for the patch.
On Monday 28 September 2015 21:46:35 Daniel Vetter wrote:
> ->load is deprecated, bus functions are deprecated and everyone
> should use drm_dev_alloc®ister.
>
> So update the .tmpl (and pull a bunch of the overview docs into the
> sourcecode to increase chanc
The RC6 residency time unit is 833.33ns on BXT according to the
specification, so update the calculation accordingly. Use the same way
as CHV/VLV to divide by the corresponding frequency, as I think this is
the more natural unit for what the HW does internally.
v2:
- add missing IS_BROXTON check (
On Tue, Sep 29, 2015 at 3:23 PM, Ville Syrjälä
wrote:
> Hmm. Why are we going back and forth on this all the time? Was there
> some problem with the plan [1] that Imre and I hatched?
>
> [1] http://lists.freedesktop.org/archives/intel-gfx/2015-September/076612.html
Well this is just the interim b
On Tue, Sep 29, 2015 at 04:28:15PM +0300, Laurent Pinchart wrote:
> Hi Daniel,
>
> Thank you for the patch.
>
> On Monday 28 September 2015 21:46:35 Daniel Vetter wrote:
> > ->load is deprecated, bus functions are deprecated and everyone
> > should use drm_dev_alloc®ister.
> >
> > So update the
On Mon, Sep 28, 2015 at 04:45:36PM -0700, Rafael Antognolli wrote:
> This module is heavily based on i2c-dev. Once loaded, it provides one
> dev node per DP AUX channel, named drm_dp_auxN, where N is an integer.
>
> It's possible to know which connector owns this aux channel by looking
> at the re
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 46
>
> 2 files changed,
On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 8
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 2 files changed, 6 insertions(+), 6 deletion
On Mon, Sep 28, 2015 at 10:09:18AM +0100, Chris Wilson wrote:
> On Mon, Sep 28, 2015 at 10:54:59AM +0200, Daniel Vetter wrote:
> > On Wed, Sep 23, 2015 at 05:54:25PM +0100, Chris Wilson wrote:
> > > On Wed, Sep 23, 2015 at 12:52:23PM -0300, Paulo Zanoni wrote:
> > > > Technology has evolved and now
On Fri, 25 Sep 2015, Jani Nikula wrote:
> On Fri, 25 Sep 2015, Egbert Eich wrote:
>> Jani Nikula writes:
>> >
>> > Shouldn't this be _unlocked?
>> >
>> > I thought the convention was that functions that do not acquire locks
>> > are called _unlocked (although they may require a lock to be
After some recent progress enabling the Observation Architecture unit
for Gen8+, we can hopefully paint a fairly complete picture of the
requirements for supporting the unit from Haswell to Skylake and so
I'm looking again at the challenges in upstreaming this work.
Considering this, it looked lik
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl comparable to perf_event_open
that opens a file descriptor for an event source.
Based on our initial experience aiming to use the core perf
infrastructure, this interface is inspired by perf, but focused on
exposing metrics about work running on Gen graph
OACONTROL changes quite a bit for gen8, with some bits split out into a
per-context OACTXCONTROL register
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h| 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a
Adds a static OA unit, MUX + B Counter configuration for basic '3D'
metrics on Haswell. This is autogenerated from an internal XML
description of metric sets.
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.h| 5 ++
drivers/gpu/drm/i
Gen graphics hardware can be set up to periodically write snapshots of
performance counters into a circular buffer via its Observation
Architecture and this patch exposes that capability to userspace via the
i915 perf interface.
Cc: Chris Wilson
Signed-off-by: Robert Bragg
Signed-off-by: Zhenyu
The minimal sampling period is now configurable via a
dev.i915.oa_event_min_timer_exponent sysctl parameter.
Following the precedent set by perf, the default is the minimum that
won't (on its own) exceed the default kernel.perf_event_max_sample_rate
default of 10 samples/s.
Signed-off-by: Rob
Consistent with the kernel.perf_event_paranoid sysctl option that can
allow non-root users to access system wide cpu metrics, this can
optionally allow non-root users to access system wide OA counter metrics
from Gen graphics hardware.
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_pe
Maybe line 294 should become an unlock and should be moved under 295?
julia
On Tue, 29 Sep 2015, kbuild test robot wrote:
> CC: kbuild-...@01.org
> In-Reply-To: <1443513993-5228-2-git-send-email-daniel.vet...@ffwll.ch>
> TO: Daniel Vetter
> CC: DRI Development
> CC: Daniel Vetter , Intel Graph
Hi Robert,
[auto build test results on v4.3-rc3 -- if it's inappropriate base, please
ignore]
config: i386-defconfig (attached as .config)
reproduce:
git checkout a1d59679ae8f3e7e7659e9723ae3fc69af2532e6
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new one
On Tue, Sep 29, 2015 at 02:49:20PM +0200, Lukas Wunner wrote:
> Hi Rafael,
>
> On Mon, Sep 28, 2015 at 04:45:35PM -0700, Rafael Antognolli wrote:
> > This is useful to determine which connector owns this AUX channel.
>
> WTF? I posted a patch in August which does exactly that:
> http://lists.free
On Tue, Sep 29, 2015 at 10:55:39PM +0800, kbuild test robot wrote:
> Hi Robert,
>
> [auto build test results on v4.3-rc3 -- if it's inappropriate base, please
> ignore]
>
> config: i386-defconfig (attached as .config)
> reproduce:
> git checkout a1d59679ae8f3e7e7659e9723ae3fc69af2532e6
> # s
Hi Daniel,
On Tue, Sep 29, 2015 at 05:04:03PM +0200, Daniel Vetter wrote:
> On Tue, Sep 29, 2015 at 02:49:20PM +0200, Lukas Wunner wrote:
> > On Mon, Sep 28, 2015 at 04:45:35PM -0700, Rafael Antognolli wrote:
> > > This is useful to determine which connector owns this AUX channel.
> >
> > WTF? I
Hi all,
You may have noticed already, patchwork.freedesktop.org looks different.
That new version includes:
- Some re-design. Design is very much an iterative process, thoughts
and comments are welcome,
- Showing the number of Reviewed-by, Acked-by, Tested-by tags,
- Some cleanup of the
From: Animesh Manna
Mmio register access after DC6 entry is not allowed when according to
bspec (bspec-id 0527). Hence we must move dc6 enabling to be the very
last/first thing in the device suspend/resume flow. Currently it is
bound to PW2 as an alternative to DC5.
With this patch we have the f
On Tue, Sep 29, 2015 at 10:53:02AM +0300, Jani Nikula wrote:
> On Tue, 29 Sep 2015, Rafael Antognolli wrote:
> > This new test makes some basic testing on the proposed drm_dp_aux_dev
> > interface. If the feature is enabled and the drm_dp_aux_dev class is
> > present, it will check for available D
On Tue, Sep 29, 2015 at 05:27:33PM +0200, Lukas Wunner wrote:
> Hi Daniel,
>
> On Tue, Sep 29, 2015 at 05:04:03PM +0200, Daniel Vetter wrote:
> > On Tue, Sep 29, 2015 at 02:49:20PM +0200, Lukas Wunner wrote:
> > > On Mon, Sep 28, 2015 at 04:45:35PM -0700, Rafael Antognolli wrote:
> > > > This is u
On Tue, Sep 29, 2015 at 02:49:20PM +0200, Lukas Wunner wrote:
> Hi Rafael,
>
> On Mon, Sep 28, 2015 at 04:45:35PM -0700, Rafael Antognolli wrote:
> > This is useful to determine which connector owns this AUX channel.
>
> WTF? I posted a patch in August which does exactly that:
> http://lists.free
On Fri, Sep 04, 2015 at 07:32:57PM -0700, Chandra Konduru wrote:
> Properly allocate min blocks per hw requirements.
>
> v2:
> - changed helper functional param to bool, some code simplification (Ville)
>
> Signed-off-by: Chandra Konduru
IIRC I gave my r-b alrady?
But I'll toss it in again:
Re
On Fri, Sep 04, 2015 at 07:32:58PM -0700, Chandra Konduru wrote:
> This patch swaps src width and height for dbuf/wm calculations
> when rotation is 90/270 as per hw requirements.
>
> v2:
> - minor/cosmetic changes, removed plane_state check kludge (Ville)
>
> Signed-off-by: Chandra Konduru
Spe
On Fri, Sep 04, 2015 at 07:32:59PM -0700, Chandra Konduru wrote:
> This patch sets appropriate scaler mode for NV12 format.
> In this mode, skylake scaler does either chroma-upsampling or
> chroma-upsampling and resolution scaling.
>
> v2:
> - new reg defines squashed into patches used them (Ville
On Fri, Sep 04, 2015 at 07:33:01PM -0700, Chandra Konduru wrote:
> This patch adds NV12 to format_is_yuv() function
> and made it available for both primary and sprite
> planes.
>
> v2:
> -Use intel_ prefix for format_is_yuv (Ville)
>
> Signed-off-by: Chandra Konduru
Reviewed-by: Ville Syrjälä
On Fri, Sep 04, 2015 at 07:33:02PM -0700, Chandra Konduru wrote:
> This patch updates max supported scaler limits for NV12.
>
> v2:
> -Rebased to current kernel version 4.2.0.rc4 (me)
>
> v3:
> -simplified max_scale calculation (Ville)
>
> Signed-off-by: Chandra Konduru
> ---
> drivers/gpu/drm
On Fri, Sep 04, 2015 at 07:33:04PM -0700, Chandra Konduru wrote:
> This patch adds NV12 to list of supported formats for
> sprite plane.
>
> v2:
> - made supported format list const, fixed a leftover -1. (Ville)
>
> Signed-off-by: Chandra Konduru
> Testcase: igt/kms_nv12
Reviewed-by: Ville Syrj
On Fri, Sep 04, 2015 at 07:33:08PM -0700, Chandra Konduru wrote:
> This patch sets default initial phase and trip to scale NV12
> content. In future, if needed these can be set via properties
> or other means depending on incoming stream request. Until then
> defaults are fine.
>
> Signed-off-by:
tree: git://anongit.freedesktop.org/drm-intel for-linux-next
head: 22f146cd928e834c7eec724b6816e24cc29b59fb
commit: 67d92bb51cff3596b0ee660eef26f5c7017e3509 [746/778] drm/i915: Constify
adjusted_mode
reproduce:
# apt-get install sparse
git checkout 67d92bb51cff3596b0ee660eef26f5c7017e3509
On Fri, Sep 11, 2015 at 09:43:48AM -0700, Chandra Konduru wrote:
> This patch adds NV12 to list of supported formats for
> primary plane.
>
> v2:
> -Rebased (me)
>
> v3:
> -Rebased on top of primary plane YUV support patch (Ville)
>
> Signed-off-by: Chandra Konduru
> Testcase: igt/kms_nv12
Was
On Fri, Sep 11, 2015 at 09:44:18AM -0700, Chandra Konduru wrote:
> This patch adds NV12 as supported format to
> intel_framebuffer_init and performs various checks.
>
> v2:
> -Fix an issue in checks added (me)
>
> v3:
> -cosmetic update, split checks into two (Ville)
>
> v4:
> -Add stride alignm
On Tue, Sep 29, 2015 at 08:50:20PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 04, 2015 at 07:33:04PM -0700, Chandra Konduru wrote:
> > This patch adds NV12 to list of supported formats for
> > sprite plane.
> >
> > v2:
> > - made supported format list const, fixed a leftover -1. (Ville)
> >
> > Si
On Tue, Sep 29, 2015 at 04:28:46PM +0300, Imre Deak wrote:
> The RC6 residency time unit is 833.33ns on BXT according to the
> specification, so update the calculation accordingly. Use the same way
> as CHV/VLV to divide by the corresponding frequency, as I think this is
> the more natural unit for
On Fri, Sep 25, 2015 at 11:54:58AM +0200, Łukasz Daniluk wrote:
> Added checks for available slices, subslices and EUs for Broadwell. This
> information is filled in intel_device_info and is available to user with
> GET_PARAM.
> Added checks for enabled slices, subslices and EU for Broadwell. This
If MIPI is operated in command mode, and after display reset. if
not even one frame is sent after enabling the pipe and then if it
is disabled, pipe is getting stuck. This patch will fix this issue
by sending one frame after enabling the pipe.
Ideally,there should not be a case where there is mode
For command mode and video mode, panel prepare, wait for FIFO
checks are required. Making these changes generic across command
mode and video mode.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 10 +
During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
v2: Use crtc state flag instead of loop over encoders (Daniel)
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/
vblank interrupt should be disabled before starting the disable
sequence for MIPI command mode. Otherwise when pipe is disabled
TE interurpt will be still handled and one memory write command
will be sent with pipe disabled. This makes the pipe hw to get
stuck and it doesn't recover in the next ena
The bpp value which is used while calulating the txbyteclkhs values
should be wrt the pixel format value. Currently bpp is coming
from pipe config to calculate txbyteclkhs.
Signed-off-by: Deepak M
Signed-off-by: Yogesh Mohan Marimuthu
---
drivers/gpu/drm/i915/intel_dsi.c |5 ++---
During disable sequence for MIPI encoder in command mode, disable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
v2: Use crtc state flag instead of loop over encoders (Daniel)
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gp
Reset the display hardware if video mode to command mode transition
has to be done in MIPI display. otherwise command mode will not work.
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_display.c |
While enabling MIPI Port in command mode, enable tearing effect
by GPIO pin.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/
For command mode panel, panel's fb enabling and tearing configuration
is done as part of TEAR ON sequence. This patch parses and executes
TEAR ON sequence for MIPI command mode.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm
Changes done in preparation of command mode-
1. Set DBI HS LS Switch bit for DBI packets to be tramitted in HS mode.
2. Set DBI FIFO watermark.
3. Timing regs need not be programmmed for command mode.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kum
This patch will calculate the bandwidth timer for MIPI DBI interface.
If the BW timer value is available from VBT, then value from VBT
will be used.
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 24 +++-
Allocate DMA region for MIPI DBI command buffer. This memory
will be used when sending command via DBI interface.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
---
drivers/gpu/drm/i915/intel_dsi.c | 17 +
drivers/gpu/drm/i915/intel_dsi.h |2 ++
2 file
Add functions for DCS memory write command. The mem write
command to send fb data to panel is sent using this function.
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_drv
Hi,
These set of patches are for enabling DSI command mode on CHT. Command Mode
refers to
an operation in which transactions primarily take the form of sending commands
and data to a peripheral that incorporates a display controller. The display
controller may include local registers and a frame
While disabling MIPI Port in command mode, disable TE trigger by GPIO pin.
Signed-off-by: Gaurav K Singh
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/driver
On Tue, Sep 29, 2015 at 05:18:45PM +0200, Peter Zijlstra wrote:
> On Tue, Sep 29, 2015 at 10:55:39PM +0800, kbuild test robot wrote:
> > Hi Robert,
> >
> > [auto build test results on v4.3-rc3 -- if it's inappropriate base, please
> > ignore]
> >
> > config: i386-defconfig (attached as .config)
Thanks Ville for the review, I'm addressing all the issues but have some
questions on the ones mentioned below:
On Tue, Sep 29, 2015 at 05:09:23PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 28, 2015 at 04:45:36PM -0700, Rafael Antognolli wrote:
> > This module is heavily based on i2c-dev. Once load
On 9/29/2015 10:51 AM, Daniel Vetter wrote:
On Tue, Sep 29, 2015 at 01:54:53AM +0200, Rafael J. Wysocki wrote:
On 9/28/2015 8:52 AM, Daniel Vetter wrote:
On Wed, Sep 23, 2015 at 10:49:36PM +0200, Rafael J. Wysocki wrote:
On 9/23/2015 7:17 PM, Daniel Vetter wrote:
acpi_target_system_state() se
On Thu, Sep 24, 2015 at 04:26:28PM +0300, Jani Nikula wrote:
> On Thu, 24 Sep 2015, "da...@codemonkey.org.uk"
> wrote:
> > On Wed, Sep 23, 2015 at 11:07:56AM +, Lankhorst, Maarten wrote:
> > > Hey,
> > >
> > > Dave Jones schreef op di 22-09-2015 om 21:49 [-0400]:
> > > > On Tue, S
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/intel_lrc.c
between commit:
dfc53c5e73f8 ("drm/i915: Consider HW CSB write pointer before resetting the
sw read pointer")
from the drm-intel-fixes tree and commit:
83843d84fcd3 ("drm/i915: Pa
Hi Takashi,
Today's linux-next merge of the sound tree got a conflict in:
drivers/gpu/drm/i915/intel_audio.c
between commit:
3c85f5027595 ("drm/i915: s/mode/adjusted_mode/ in functions that really get
passed the adjusted_mode")
from the drm-intel tree and commit:
7e8275c2f2bb ("drm/i91
On Fri, Sep 25, 2015 at 11:46:56AM -0700, yu@intel.com wrote:
> From: Alex Dai
>
> GuC expects two bits for Render and Media domain separately when
> driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for
> Render and bit 1 is for Media domain.
>
> v2: Keep sync with code for WaRsDoub
On 2015.09.29 15:39:03 +0100, Robert Bragg wrote:
>
> - Logistically it might be more practical to contain this to the
> graphics stack.
>
> It seems fair to consider that if we can't see a very compelling
> benefit to building on perf, then containing this work to
> drivers/gpu/drm
On Tue, Sep 29, 2015 at 09:07:22PM -0400, da...@codemonkey.org.uk wrote:
> On Thu, Sep 24, 2015 at 04:26:28PM +0300, Jani Nikula wrote:
> > On Thu, 24 Sep 2015, "da...@codemonkey.org.uk"
> wrote:
> > > On Wed, Sep 23, 2015 at 11:07:56AM +, Lankhorst, Maarten wrote:
> > > > Hey,
> > > >
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