This patch includes enabling render decompression after checking all the
requirements (format, tiling, rotation etc.). Along with this, the WAs
mentioned in BSpec Workaround page have been implemented.
This patch has been implemented on top of Nabendu/Chandra's NV12 patches.
TODO:
1. Disable ster
On Fri, 4 Sep 2015 14:53:34 -0300
Danilo Cesar Lemes de Paula wrote:
> In the last few days I sent three features:
> Markdown support (patch series 1)
> Cross-reference hyperlink support (patch series 1)
> in-struct-body documentation (series 2)
>
> I assume you want a new patch series for the s
From: Alex Dai
By using information from GuC css header, we can eliminate some
hard code w.r.t size of some components of firmware.
v1: 1) guc_css_header is defined as __packed now
2) Add and correct GuC related topics in kernel/Doc
Signed-off-by: Alex Dai
---
Documentation/DocBook/drm.tm
On 09/04/2015 06:55 AM, Jani Nikula wrote:
Currently the difference between backlight control on HSW vs. BDW/SKL is
that on HSW we modify the duty cycle on the CPU register, and have the
hardware pass the changes on to the PCH registers. We still drive the
PCH PWM on both. While HSW and BDW use t
On 09/04/2015 06:55 AM, Jani Nikula wrote:
Normally we determine the backlight PWM modulation frequency (which we
also use as backlight max value) from the backlight registers at module
load time, expecting the registers have been initialized by the BIOS. If
this is not the case, we fail.
The VB
On 09/04/2015 06:55 AM, Jani Nikula wrote:
Fall back to VBT based backlight modulation frequency if it's not
set. Do not hard code.
This could be a problem if there is no VBT.
Cc: Clint Taylor
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_panel.c | 13 -
1 file chan
> > +
> > + if (fb->pixel_format == DRM_FORMAT_NV12) {
> > + int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
> > + /*
> > +* If UV starts from middle of a page, then UV start
> should
> > +* be programmed to
> > +
> > + if (((IS_SKYLAKE(dev) && intel_get_stepping(dev) == 'C') ||
> > + (IS_BROXTON(dev) && intel_get_stepping(dev) == 'A')) &&
> > + fb->pixel_format == DRM_FORMAT_NV12) {
> > + I915_WRITE(CHICKEN_PIPESL(pipe),
> > + I915_READ
> > /* Adjust (macro)pixel boundary */
> > if (fb && intel_format_is_yuv(fb->pixel_format)) {
> > - to_intel_plane_state(plane_state)->src.x1 &= ~0x1;
> > - to_intel_plane_state(plane_state)->src.x2 &= ~0x1;
> > + if (intel_rotation_90_or_270(plane_stat
> > > On Thu, Aug 27, 2015 at 01:44:06AM +, Konduru, Chandra wrote:
> > > > > > -static char intel_get_stepping(struct drm_device *dev)
> > > > > > +char intel_get_stepping(struct drm_device *dev)
> > > > >
> > > > > I guess we should have a new home for this now that it's used outside
> > > >
Properly allocate min blocks per hw requirements.
v2:
- changed helper functional param to bool, some code simplification (Ville)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_pm.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git
This patch adds NV12 to list of supported formats for
sprite plane.
v2:
- made supported format list const, fixed a leftover -1. (Ville)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 25 ++---
1 file changed, 22 insertions(
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
v3:
-cosmetic update, split checks into two (Ville)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 33 +
This patch series is adding initial NV12 support for Skylake display
after rebasing on latest drm-intel-nightly. Earlier I had two patch
series one for 0/180 and another for 90/270. Some of the patches
were already merged. This is combined series to support 0/90/180/270
and removing the ones that a
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
v2:
- minor/cosmetic changes, removed plane_state check kludge (Ville)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_pm.c | 28
1 file ch
This patch updates max supported scaler limits for NV12.
v2:
-Rebased to current kernel version 4.2.0.rc4 (me)
v3:
-simplified max_scale calculation (Ville)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_display.c | 17 +
drivers/gpu/drm/i915/intel_drv.h |
This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.
v2:
-Added helper function for need_scaling (Ville)
v3:
-Rebased to current kernel version 4.2.0.rc4 (me)
v4:
-minor updates (Ville)
Signed-off-by: Chandra
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.
v2:
- new reg defines squashed into patches used them (Ville)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/i915_reg.h |
This patch sets default initial phase and trip to scale NV12
content. In future, if needed these can be set via properties
or other means depending on incoming stream request. Until then
defaults are fine.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_display.c |7 +++
dr
This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_drv.h|1 +
drivers/gpu/drm/i915/intel_sprite.c |9 +
2 fi
Adding NV12 90/270 rotation support for primary and sprite planes.
v2:
-For 90/270 adjust pixel boundary only in Y-direction (bspec)
v3:
-Rebased (me)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 46 +++-
drivers/gpu
This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Onc
When the plane source pixel format is NV12, the CHICKEN_PIPESL
register bit 22 must be set to 1
v2:
-one wa per commit with comments, and function headers (Daniel)
v3:
-moved intel stepping helper functions to i915_drv.c (Daniel)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/i915_drv
Switching format from NV12 to RGB can result in display underrun
and corruption. This workaround sets bits 15 & 19 to 1 in
CLKGATE_DIS_PSL register to address transition underrun.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/i915_reg.h |8
drivers/gpu/drm/i915/intel_
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. On
This patch adds NV12 to list of supported formats for
primary plane.
v2:
-Rebased (me)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i91
From: chandra konduru
This patch adds kms_nv12 test case. It covers testing NV12
in linear/tile-X/tile-Y tiling formats in 0/90/180/270
orientations. For each tiling format, it tests several
combinations of planes and its scaling.
v2:
-Added 90/270 tests (me)
-took out crc test as it isn't addin
OK, thank you for your help.
Regards,
David
-Original Message-
From: Vivi, Rodrigo [mailto:rodrigo.v...@intel.com]
Sent: 04 September 2015 23:06
To: matts...@gmail.com; rodrigo.v...@gmail.com; hupernikao...@gmail.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] Request L
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