Paulo Zanoni writes:
> From: Chris Wilson
>
> Delay the expensive read on the FPGA_DBG register from once per mmio to
> once per forcewake section when we are doing the general wellbeing
> check rather than the targetted error detection. This almost reduces
> the overhead of the debug facility (
On Thu, Sep 03, 2015 at 11:30:07AM +, Jindal, Sonika wrote:
> Reviewed-by: Sonika Jindal
>
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Kumar, Mahesh
> Sent: Thursday, September 3, 2015 4:17 PM
> To: intel-gfx@lists.freedeskto
On Thu, Sep 03, 2015 at 06:33:25PM +, Konduru, Chandra wrote:
>
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > Vetter
> > Sent: Wednesday, September 02, 2015 1:02 AM
> > To: Konduru, Chandra
> > Cc: Daniel Vetter; intel-gfx@lists
On Thu, Sep 03, 2015 at 03:25:04PM +0300, Jani Nikula wrote:
> On Wed, 02 Sep 2015, Daniel Vetter wrote:
> > On Tue, Sep 01, 2015 at 01:16:49PM +0300, Jani Nikula wrote:
> >> On Thu, 27 Aug 2015, Sivakumar Thulasimani
> >> wrote:
> >> > From: "Thulasimani,Sivakumar"
> >> >
> >> > Compliance req
On Thu, Aug 27, 2015 at 01:13:31PM +0200, Maarten Lankhorst wrote:
> connector->encoder is initialized as NULL. Fix this by setting it in
> during pre enable. MST connectors are not read out during initial hw
> readout, and have no fixed encoder mappings. So it's harmless to
> return false when the
On Thu, Sep 03, 2015 at 09:48:03PM +0100, Chris Wilson wrote:
> On Thu, Sep 03, 2015 at 07:22:18PM +0200, Michał Winiarski wrote:
> > + pts = kcalloc(pdpes * BITS_TO_LONGS(I915_PDES),
> > + sizeof(unsigned long), GFP_TEMPORARY);
>
> Something to remember is that kcalloc is writte
On Fri, Sep 04, 2015 at 09:40:17AM +0300, Jani Nikula wrote:
> On Fri, 04 Sep 2015, "Yang, Libin" wrote:
> >> -Original Message-
> >> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> >> Daniel Vetter
> >> Sent: Wednesday, September 02, 2015 8:18 PM
> >> To: Yang, Libin
>
On Thu, Sep 03, 2015 at 01:24:45PM +0200, David Henningsson wrote:
> To make kernel-doc happy, the i915_audio_component_audio_ops struct
> cannot be nested.
>
> Signed-off-by: David Henningsson
> ---
>
> Note that I didn't do the same un-nesting for i915_audio_component_ops.
> This is to make it
On Thu, Sep 03, 2015 at 02:38:00PM -0700, Rodrigo Vivi wrote:
> Unless future specs tells otherwise we can assume future gens
> inherit some stuff from the previous so let's handle
> missed cases when we know tehy should't be there and assume
> default equals newest one.
>
> No functional changes.
On Wed, Sep 02, 2015 at 03:52:35PM -0700, yu@intel.com wrote:
> From: Alex Dai
>
> By using information from GuC css header, we can eliminate some
> hard code w.r.t size of some components of firmware.
>
> Signed-off-by: Alex Dai
> ---
> drivers/gpu/drm/i915/intel_guc.h| 2 +-
> d
On Thu, Sep 03, 2015 at 10:05:27AM +0100, Thomas Wood wrote:
> Signed-off-by: Thomas Wood
Bit more commit message would be good, just copypaste the debug output ;-)
lgtm otherwise on the patch series.
-Daniel
> ---
> tests/gem_storedw_loop.c | 13 +++--
> 1 file changed, 11 insertions(+
On Thu, Sep 03, 2015 at 05:56:20PM +0300, Mika Kuoppala wrote:
> "Zanoni, Paulo R" writes:
>
> > Em Qui, 2015-09-03 às 13:01 +0100, Chris Wilson escreveu:
> >> A small, very small, step to sharing the duplicate code between
> >> execlists and legacy submission engines, starting with the ringbuffe
On Thu, Sep 03, 2015 at 11:16:06AM +0300, Jani Nikula wrote:
> The remaining patches from [1] rebased on top of current nightly for
> convenience. Just s/intel_dp_tps3_supported/drm_dp_tps3_supported/g.
Thanks for rebasing, all applied to dinq.
-Daniel
>
> BR,
> Jani.
>
> [1]
> http://mid.gman
On Thu, Sep 03, 2015 at 04:41:59PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 03, 2015 at 04:24:36PM +0300, Imre Deak wrote:
> > These registers exist only before GEN5, so currently we may access
> > undefined registers on VLV/CHV and BXT. Apply the workaround only pre
> > GEN5.
> >
> > Since the w
On Wed, Aug 19, 2015 at 06:02:22PM -0700, Chandra Konduru wrote:
> Properly allocate min blocks per hw requirements.
>
> Signed-off-by: Chandra Konduru
> ---
> drivers/gpu/drm/i915/intel_pm.c | 39
> +--
> 1 file changed, 37 insertions(+), 2 deletions(-)
>
On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote:
> From: Chris Wilson
>
> Delay the expensive read on the FPGA_DBG register from once per mmio to
> once per forcewake section when we are doing the general wellbeing
> check rather than the targetted error detection. This almost reduce
On Wed, Aug 19, 2015 at 06:02:23PM -0700, Chandra Konduru wrote:
> This patch swaps src width and height for dbuf/wm calculations
> when rotation is 90/270 as per hw requirements.
The spec is rather unclear about this. It only says:
"If plane 90 or 270 rotation is enabled, use the rotated width an
On Thu, Sep 03, 2015 at 09:50:16PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The pfit state is stored as register values, so dump them as hex instead
> of decimal to make some sense of the error messages.
>
> Signed-off-by: Ville Syrjälä
Picked just this one because
On Wed, Aug 19, 2015 at 06:02:24PM -0700, Chandra Konduru wrote:
> This patch adds register definitions for skylake
> display NV12 support.
>
> Signed-off-by: Chandra Konduru
> ---
> drivers/gpu/drm/i915/i915_reg.h | 27 +++
> 1 file changed, 27 insertions(+)
>
> diff
Daniel Vetter writes:
> On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote:
>> From: Chris Wilson
>>
>> Delay the expensive read on the FPGA_DBG register from once per mmio to
>> once per forcewake section when we are doing the general wellbeing
>> check rather than the targetted erro
On Thu, Sep 03, 2015 at 11:06:38AM +0100, Arun Siluvery wrote:
> On 02/09/2015 12:29, Chris Wilson wrote:
> >Fixes regression from
> >commit f1afe24f0e736b9d7f2275e2b1504af3fe612f2a
> >Author: Arun Siluvery
> >Date: Tue Aug 4 16:22:20 2015 +0100
> >
> > drm/i915: Change SRM, LRM instructions
On Wed, Aug 19, 2015 at 06:02:25PM -0700, Chandra Konduru wrote:
> This patch sets appropriate scaler mode for NV12 format.
> In this mode, skylake scaler does either chroma-upsampling or
> chroma-upsampling and resolution scaling.
>
> Signed-off-by: Chandra Konduru
> ---
> drivers/gpu/drm/i915/
On Thu, 03 Sep 2015, Imre Deak wrote:
> These registers exist only before GEN5, so currently we may access
> undefined registers on VLV/CHV and BXT. Apply the workaround only pre
> GEN5.
>
> Since the workaround is relevant only when LVDS is present, for clarity
> apply it only if this is the case
On Fri, Sep 04, 2015 at 11:40:26AM +0300, Mika Kuoppala wrote:
> Daniel Vetter writes:
>
> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote:
> >> From: Chris Wilson
> >>
> >> Delay the expensive read on the FPGA_DBG register from once per mmio to
> >> once per forcewake section wh
On Wed, Aug 19, 2015 at 06:02:26PM -0700, Chandra Konduru wrote:
> This patch stages a scaler request when input format
> is NV12. The same scaler does both chroma-upsampling
> and resolution scaling as needed.
>
> v2:
> -Added helper function for need_scaling (Ville)
>
> v3:
> -Rebased to curren
On Wed, Aug 19, 2015 at 06:02:27PM -0700, Chandra Konduru wrote:
> This patch adds NV12 to format_is_yuv() function
> and made it available for both primary and sprite
> planes.
>
> v2:
> -Use intel_ prefix for format_is_yuv (Ville)
>
> Signed-off-by: Chandra Konduru
Reviewed-by: Ville Syrjälä
On Wed, Aug 19, 2015 at 06:02:28PM -0700, Chandra Konduru wrote:
> This patch updates max supported scaler limits for NV12.
>
> v2:
> -Rebased to current kernel version 4.2.0.rc4 (me)
>
> Signed-off-by: Chandra Konduru
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 +
> drivers
On Wed, Aug 19, 2015 at 06:02:30PM -0700, Chandra Konduru wrote:
> This patch adds NV12 to list of supported formats for
> sprite plane.
>
> Signed-off-by: Chandra Konduru
> Testcase: igt/kms_nv12
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 23 +--
> 1 file changed, 21 in
Remove quick_dump as it has been replaced by the intel_reg tool and move
the register definition files to tools/registers.
Signed-off-by: Thomas Wood
---
README | 13 ---
configure.ac | 27 +
man/intel_reg.rs
On 2015-09-04 10:03, Daniel Vetter wrote:
Also please use the new inline style for struct members.
I tried that, but I couldn't get it to work. This was with Takashi's
for-next tree, do I need to apply some docbook special patches on top of
that to get the new functionality?
--
David Henn
On Wed, Aug 19, 2015 at 06:02:31PM -0700, Chandra Konduru wrote:
> This patch adds NV12 as supported format to
> intel_framebuffer_init and performs various checks.
>
> v2:
> -Fix an issue in checks added (me)
>
> Signed-off-by: Chandra Konduru
> Testcase: igt/kms_nv12
> ---
> drivers/gpu/drm/i
On Fri, 04 Sep 2015 12:33:45 +0200,
David Henningsson wrote:
>
>
>
> On 2015-09-04 10:03, Daniel Vetter wrote:
> > Also please use the new inline style for struct members.
>
> I tried that, but I couldn't get it to work. This was with Takashi's
> for-next tree, do I need to apply some docbook
On Wed, Aug 19, 2015 at 06:02:32PM -0700, Chandra Konduru wrote:
> This patch is adding NV12 support to skylake primary plane
> programming. It is covering linear/X/Y/Yf tiling formats
> for 0 and 180 rotations.
>
> For 90/270 rotation, Y and UV subplanes should be treated
> as separate surfaces a
On Wed, Aug 19, 2015 at 06:02:34PM -0700, Chandra Konduru wrote:
> This patch sets default initial phase and trip to scale NV12
> content. In future, if needed these can be set via properties
> or other means depending on incoming stream request. Until then
> defaults are fine.
We should set it ac
On Wed, Aug 19, 2015 at 06:02:35PM -0700, Chandra Konduru wrote:
> Adding driver workarounds for nv12.
>
> Signed-off-by: Chandra Konduru
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20
> drivers/gpu/drm/i915/intel_csr.c |2 +-
> drivers/gpu/drm/i915/intel_displ
On Wed, Aug 19, 2015 at 06:02:36PM -0700, Chandra Konduru wrote:
> Adding NV12 90/270 rotation support for primary and sprite planes.
>
> v2:
> -For 90/270 adjust pixel boundary only in Y-direction (bspec)
>
> v3:
> -Rebased (me)
>
> Signed-off-by: Chandra Konduru
> Testcase: igt/kms_nv12
> ---
On Fri, Sep 04, 2015 at 11:22:28AM +0100, Thomas Wood wrote:
> Remove quick_dump as it has been replaced by the intel_reg tool and move
> the register definition files to tools/registers.
>
> Signed-off-by: Thomas Wood
NAK
It's the only tool that works on VLV/CHV reasonably.
> ---
> README
Daniel Vetter writes:
> On Fri, Sep 04, 2015 at 11:40:26AM +0300, Mika Kuoppala wrote:
>> Daniel Vetter writes:
>>
>> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote:
>> >> From: Chris Wilson
>> >>
>> >> Delay the expensive read on the FPGA_DBG register from once per mmio to
>>
Paulo Zanoni writes:
> I added this code on 8664281b64c457705db72fc60143d03827e75ca9, on
> April 12 2013. Back then, we only had support for detecting unclaimed
> registers on I915_WRITE operations, and we didn't have the
> i915.mmio_debug infrastructure.
>
> I tried to remember exactly why I add
On Fri, Sep 04, 2015 at 02:38:41PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 04, 2015 at 11:22:28AM +0100, Thomas Wood wrote:
> > Remove quick_dump as it has been replaced by the intel_reg tool and move
> > the register definition files to tools/registers.
> >
> > Signed-off-by: Thomas Wood
>
>
On Fri, 04 Sep 2015, Thomas Wood wrote:
> Remove quick_dump as it has been replaced by the intel_reg tool and move
> the register definition files to tools/registers.
>
> Signed-off-by: Thomas Wood
Acked-by: Jani Nikula
As a follow-up, I'd like it if Someone(tm) would add rules to install
the
On Fri, 04 Sep 2015, Ville Syrjälä wrote:
> On Fri, Sep 04, 2015 at 11:22:28AM +0100, Thomas Wood wrote:
>> Remove quick_dump as it has been replaced by the intel_reg tool and move
>> the register definition files to tools/registers.
>>
>> Signed-off-by: Thomas Wood
>
> NAK
>
> It's the only too
Also check for correct revision id in each Gen9 platform (SKL until B0
and BXT until A0).
Cc: Nick Hoath
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/
When WaEnableForceRestoreInCtxtDescForVCS is required, it is only
safe to send new contexts if the last reported event is "active to
idle". Otherwise the same context can fully preempt itself because
lite-restore is disabled.
Testcase: igt/gem_concurrent_blit
Reported-by: Daniele Ceraolo Spurio
S
Mika Kuoppala writes:
> Daniel Vetter writes:
>
>> On Fri, Sep 04, 2015 at 11:40:26AM +0300, Mika Kuoppala wrote:
>>> Daniel Vetter writes:
>>>
>>> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote:
>>> >> From: Chris Wilson
>>> >>
>>> >> Delay the expensive read on the FPGA_DBG
On Thu, 27 Aug 2015, Clint Taylor wrote:
> On 08/26/2015 12:58 AM, Jani Nikula wrote:
>> Normally we determine the backlight PWM modulation frequency (which we
>> also use as backlight max value) from the backlight registers at module
>> load time, expecting the registers have been initialized by
On Fri, 04 Sep 2015, Jani Nikula wrote:
> On Thu, 27 Aug 2015, Clint Taylor wrote:
>> On 08/26/2015 12:58 AM, Jani Nikula wrote:
>>> Normally we determine the backlight PWM modulation frequency (which we
>>> also use as backlight max value) from the backlight registers at module
>>> load time, ex
This is to allow live status check for HDMI as well.
Also, using intel_encoder->hpd_pin to check the live status
for bxt because of BXT A0/A1 WA for HPD pins.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_dp.c | 11 +++
drivers/gpu/drm/i915/intel_drv.h |2 ++
2 files
This series adds changes in HDMI detection methods and also afew
optimization. The overview of changes are:
1. HDMI EDID is read only at the hot-plug time.
2. EDID is cached in connectoer on hotplug,and released from cache only
on the hot-unplug.
3. In between, for all detetct calls, only cached
From: Durgadoss R
Currently, HDMI hotplug with eDP as local panel is failing
because the HDMI hpd is detected as a long hpd for eDP; and is
thus rightfully ignored. But, it should really be handled as
an interrupt on port B for HDMI (due to BXT A1 platform having
HPD pins A and B swapped). This p
Em Sex, 2015-09-04 às 09:53 +0300, Mika Kuoppala escreveu:
> Paulo Zanoni writes:
>
> > The unclaimed register bit is only triggered when someone touches
> > the
> > specified register range.
> >
>
> I got the impression that we get the unclaimed access also
> for other ranges, if they are pow
Em Sex, 2015-09-04 às 10:02 +0300, Mika Kuoppala escreveu:
> Paulo Zanoni writes:
>
> > From: Chris Wilson
> >
> > Delay the expensive read on the FPGA_DBG register from once per
> > mmio to
> > once per forcewake section when we are doing the general wellbeing
> > check rather than the target
From: Shashank Sharma
This patch adds a separate probe function for HDMI
EDID read over DDC channel. This function has been
registered as a .hot_plug handler for HDMI encoder.
The current implementation of hdmi_detect()
function re-sets the cached HDMI edid (in connector->detect_edid) in
every d
The Bspec is very clear that Live status must be checked about before
trying to read EDID over DDC channel. This patch makes sure that HDMI
EDID is read only when live status us up.
The live status doesn't seem to perform very consistent across various
platforms when tested with different monitors
If the same port is enumerated as hdmi as well as DP, this will get
called for DP connector as well which is not required because
i915_hotplug_work_func is solely to handle hdmi HPD.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_hotplug.c |3 ++-
1 file changed, 2 insertions(+)
From: Shashank Sharma
This patch adds the intel_connector initialized to intel_hdmi
display, during the init phase, just like the other encoders do.
This attachment is very useful when we need to extract the connector
pointer during the hotplug handler function
Signed-off-by: Shashank Sharma
--
Em Sex, 2015-09-04 às 11:40 +0300, Mika Kuoppala escreveu:
> Daniel Vetter writes:
>
> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote:
> > > From: Chris Wilson
> > >
> > > Delay the expensive read on the FPGA_DBG register from once per
> > > mmio to
> > > once per forcewake sec
Extend init/init_hw split to context init.
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- Move default context initialisation to logical_ring_init
Rename intel_lr_context_deferred_create to
intel_lr
Normally we determine the backlight PWM modulation frequency (which we
also use as backlight max value) from the backlight registers at module
load time, expecting the registers have been initialized by the BIOS. If
this is not the case, we fail.
The VBT contains the backlight modulation frequency
Fall back to VBT based backlight modulation frequency if it's not
set. Do not hard code.
This could be a problem if there is no VBT.
Cc: Clint Taylor
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_panel.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/
Currently the difference between backlight control on HSW vs. BDW/SKL is
that on HSW we modify the duty cycle on the CPU register, and have the
hardware pass the changes on to the PCH registers. We still drive the
PCH PWM on both. While HSW and BDW use the same LPT PCH, BDW does not
pass these mess
On Fri, Sep 04, 2015 at 01:38:07PM +, Zanoni, Paulo R wrote:
> Em Sex, 2015-09-04 às 09:53 +0300, Mika Kuoppala escreveu:
> > Paulo Zanoni writes:
> >
> > > The unclaimed register bit is only triggered when someone touches
> > > the
> > > specified register range.
> > >
> >
> > I got the i
"Zanoni, Paulo R" writes:
> Em Sex, 2015-09-04 às 11:40 +0300, Mika Kuoppala escreveu:
>> Daniel Vetter writes:
>>
>> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote:
>> > > From: Chris Wilson
>> > >
>> > > Delay the expensive read on the FPGA_DBG register from once per
>> > >
From: Tvrtko Ursulin
We had two failure modes here:
1.
Deadlock in intelfb_alloc failure path where it calls
drm_framebuffer_remove, which grabs the struct mutex and intelfb_create
(caller of intelfb_alloc) was already holding it.
2.
Deadlock in intelfb_create failure path where it calls
drm_fr
Hi Jani,
On Mon, Aug 31, 2015 at 10:15:07PM +0300, Jani Nikula wrote:
> On Sat, 29 Aug 2015, Lukas Wunner wrote:
> > the patch set I've posted August 12 included 3 commits which fix bugs
> > in i915. These bugs should be fixed independently of MacBook Pro GPU
> > switching, please consider mergin
Currently when allocating a framebuffer fails, the gem object gets
unrefed at the bottom of the call chain in __intel_framebuffer_create,
not where it gets refed, which is in intel_framebuffer_create_for_mode
(via i915_gem_alloc_object) and in intel_user_framebuffer_create
(via drm_gem_object_looku
2015-09-04 10:57 GMT-03:00 Mika Kuoppala :
> "Zanoni, Paulo R" writes:
>
>> Em Sex, 2015-09-04 às 11:40 +0300, Mika Kuoppala escreveu:
>>> Daniel Vetter writes:
>>>
>>> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote:
>>> > > From: Chris Wilson
>>> > >
>>> > > Delay the expensive
Install the register definition files and use them by default in
intel_reg.
Suggested-by: Jani Nikula
Signed-off-by: Thomas Wood
---
configure.ac| 5 +++--
tools/Makefile.am | 2 +-
tools/intel_reg.c | 4 +++-
tools/registers/Makefile.am | 3 ++-
4 files chan
Hello Rodrigo/Matt,
Running:
lspci -ns :00:02.0 | awk -F: '{ print $4 }'
returns:
a001 (rev 02)
I’m not very familiar with “build”.
and build your self following:
https://01.org/linuxgraphics/documentation/build-guide-0
If I follow all steps in above link, will I get a de
On Fri, Sep 04, 2015 at 06:56:15PM +0530, Sonika Jindal wrote:
> If the same port is enumerated as hdmi as well as DP, this will get
> called for DP connector as well which is not required because
> i915_hotplug_work_func is solely to handle hdmi HPD.
>
> Signed-off-by: Sonika Jindal
> ---
> dri
On Fri, Sep 04, 2015 at 06:56:12PM +0530, Sonika Jindal wrote:
> From: Shashank Sharma
>
> This patch adds a separate probe function for HDMI
> EDID read over DDC channel. This function has been
> registered as a .hot_plug handler for HDMI encoder.
>
> The current implementation of hdmi_detect()
On Fri, Sep 04, 2015 at 06:56:14PM +0530, Sonika Jindal wrote:
> The Bspec is very clear that Live status must be checked about before
> trying to read EDID over DDC channel. This patch makes sure that HDMI
> EDID is read only when live status us up.
>
> The live status doesn't seem to perform ver
On Fri, Sep 04, 2015 at 03:18:14PM +0300, Mika Kuoppala wrote:
> Mika Kuoppala writes:
>
> > Daniel Vetter writes:
> >
> >> On Fri, Sep 04, 2015 at 11:40:26AM +0300, Mika Kuoppala wrote:
> >>> Daniel Vetter writes:
> >>>
> >>> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote:
> >
On Fri, Sep 04, 2015 at 11:53:36AM +0300, Ville Syrjälä wrote:
> On a further note, this function could use some cleaning to move
> various variables into narrower scope. Now it's rather hard to see what
> is valid per iteration and what is valid across the entire loop.
It's also rather big, so mi
On Fri, Sep 04, 2015 at 02:09:41PM +0300, Ville Syrjälä wrote:
> Really, someone should just finally fix the mess we have made with handling
> different types of planes in totally different ways and unify things as
> much as possible.
Yeah I want universal planes for skl finally, and I'd like to h
On Fri, Sep 04, 2015 at 04:53:28PM +0200, Daniel Vetter wrote:
> On Fri, Sep 04, 2015 at 03:18:14PM +0300, Mika Kuoppala wrote:
> > Mika Kuoppala writes:
> >
> > > Daniel Vetter writes:
> > >
> > >> On Fri, Sep 04, 2015 at 11:40:26AM +0300, Mika Kuoppala wrote:
> > >>> Daniel Vetter writes:
> >
On Fri, Sep 04, 2015 at 06:16:19PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 04, 2015 at 04:53:28PM +0200, Daniel Vetter wrote:
> > On Fri, Sep 04, 2015 at 03:18:14PM +0300, Mika Kuoppala wrote:
> > > Mika Kuoppala writes:
> > >
> > > > Daniel Vetter writes:
> > > >
> > > >> On Fri, Sep 04, 2015
On Fri, Sep 04, 2015 at 06:16:19PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 04, 2015 at 04:53:28PM +0200, Daniel Vetter wrote:
> > On Fri, Sep 04, 2015 at 03:18:14PM +0300, Mika Kuoppala wrote:
> > > Mika Kuoppala writes:
> > >
> > > > Daniel Vetter writes:
> > > >
> > > >> On Fri, Sep 04, 2015
Install the register definition files and use them by default in
intel_reg.
v2: remove redundant path check
Suggested-by: Jani Nikula
Signed-off-by: Thomas Wood
---
configure.ac| 5 +++--
tools/Makefile.am | 2 +-
tools/intel_reg.c | 4 ++--
tools/registers/
On Fri, 2015-09-04 at 21:41 +0700, David Ho wrote:
> Hello Rodrigo/Matt,
>
> Running:
> lspci -ns :00:02.0 | awk -F: '{ print $4 }'
>
> returns:
> a001 (rev 02)
Yes, it is supported. Definitely a Pineview.
>
> I’m not very familiar with “build”.
SO it is probably not recommended option
On 04/09/15 12:59, Michel Thierry wrote:
When WaEnableForceRestoreInCtxtDescForVCS is required, it is only
safe to send new contexts if the last reported event is "active to
idle". Otherwise the same context can fully preempt itself because
lite-restore is disabled.
Testcase: igt/gem_concurrent_
I've been carrying something looking rougly like this patchset around
internally for a long time now, and with SKL out there now, I figured
it's time to get it posted and start the process of integration.
David is working on pulling over most of the "driver based PASID
handling" and other code int
This simplifies the sync code quite a bit. I don't think we'll be able
to get away with using the core fence code's seqno support, since we'll
be moving away from simple seqno comparisions with the scheduler and
preemption, but the additional code is pretty minimal anyway, and lets
us add addition
We just need to pass in an address to execute and some flags, since we
don't have to worry about buffer relocation or any of the other usual
stuff. Returns a fence to be used for synchronization.
---
drivers/gpu/drm/i915/i915_dma.c| 140 -
drivers/gpu/drm/i
For passing flags (e.g. SVM) when creating a context.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_dma.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_context.c | 63 +++--
include/uapi/drm/i915_drm.h
For use by other modules.
Signed-off-by: Jesse Barnes
---
drivers/misc/sgi-gru/grutlbpurge.c | 19 ---
include/linux/mmu_notifier.h | 8
mm/mmu_notifier.c | 19 +++
3 files changed, 27 insertions(+), 19 deletions(-)
diff --git a/d
From: Maarten Lankhorst
This allows users of dma fences to create a android fence.
Cc: Daniel Vetter
Cc: Jesse Barnes
Signed-off-by: Maarten Lankhorst
---
drivers/staging/android/sync.c | 13 +
drivers/staging/android/sync.h | 3 ++-
2 files changed, 11 insertions(+), 5 deletion
New file with VT-d SVM and PASID handling functions and page table
management. This belongs in the IOMMU code (along with some extra bits
for waiting for invalidations and page faults to complete, flushing the
device IOTLB, etc.)
FIXME:
need work queue for re-submitting contexts
TE bit handli
Allow for sync point exposure in the i915 driver. This
There are a couple of goals here:
1) allow applications and libraries to create fences without an
associated buffer
2) re-use a common API so userspace doesn't have to impedance mismatch
between different driver implementations
For signaling tasks from drivers.
---
kernel/signal.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/signal.c b/kernel/signal.c
index 0f6bbbe..9122aa2 100644
--- a/kernel/signal.c
+++ b/kernel/signal.c
@@ -1227,6 +1227,7 @@ force_sig_info(int sig, struct siginfo *info, struct
task_str
---
drivers/staging/android/sync.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/staging/android/sync.c b/drivers/staging/android/sync.c
index 7f0e919..858278d 100644
--- a/drivers/staging/android/sync.c
+++ b/drivers/staging/android/sy
On Fri, Sep 04, 2015 at 09:58:54AM -0700, Jesse Barnes wrote:
> A few things to think about:
> - how to signal GPU hangs with the new execbuf (a signal might be more
> natural as the execution appears more CPU-like? what state do we
> have to worry about restoring for bufferless contexts
On Fri, Sep 04, 2015 at 09:59:03AM -0700, Jesse Barnes wrote:
> We just need to pass in an address to execute and some flags, since we
> don't have to worry about buffer relocation or any of the other usual
> stuff. Returns a fence to be used for synchronization.
There is no need for a flush+fenc
On 09/02/2015 11:15 AM, Jonathan Corbet wrote:
> On Tue, 1 Sep 2015 14:57:33 -0300
> Danilo Cesar Lemes de Paula wrote:
>
>> Did you find time to check this patch? As you mentioned that you applied
>> the Markdown support for the linux-next tree, this patch might be needed
>> (maybe "wanted" is a
the crtc id is now always equivalent to its index in the array of crtcs
returned by the kernel
---
tests/drm_read.c | 43 +--
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/tests/drm_read.c b/tests/drm_read.c
index b808bed..ab7e4ef 100644
-
the crtc id is now always equivalent to its index in the array of crtcs
returned by the kernel
---
overlay/Makefile.am | 4 ++--
overlay/kms/kms-overlay.c | 7 ++-
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/overlay/Makefile.am b/overlay/Makefile.am
index c648875..c82
This function uses an intel-specific ioctl to fetch a mapping between pipes and
crtc ids, but this technique is outdated as the crtc id is now always
equivalent to its index in the array of crtcs returned by the kernel.
---
lib/igt_kms.c | 33 -
1 file changed, 24
This patchset removes the code that looks up a pipe number from a crtc ID. The
pipe number is equivalent to the index of the crtc in the array of crtcs
returned by the kernel for a drmModeGetResources() call. This may not have
been the case when these lookups were written, but it is the de facto
On 09/04/2015 10:23 AM, Chris Wilson wrote:
> On Fri, Sep 04, 2015 at 09:58:54AM -0700, Jesse Barnes wrote:
>> A few things to think about:
>> - how to signal GPU hangs with the new execbuf (a signal might be more
>> natural as the execution appears more CPU-like? what state do we
>> hav
On 09/04/2015 10:37 AM, Chris Wilson wrote:
> On Fri, Sep 04, 2015 at 09:59:03AM -0700, Jesse Barnes wrote:
>> We just need to pass in an address to execute and some flags, since we
>> don't have to worry about buffer relocation or any of the other usual
>> stuff. Returns a fence to be used for sy
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