On Wed, Sep 02, 2015 at 02:50:52PM +0100, Graham Whaley wrote:
> (RFC/test - not for merging)
> The below is a test of moving the large HTML KMS properties table out
> to markdown style in the appropriate files.
> In the test we only use the first few rows of the existing KMS table
> an example.
>
On Wed, Sep 02, 2015 at 04:22:56PM +0200, Maarten Lankhorst wrote:
> Op 02-09-15 om 13:15 schreef Ville Syrjälä:
> > On Wed, Sep 02, 2015 at 01:08:31PM +0200, Maarten Lankhorst wrote:
> >> Op 02-09-15 om 12:35 schreef Ville Syrjälä:
> >>> On Wed, Sep 02, 2015 at 07:15:25AM +0200, Maarten Lankhorst
On Wed, 02 Sep 2015 17:22:01 +0200,
Daniel Vetter wrote:
>
> On Wed, Sep 02, 2015 at 03:46:40PM +0200, Takashi Iwai wrote:
> > On Wed, 02 Sep 2015 15:44:34 +0200,
> > Jani Nikula wrote:
> > >
> > > On Wed, 02 Sep 2015, Takashi Iwai wrote:
> > > > On Wed, 02 Sep 2015 11:02:42 +0200,
> > > > Jani
These registers exist only before GEN5, so currently we may access
undefined registers on VLV/CHV and BXT. Apply the workaround only pre
GEN5.
This triggered an unclaimed register access warning on BXT.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_bios.c | 2 +-
1 file changed, 1 ins
On each call to gen8_alloc_va_range_3lvl we're allocating temporary
bitmaps needed for error handling. Unfortunately, when we increase
address space size (48b ppgtt) we do additional (512 - 4) calls to
kcalloc, increasing latency between exec and actual start of execution
on the GPU. Let's just do
On Wed, Sep 02, 2015 at 05:46:38PM +0200, Michał Winiarski wrote:
> + pts = kcalloc(pdpes * BITS_TO_LONGS(I915_PDES),
> + sizeof(unsigned long), GFP_TEMPORARY);
> + if (!pts)
> + goto err_out;
This is the oddly aligned bracket!
-Chris
--
Chris Wilson, Inte
Damien,
You reviewed v1 and then went on vacation for v2. Any chance you can
review v2?
Thanks,
Bob
On Tue, 21 Jul 2015 10:42:53 -0700
Bob Paauwe wrote:
> Clearing the watermarks for all pipes/planes when updating the
> watermarks for a single CRTC change seems like the wrong thing to
> do he
On Wed, 2015-09-02 at 18:16 +0700, David Ho wrote:
> Dear Rodrigo,
Hi David,
I just paid attention to the subject and notice you are looking for
driver for GMA 3150. I'm not sure, but I'm afraid this platform doesn't
have the GPU supported by our open source driver.
Probably the GMA 3150 will be
On Wed, Sep 02, 2015 at 06:36:35PM +0300, Imre Deak wrote:
> These registers exist only before GEN5, so currently we may access
> undefined registers on VLV/CHV and BXT. Apply the workaround only pre
> GEN5.
>
> This triggered an unclaimed register access warning on BXT.
>
> Signed-off-by: Imre D
The following commit was bisected and tested to be the first bad commit which
causes the warning as seen below at a ThinkPad T40s:
commit a1b2278e4dfcd2dbea85e319ebf73a6b7b2f180b
Author: Chandra Konduru
Date: Tue Apr 7 15:28:45 2015 -0700
drm/i915: skylake panel fitting using shared sca
Em Qua, 2015-08-26 às 08:44 +0100, Chris Wilson escreveu:
> On Tue, Aug 25, 2015 at 07:03:42PM -0300, Paulo Zanoni wrote:
> > The unclaimed register bit is only triggered when someone touches
> > the
> > specified register range.
> >
> > For the normal use case (with i915.mmio_debug=0), this comm
>> Sep 2 18:10:26 t44 kernel: [drm:check_crtc_state [i915]] *ERROR* mismatch
>> in ips_enabled (expected 1, found 0)
It is due to ips_enabled mismatch in crtc_state.
I can't think how below patch is triggering mismatch in ips_enabled.
> -Original Message-
> From: Toralf Förster [mailt
On Wed, Sep 02, 2015 at 08:20:52PM +, Zanoni, Paulo R wrote:
> Em Qua, 2015-08-26 às 08:44 +0100, Chris Wilson escreveu:
> > On Tue, Aug 25, 2015 at 07:03:42PM -0300, Paulo Zanoni wrote:
> > > The unclaimed register bit is only triggered when someone touches
> > > the
> > > specified register
2015-09-02 17:53 GMT-03:00 ch...@chris-wilson.co.uk :
> On Wed, Sep 02, 2015 at 08:20:52PM +, Zanoni, Paulo R wrote:
>> Em Qua, 2015-08-26 às 08:44 +0100, Chris Wilson escreveu:
>> > On Tue, Aug 25, 2015 at 07:03:42PM -0300, Paulo Zanoni wrote:
>> > > The unclaimed register bit is only triggere
2015-09-02 17:53 GMT-03:00 ch...@chris-wilson.co.uk :
> On Wed, Sep 02, 2015 at 08:20:52PM +, Zanoni, Paulo R wrote:
>> Em Qua, 2015-08-26 às 08:44 +0100, Chris Wilson escreveu:
>> > On Tue, Aug 25, 2015 at 07:03:42PM -0300, Paulo Zanoni wrote:
>> > > The unclaimed register bit is only triggere
This is another case where we can consider the default is the
newest available and not actually a missed case.
No functional change.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drive
Unless future specs tells otherwise we can assume future gens
inherit some stuff from the previous so let's handle
missed cases when we know tehy should't be there and assume
default equals newest one.
No functional changes.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_uncore.c |
These functions are already being called for gen >= 9,
so let's be sure when this happens we use whatever is
there already for the latest platform.
No functional change.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_irq.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Hi all,
We suspect watermark has problem in kernel 3.14,
Does anyone have a new watermark patch for 3.14 similar as below patch:
http://patchwork.freedesktop.org/bundle/anderco/matt-watermarks/
Thanks
William
___
Intel-gfx mailing list
Intel-gfx@lists.f
Hi all,
Can anyone educate me if water mark update need to wait for next VSYNC?
In other words, if we flip a frame to overlay for the first time,
it will be showed in the next VBlank as water mark update needs to wait for
that?
Is this true or a bug?
Thanks
William
_
From: Alex Dai
Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE
status is a reliable readiness flag only when resuming from RC6.
This fix a racing issue that allocation of doorbell fails whilst
GuC init is not finished.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_
From: Alex Dai
By using information from GuC css header, we can eliminate some
hard code w.r.t size of some components of firmware.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc.h| 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 36 +
drivers/gpu/drm/i915/inte
)
Caused by commit
a317290af0db ("drm/atomic: Make prepare_fb/cleanup_fb only take state, v3")
Well, that was clearly never build tested :-(
I have used the drm-misc tree from next-20150902 for today.
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
On Wed, Sep 2, 2015 at 10:37 AM, Vivi, Rodrigo wrote:
> On Wed, 2015-09-02 at 18:16 +0700, David Ho wrote:
>> Dear Rodrigo,
>
> Hi David,
>
> I just paid attention to the subject and notice you are looking for
> driver for GMA 3150. I'm not sure, but I'm afraid this platform doesn't
> have the GPU
On Wed, 2015-09-02 at 18:09 -0700, Matt Turner wrote:
> On Wed, Sep 2, 2015 at 10:37 AM, Vivi, Rodrigo <
> rodrigo.v...@intel.com> wrote:
> > On Wed, 2015-09-02 at 18:16 +0700, David Ho wrote:
> > > Dear Rodrigo,
> >
> > Hi David,
> >
> > I just paid attention to the subject and notice you are lo
Dear Rodrigo,
Thank you for your help.
I'll take a look at the PCI ID.
However,
when I search GMA 3150 at 01.org, I came across this page:
https://01.org/linuxgraphics/downloads/2013q1-intel-graphics-stack-release
and also this page at Intel.com
http://www.intel.com/support/graphics/sb/cs-01051
On Wed, Sep 2, 2015 at 9:01 PM, David Ho wrote:
> Dear Rodrigo,
>
> Thank you for your help.
>
> I'll take a look at the PCI ID.
>
> However,
> when I search GMA 3150 at 01.org, I came across this page:
> https://01.org/linuxgraphics/downloads/2013q1-intel-graphics-stack-release
>
> and also this
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