>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>> That fuse may not be correct on all SKUs, but I assume you have other ways to
>recognize what kind of package it is. I originally listed out ULT and ULX,
>but it
>became more complicated with BDW.
>
>I'm not aware of any way of identi
On Tue, Aug 18, 2015 at 02:32:35PM -0700, yu@intel.com wrote:
> From: Alex Dai
>
> The firmware layout changes that now it only has css header +
> uCode + RSA signature. Plus, other trivial changes to support
> GuC V4.3.
>
> Signed-off-by: Alex Dai
Reviewed-by: Tom O'Rourke
This patch ha
On Thu, Aug 27, 2015 at 04:29:21PM -0300, Paulo Zanoni wrote:
> 2015-08-12 12:44 GMT-03:00 :
> > From: Ville Syrjälä
> >
> > Wire up the port A HPD for BDW. Compared to earlier platforms the
> > interrupt setup is a bit different, but basically everything else
> > looks the same.
> >
> > Signed-o
On Tue, Aug 18, 2015 at 02:34:47PM -0700, yu@intel.com wrote:
> From: Alex Dai
>
> If rc6 is enabled, notify GuC so it can do proper forcewake before
> command submission.
>
> Signed-off-by: Alex Dai
Reviewed-by: Tom O'Rourke
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 15 +
On Thu, Aug 27, 2015 at 07:34:41PM +, Runyan, Arthur J wrote:
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >> That fuse may not be correct on all SKUs, but I assume you have other ways
> >> to
> >recognize what kind of package it is. I originally listed out ULT and ULX,
>
On Sun, Aug 23, 2015 at 05:52:51PM +0530, Sagar Arun Kamble wrote:
> From: Alex Dai
>
[TOR:] This commit message is inadequate. The
needed information is in the cover letter but
is lacking here. Please rebase with Alex's
previous patch "drm/i915: Notify GuC rc6 state"
> Signed-off-by: Alex
2015-08-12 12:44 GMT-03:00 :
> From: Ville Syrjälä
>
> On SKL the port A HPD has moved to the PCH. Hook it up.
Today is Déjà vu day.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.c | 21 +++--
> drivers/gpu/drm/i915/i915_reg
2015-08-19 15:13 GMT-03:00 :
> From: Ville Syrjälä
>
> Runtime suspends disabled all interrupts, so in order to get them back
> fully we need to also do the HPD irq setup on runtime resume. Except
> on VLV/CHV where the display interrupt initialization is part of the
> display power well powerup.
Extend this to SKL and BXT as it's needed for these platforms as well.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 88f97
Since SKL has universal planes, we should configure the sprite planes
and the primary plane the same. For the primary plane we do enable
the pipe gamma on the plane so do the same for the non-primary planes.
Without this, the pipe CRC values will be different for something
displayed on the primar
From: Ville Syrjälä
Move the 0 initialization of pin_mask and long_mask from
intel_get_hpd_pins() into each caller. This we we can call
intel_get_hpd_pins() multiple times to accumulate more pins from several
sources.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 11 --
From: Ville Syrjälä
Second posting of the HPD port A series, with some new added goodies
at the end ;)
I tried to accomodate Paulo's review comments on v1 of the series [1]
and noticed a few other warts myself that I tried to sort out. Additonally
I added a bunch of BXT cleanups to the end, and
From: Ville Syrjälä
Indent the PORTx_HOTPLUG_... defines appropriately, and fix some space
vs. tab issues.
v2: Document pre-HSW/LPT bits, and order another tab (Paulo)
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 74 +---
From: Ville Syrjälä
Eliminate a bunch of duplicated code that calculates the currently
enabled HPD interrupt bits.
v2: s/;/:/ in patch subject (Paulo)
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 43 -
1
From: Ville Syrjälä
The PORTA HPD defines are not BXT specific. They also exist on SPT,
and partially already on LPT:LP.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 10 +-
2 files changed, 6 inse
From: Ville Syrjälä
Extract the core of ironlake_{enable,disable}_display_irq() into a new
function. We'll have further use for it later.
v2: Warn about invalid mask vs. enable bits (Paulo)
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 41 ++
From: Ville Syrjälä
Starting from SPT the only interrupts living in the south are GMBUS and
HPD. What's worse some of the SPT specific new bits conflict with some
other bits on earlier PCH generations. So better not use the
cpt_irq_handler() for SPT+ anymore.
Also kill the hand rolled port E han
From: Ville Syrjälä
bxt_hpd_handler() looks different to everyone else for no good reason.
Rewrite it to use the standard variable namees etc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 37 -
1 file changed, 16 insertions(+), 21 delet
From: Ville Syrjälä
Wire up the port A HPD for BDW. Compared to earlier platforms the
interrupt setup is a bit different, but basically everything else
looks the same.
v2: 0 initialize pin_mask/long_mask due to intel_get_hpd_pins() changes
Check for BDW before processing the HPD to not break
From: Ville Syrjälä
As with ILK/SNB wire up the port A HPD on IVB/HSW.
This might be more important on HSW with PSR. BSpec tells us that if the
automagic link training performed by the hardware fails for some reason,
we're going to get a short HPD and are supposed to re-train the link
manyally.
From: Ville Syrjälä
If the CPU and PCH are on the same package we must enabled the port A
HPD also in the south hotplug register. To identify the package type
we simply look at the PCH type: LPT-H means separate package, and
LPT-LP means multi chip package (MCP).
v2: Add comment and pimp commit
From: Ville Syrjälä
On SKL the port A HPD has moved to the PCH. Hook it up.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 21 +++--
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
2 files changed, 22 insertions(+), 3 deletions(-)
diff
From: Ville Syrjälä
ILK/SNB support port A HPD. While HPD is optional on eDP let's at least
try to wite it up so that we might notice if the link has issues.
The eDP spec suggests that if HPD is not wired up, one should poll the
link status instead. We don't even do that currently.
v2: 0 initia
From: Ville Syrjälä
Make LPT:LP checks look neater by wrapping the details in a
new HAS_PCH_LPT_LP() macro.
Reviewed-by: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 13 +
drivers/gpu/drm/i915/int
From: Ville Syrjälä
A lot of the hpd irq handling is duplicated code, so refactor it a bit
by observing that in several places the only difference is the hpd[]
array. So pull the code to a few functions and pass in the hpd[] array
from the caller. Another option would be to determine the correct
From: Ville Syrjälä
Runtime suspends disabled all interrupts, so in order to get them back
fully we need to also do the HPD irq setup on runtime resume. Except
on VLV/CHV where the display interrupt initialization is part of the
display power well powerup.
Reviewed-by: Paulo Zanoni
Signed-off-b
From: Ville Syrjälä
Rewrite the BXT hpd setup to match the way we do it on other platforms:
- Throw out BXT_HOTPLUG_CTL since it's the same as PCH_PORT_HOTPLUG
- Enable the HPD bits in the DE port IER in gen8_de_irq_postinstall()
- Update DE port IMR using bdw_update_port_irq()
Also throw out po
From: Ville Syrjälä
Pass the correct hpd[] array to intel_get_hpd_pins() on pre-g4x
platforms.
This got broken in the following commit:
commit fd63e2a972c670887e5e8a08440111d3812c0996
Author: Imre Deak
Date: Tue Jul 21 15:32:44 2015 -0700
drm/i915: combine i9xx_get_hpd_pins and pch_get_h
It requires i915 changes to add end_cpu_access().
v2: Use local definitions so older kernels fail fine.
Signed-off-by: Tiago Vignatti
---
tests/kms_mmap_write_crc.c | 82 --
1 file changed, 72 insertions(+), 10 deletions(-)
diff --git a/tests/kms_mma
From: Rob Bradford
This test has the following subtests:
- test_correct for correctness of the data
- test_map_unmap checks for mapping idempotency
- test_reprime checks for dma-buf creation idempotency
- test_forked checks for multiprocess access
- test_refcounting checks for buffer referen
This patch moves userptr definitions and helpers implementation that were
locally in gem_userptr_benchmark and gem_userptr_blits to the library, so other
tests can make use of them as well. There's no functional changes.
v2: added __ function to differentiate when errors want to be handled back in
This program can be used to detect when the writes don't land in scanout due
cache incoherency. Although this seems a problem inherently of non-LCC machines
("Atom"), this particular test catches a cache dirt on scanout on LLC machines
as well. It's inspired in Ville's kms_pwrite_crc.c and can be u
This patch adds test_correct_cpu_write, which maps the texture buffer through a
prime fd and then writes directly to it using the CPU. It stresses the driver
to guarantee cache synchronization among the different domains.
This test also adds test_forked_cpu_write, which creates the GEM bo in one
p
Hi,
Here's the igt side of the work I sent yesterday to dri-devel:
http://lists.freedesktop.org/archives/dri-devel/2015-August/089263.html
I've addressed all the commentaries made in the previous igt patchset and I
believe that all tests now run fine in older kernels that don't support
dma-buf m
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7227
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -2
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7228
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
On Tue, 25 Aug 2015, Daniel Vetter wrote:
> On Fri, Aug 21, 2015 at 11:41:45AM +0300, Jani Nikula wrote:
>> On Tue, 30 Jun 2015, Ander Conselvan De Oliveira
>> wrote:
>> > On Mon, 2015-06-29 at 14:31 +0300, Ander Conselvan De Oliveira wrote:
>> >> On Fri, 2015-06-26 at 18:28 +0300, Ander Conselv
On Thu, 27 Aug 2015, Chris Wilson wrote:
> On Thu, Aug 27, 2015 at 09:19:18AM -0700, Jesse Barnes wrote:
>> On 08/27/2015 01:36 AM, Jani Nikula wrote:
>> > On Wed, 26 Aug 2015, Daniel Vetter wrote:
>> >> On Wed, Aug 26, 2015 at 12:55:57PM +0100, Chris Wilson wrote:
>> >>> As we mark the prealloca
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