That seems to be a typo. The original code will override the previous
list empty check value in the loop. As the result, only the last vm in
vm_list impacts the empty check. The problem is fixed by using local
bool variable inside the loop.
Signed-off-by: Zhiyuan Lv
---
drivers/gpu/drm/i915/i915
On Mon, Aug 17, 2015 at 05:19:09PM +, Zanoni, Paulo R wrote:
> Em Sex, 2015-08-14 às 12:35 +0200, Thierry Reding escreveu:
> > From: Thierry Reding
> >
> > The gtt.stolen_size field is of type size_t, and so should be printed
> > using %zu to avoid build warnings on either 32-bit and 64-bit b
On Fri, Aug 14, 2015 at 05:18:27PM +0100, Chris Wilson wrote:
> On Fri, Aug 14, 2015 at 06:43:30PM +0300, Imre Deak wrote:
> > Due to a coherency issue on BXT A steppings we can't guarantee a
> > coherent view of cached (CPU snooped) GPU mappings, so fail such
> > requests. User space is supposed t
On Mon, 17 Aug 2015, Xiong Zhang wrote:
> v2: fix one error found by checkpath.pl
> v3: Add one ignored break for switch-case. DDI-E hotplug
> function doesn't work after updating drm-intel tree,
> I checked the code and found this missing which isn't
> the root cause for broke DDI-E h
On Wed, 26 Aug 2015, Daniel Vetter wrote:
> On Mon, Aug 17, 2015 at 05:19:09PM +, Zanoni, Paulo R wrote:
>> Em Sex, 2015-08-14 às 12:35 +0200, Thierry Reding escreveu:
>> > From: Thierry Reding
>> >
>> > The gtt.stolen_size field is of type size_t, and so should be printed
>> > using %zu to
On Tue, 25 Aug 2015, Rodrigo Vivi wrote:
> SKL-Y can now use the same programming for all VccIO values after an
> adjustment to I_boost.
> SKL-U DP table adjustments.
> 1. Remove SKL Y 0.95V from "SKL H and S" columns in all tables. The
> other SKL Y column removes the "0.85V VccIO" so it
On Wed, Aug 26, 2015 at 03:01:26PM +0800, Zhiyuan Lv wrote:
> That seems to be a typo. The original code will override the previous
> list empty check value in the loop. As the result, only the last vm in
> vm_list impacts the empty check. The problem is fixed by using local
> bool variable inside
This partially reverts commit 74c090b1bdc57b1c9f1361908cca5a3d8a80fb08.
The DRIVER_ATOMIC cap cannot yet be exported because i915 lacks async
support.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i
On Fri, Aug 14, 2015 at 06:24:32PM +0100, Chris Wilson wrote:
> The PIPE.STAT register contains some interrupt status bits per pipe, and
> if assert cause the corresponding bit in the IIR to be asserted (thus
> raising an interrupt). When handling an interrupt, we should clear the
> PIPE.STAT gener
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7223
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -2
On Thu, Aug 20, 2015 at 06:00:02PM +0300, Ville Syrjälä wrote:
> On Thu, Aug 20, 2015 at 11:29:29AM -0300, Paulo Zanoni wrote:
> > 2015-08-20 10:58 GMT-03:00 Ville Syrjälä :
> > > Once it's otherwise known to be solid,
> > > then it might make sense, although a much cooler thing would be if we
> >
On Wed, Aug 26, 2015 at 10:26:35AM +0300, Jani Nikula wrote:
> On Wed, 26 Aug 2015, Daniel Vetter wrote:
> > On Mon, Aug 17, 2015 at 05:19:09PM +, Zanoni, Paulo R wrote:
> >> Em Sex, 2015-08-14 às 12:35 +0200, Thierry Reding escreveu:
> >> > From: Thierry Reding
> >> >
> >> > The gtt.stolen_
On Tue, Aug 25, 2015 at 07:03:42PM -0300, Paulo Zanoni wrote:
> The unclaimed register bit is only triggered when someone touches the
> specified register range.
>
> For the normal use case (with i915.mmio_debug=0), this commit will
> avoid the extra __raw_i915_read32() call for every register out
On Wed, Aug 19, 2015 at 02:55:34PM +0300, Ville Syrjälä wrote:
> On Sat, Aug 15, 2015 at 09:30:18AM +0100, Chris Wilson wrote:
> > On Fri, Aug 14, 2015 at 06:34:18PM -0300, Paulo Zanoni wrote:
> > > The spec says we just can't use it.
> >
> > But what about when we inherit a framebuffer at that ad
On Mon, Aug 17, 2015 at 12:00:38PM +0200, Maarten Lankhorst wrote:
> Set DRIVER_MODESET and DRIVER_ATOMIC by default. The driver is fully atomic.
> Remove the legacy suspend/resume, to fix a warning introduced by:
>
> "drm: WARN_ON if a modeset driver uses legacy suspend/resume helpers"
>
> and r
On Mon, Aug 17, 2015 at 03:20:38PM +0300, Jani Nikula wrote:
> On Mon, 17 Aug 2015, libin.y...@intel.com wrote:
> > From: Libin Yang
> >
> > HDMI audio may not work at some frequencies
> > with the HW provided N/CTS.
> >
> > This patch sets the proper N value for the
> > given audio sample rate at
Delay the expensive read on the FPGA_DBG register from once per mmio to
once per forcewake section when we are doing the general wellbeing
check rather than the targetted error detection. This almost reduces
the overhead of the debug facility (for example when submitting execlists)
to zero whilst k
Make it available outside of intel_dp.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 33 +
drivers/gpu/drm/i915/intel_dp.c | 34 --
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 34 inse
Normally we determine the backlight PWM modulation frequency (which we
also use as backlight max value) from the backlight registers at module
load time, expecting the registers have been initialized by the BIOS. If
this is not the case, we fail.
The VBT contains the backlight modulation frequency
This is a rebase of [1] and originally [2]. I haven't tried this in a
year and I have no idea if it works on SKL, and it's not implemented for
BXT. However there's renewed interest, so here's the rebase.
BR,
Jani.
[1] http://mid.gmane.org/cover.1431003197.git.jani.nik...@intel.com
[2] http://mid.
Op 26-08-15 om 09:51 schreef Daniel Vetter:
> On Mon, Aug 17, 2015 at 12:00:38PM +0200, Maarten Lankhorst wrote:
>> Set DRIVER_MODESET and DRIVER_ATOMIC by default. The driver is fully atomic.
>> Remove the legacy suspend/resume, to fix a warning introduced by:
>>
>> "drm: WARN_ON if a modeset driv
On Tue, Aug 18, 2015 at 01:56:08PM +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 17-08-15 om 17:05 schreef ville.syrj...@linux.intel.com:
> > From: Ville Syrjälä
> >
> > With MST there won't be a crtc assigned to the main link encoder, so
> > trying to dig up the pipe_config from there is a recip
Hi Chris,
Thanks for the reply! Do you mean we could completely delete
i915_gem_evict_everything() and rely on others to do gem_retire_requests()?
Sorry that I am still learning the code :-)
Regards,
-Zhiyuan
On Wed, Aug 26, 2015 at 08:28:43AM +0100, Chris Wilson wrote:
> On Wed, Aug 26, 2015 at
On Mon, Aug 17, 2015 at 01:45:01PM -0300, Paulo Zanoni wrote:
> 2015-08-17 13:30 GMT-03:00 Dave Gordon :
> > The current versions of these two macros don't work correctly if the
> > argument expression happens to contain a modulo operator (%) -- when
> > stringified, it gets interpreted as a printf
Hi Daniel,
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Wednesday, August 26, 2015 3:53 PM
> To: Jani Nikula
> Cc: Yang, Libin; alsa-de...@alsa-project.org; ti...@suse.de; intel-
> g...@lists.freedesktop.org; daniel.vet...@
On Thu, 13 Aug 2015, "Jindal, Sonika" wrote:
> On 8/13/2015 8:57 AM, Zhang, Xiong Y wrote:
>>> On Wed, 2015-08-12 at 02:20 +, Zhang, Xiong Y wrote:
> On Tue, 2015-08-11 at 07:05 +, Zhang, Xiong Y wrote:
>>> -Original Message-
>>> From: Vivi, Rodrigo
>>> Sent: Saturd
On Wed, Aug 26, 2015 at 09:57:45AM +0200, Maarten Lankhorst wrote:
> Op 26-08-15 om 09:51 schreef Daniel Vetter:
> > On Mon, Aug 17, 2015 at 12:00:38PM +0200, Maarten Lankhorst wrote:
> >>.load = i915_driver_load,
> >>.unload = i915_driver_unload,
> >>.open = i915_driver_open,
> >> @@ -
On 08/17/2015 05:15 PM, Ville Syrjälä wrote:
On Mon, Aug 17, 2015 at 07:49:41AM +0530, Deepak wrote:
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
When fractional m2 divider isn't used on CHV the fractional part
is ignore by the hardware. Despite that, pr
On 08/17/2015 05:23 PM, Ville Syrjälä wrote:
On Mon, Aug 17, 2015 at 09:46:01AM +0530, Deepak wrote:
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Move the CHV clock buffer disable from chv_disable_pll() to the new
encoder .post_pll_disable() hook. This i
On Tue, Aug 18, 2015 at 02:51:51PM +0800, libin.y...@intel.com wrote:
> From: Libin Yang
>
> Add the sync_audio_rate callback.
>
> With the callback, audio driver can trigger
> i915 driver to set the proper N/CTS or N/M
> based on different sample rates.
>
> Signed-off-by: Libin Yang
> ---
>
On Wed, 26 Aug 2015, Daniel Vetter wrote:
> On Mon, Aug 17, 2015 at 03:20:38PM +0300, Jani Nikula wrote:
>> On Mon, 17 Aug 2015, libin.y...@intel.com wrote:
>> > From: Libin Yang
>> >
>> > HDMI audio may not work at some frequencies
>> > with the HW provided N/CTS.
>> >
>> > This patch sets the p
On Mon, 2015-08-24 at 14:40 +0100, Thomas Wood wrote:
> On 20 August 2015 at 15:43, Ander Conselvan de Oliveira
> wrote:
> > The drm core doesn't check unused fields of ADDFB2 for pre-FB_MODIFIERS
> > userspace, so require that and use the local version of the defines.
> >
> > Signed-off-by: Ande
On Wed, Jul 08, 2015 at 11:45:53PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Add vlv_dport_to_phy() and fix up the return values of
> vlv_dport_to_channel() and vlv_pipe_to_channel() to use
> the appropriate enums.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gp
On 08/25/2015 10:18 PM, Chris Wilson wrote:
A long time ago (before 3.14) we relied on a permanent pinning of the
ifbdev to lock the fb in place inside the GGTT. However, the
introduction of stealing the BIOS framebuffer and reusing its address in
the GGTT for the fbdev has muddied waters and w
On Wed, Jul 08, 2015 at 11:45:54PM +0300, ville.syrj...@linux.intel.com wrote:
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index dab1da9..506a8cc 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runti
The drm core doesn't check unused fields of ADDFB2 for pre-FB_MODIFIERS
userspace, so use igt_require_fb_modifiers(). Also, the size of the
ioctl changed with the addition of the modifiers, so it is necessary to
use the LOCAL_ version of it, otherwise some data may get truncated.
v2: Improve commi
On Fri, Aug 21, 2015 at 02:52:54PM +0300, Mika Kahola wrote:
> On Fri, 2015-08-21 at 13:58 +0300, Ville Syrjälä wrote:
> > On Tue, Aug 18, 2015 at 02:37:02PM +0300, Mika Kahola wrote:
> > > It is possible the we request to have a mode that has
> > > higher pixel clock than our HW can support. This
Hi Daniel,
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Wednesday, August 26, 2015 4:18 PM
> To: Yang, Libin
> Cc: alsa-de...@alsa-project.org; ti...@suse.de; intel-
> g...@lists.freedesktop.org; daniel.vet...@ffwll.ch;
> j
On Tue, Aug 18, 2015 at 04:06:17PM +0100, Chris Wilson wrote:
> On Tue, Aug 18, 2015 at 03:55:07PM +0100, Nick Hoath wrote:
> > >This is the wrong location. Just kill set_seqno, the experiment has run
> > >its course and we now have a n igt to exercise seqno wraparound.
> > It has to be here as the
On Wed, Aug 19, 2015 at 10:48:55AM +0200, David Henningsson wrote:
> This callback will be called by the i915 driver to notify the hda
> driver that its HDMI information needs to be refreshed, i e,
> that audio output is now available (or unavailable) - usually as a
> result of a monitor being plug
On Wed, Aug 19, 2015 at 06:02:29PM -0700, Chandra Konduru wrote:
> This patch adds NV12 to list of supported formats for
> primary plane.
>
> v2:
> -Rebased (me)
>
> Signed-off-by: Chandra Konduru
> Testcase: igt/kms_nv12
I think it's time to unify the separate primary/cursor code we have for
s
On Wed, Aug 19, 2015 at 06:02:35PM -0700, Chandra Konduru wrote:
> Adding driver workarounds for nv12.
>
> Signed-off-by: Chandra Konduru
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20
> drivers/gpu/drm/i915/intel_csr.c |2 +-
> drivers/gpu/drm/i915/intel_displ
On 08/26/2015 10:42 AM, Archit Taneja wrote:
On 08/25/2015 07:15 PM, Daniel Vetter wrote:
Faster than recompiling.
Note that restore_fbdev_mode_unlocked is a bit special and the only
one which returns an error code when fbdev isn't there - i915 needs
that one to not fall over with some addi
On Wed, Aug 19, 2015 at 06:05:25PM -0700, Chandra Konduru wrote:
> From: chandra konduru
>
> This patch adds kms_nv12 test case. It covers testing NV12
> in linear/tile-X/tile-Y tiling formats in 0/90/180/270
> orientations. For each tiling format, it tests several
> combinations of planes and it
On Thu, Aug 20, 2015 at 01:57:13PM +0300, Joonas Lahtinen wrote:
> On to, 2015-08-20 at 15:45 +0800, Zhiyuan Lv wrote:
> > The full ppgtt is supported in Intel GVT-g device model. So the
> > restriction can be removed.
> >
> > Signed-off-by: Zhiyuan Lv
> > Signed-off-by: Zhi Wang
>
> Reviewed-b
On Wed, Aug 26, 2015 at 10:32:01AM +0200, Daniel Vetter wrote:
> On Tue, Aug 18, 2015 at 04:06:17PM +0100, Chris Wilson wrote:
> > On Tue, Aug 18, 2015 at 03:55:07PM +0100, Nick Hoath wrote:
> > > >This is the wrong location. Just kill set_seqno, the experiment has run
> > > >its course and we now
On Mon, Aug 24, 2015 at 03:36:46PM +0300, Joonas Lahtinen wrote:
> On pe, 2015-08-21 at 10:24 +0800, Zhiyuan Lv wrote:
> > Hi Joonas,
> >
> > Thanks for the review! And my reply inline.
> >
> > Regards,
> > -Zhiyuan
> >
> > On Thu, Aug 20, 2015 at 02:23:11PM +0300, Joonas Lahtinen wrote:
> > > H
We can forgo an evict-everything here as the shrinker operation itself
will unbind any vma as required. If we explicitly idle the GPU through a
switch to the default context, we not only create a request in an
illegal context (e.g. whilst shrinking during execbuf with a request
already allocated),
With UMS gone, we no longer use it during suspend. And with the last
user removed from the shrinker, we can remove the dead code.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem_evict.c | 45 ---
2 files
Exclude active GPU pages from the purview of the background shrinker
(kswapd), as these cause uncontrollable GPU stalls. Given that the
shrinker is rerun until the freelists are satisfied, we should have
opportunity in subsequent passes to recover the pages once idle. If the
machine does run out of
This fixes kms_universal_plane.universal-plane-pipe-A-functional.
IPS gets enabled even though the primary plane is disabled. This is
not supported, and results in warnings like below:
[ cut here ]
WARNING: CPU: 0 PID: 1707 at drivers/gpu/drm/i915/intel_display.c:1354
asse
On Tue, Aug 25, 2015 at 08:17:05AM +0800, Zhiyuan Lv wrote:
> Hi Chris,
>
> On Mon, Aug 24, 2015 at 11:23:13AM +0100, Chris Wilson wrote:
> > On Mon, Aug 24, 2015 at 06:04:28PM +0800, Zhiyuan Lv wrote:
> > > Hi Chris,
> > >
> > > On Thu, Aug 20, 2015 at 09:36:00AM +0100, Chris Wilson wrote:
> > >
This is done through pre_disable_primary and hsw_disable_ips.
They're both set on the same conditions, so leave the check of
disable_ips in pre_disable_primary.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 16 +---
drivers/gpu/drm/i915/intel_drv.h |
On Thu, Aug 20, 2015 at 10:47:35AM +0300, Jani Nikula wrote:
> v2 with missing cases handled and intel_digital_port_connected return
> value changed to bool. Mostly it's just the addition of patches 2 and 3,
> and rebase of the rest.
Pulled in entire series, thanks.
-Daniel
>
> BR,
> Jani.
>
>
On Fri, Aug 21, 2015 at 09:40:12AM +0300, Jani Nikula wrote:
> On Thu, 20 Aug 2015, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > We are no longer checkling the DP link status on long hpd. We used to do
> > that from the .hot_plug() handler, but it was removed when MST got
>
On Thu, Aug 20, 2015 at 04:12:00PM -0700, Rodrigo Vivi wrote:
> From: Rodrigo Vivi
>
> Let's use a native read with retry as suggested per spec to
> fix Sink CRC on SKL when PSR is enabled.
>
> With PSR enabled panel is probably taking more time to wake
> and dpcd read is faling.
>
> Cc: Sonika
On Wed, Aug 26, 2015 at 08:29:09AM +, Yang, Libin wrote:
> Hi Daniel,
>
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> > Daniel Vetter
> > Sent: Wednesday, August 26, 2015 4:18 PM
> > To: Yang, Libin
> > Cc: alsa-de...@alsa-project.org; ti
On Thu, Aug 20, 2015 at 05:55:41PM -0700, Rodrigo Vivi wrote:
> At the beginning it was masked to allow PSR at all.
> Than it got removed later by my
> commit 09108b90f040 ("drm/i915: PSR: Remove Low Power HW tracking mask.")
> in order to trying fixing one case reported at intel-gfx mailing list
>
On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> In order to flush the results from in-batch pipecontrol writes (used for
> example in glQuery) before declaring the batch complete (and so declaring
> the query results coherent), we need to set the FlushEnable bit in our
> flushing pi
On Fri, Aug 21, 2015 at 06:50:03PM +0100, Chris Wilson wrote:
> On Fri, Aug 21, 2015 at 08:45:29PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Most of our char* arrays are markes as const already, but a few slipped
> > through the cracks. Fix it.
> >
> > Signed-of
On Mon, Aug 24, 2015 at 05:28:13PM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma
>
> We are trying to reduce the time for which the global 'struct_mutex'
> is locked. Execbuffer ioctl is one place where it is generally held
> for the longest time. And sometimes because o
On Sun, Aug 23, 2015 at 05:52:47PM +0530, Sagar Arun Kamble wrote:
> On BXT, We Observe timeout for forcewake request completion with 2ms polling
> period as given here:
> [drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack
> request.
> Polling for 50ms is recommended to avoid
On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> > In order to flush the results from in-batch pipecontrol writes (used for
> > example in glQuery) before declaring the batch complete (and so declaring
> > the query res
On Tue, Aug 25, 2015 at 05:10:54PM +0100, Graham Whaley wrote:
> On Tue, 2015-08-25 at 16:29 +0200, Daniel Vetter wrote:
> > On Tue, Aug 25, 2015 at 10:26:44AM +0100, Graham Whaley wrote:
> > > The KMS Properties table is in HTML format, which is not supported
> > > for building pdfdocs, resulting
On Tue, Aug 25, 2015 at 05:31:33PM +0530, Sonika Jindal wrote:
> Some monitors take time in setting the live status.
> So retry for few times if this is a connect HPD
>
> Signed-off-by: Sonika Jindal
Why was this bugfix not part of the original series? Now I have to retest
on my ivb to figure ou
On Tue, 25 Aug 2015, Sivakumar Thulasimani
wrote:
> From: "Thulasimani,Sivakumar"
>
> This patch reads sink_count dpcd always and removes its
> read operation based on values in downstream port dpcd. Also
> we should read it irrespective of current status of sink.
Having to write "also" in a co
On Tue, 25 Aug 2015, Sivakumar Thulasimani
wrote:
> From: "Thulasimani,Sivakumar"
>
> This patch checks for changes in sink count between short pulse
> hpds and forces full detect when there is a change. This will
> result in compliance test case 4.2.2.8 passing since it tests
> for this behavio
HPD bits control the interrupt but the live status (with some monitors) takes
time to get set.
We had experienced this with VLV and CHV with few monitors.
So Android code always has this retry for live status.
Yes, this was not added in the previous series because we planned to add the
next set
On 8/26/2015 3:17 PM, Jani Nikula wrote:
On Tue, 25 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch reads sink_count dpcd always and removes its
read operation based on values in downstream port dpcd. Also
we should read it irrespective of current status of
On 8/26/2015 3:32 PM, Jani Nikula wrote:
On Tue, 25 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a change. This will
result in compliance test case 4.2.2.8 pass
On 24 August 2015 at 10:59, Stefan Dirsch wrote:
> Hi
>
> Find a simple buildfix against current intel-gpu-tools git sources attached.
I assume the compiler warning is about uninitialised values and unused
variables? It looks like the Makefile is not using the debug cflags so
these warning do not
Hi Daniel,
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Wednesday, August 26, 2015 5:08 PM
> To: Yang, Libin
> Cc: Daniel Vetter; alsa-de...@alsa-project.org; ti...@suse.de; intel-
> g...@lists.freedesktop.org; daniel.vet..
On Wed, Aug 26, 2015 at 09:48:51AM +0200, Daniel Vetter wrote:
> On Wed, Aug 19, 2015 at 02:55:34PM +0300, Ville Syrjälä wrote:
> > On Sat, Aug 15, 2015 at 09:30:18AM +0100, Chris Wilson wrote:
> > > On Fri, Aug 14, 2015 at 06:34:18PM -0300, Paulo Zanoni wrote:
> > > > The spec says we just can't u
On 8/26/2015 3:32 PM, Jani Nikula wrote:
On Tue, 25 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a change. This will
result in compliance test case 4.2.2.8 pass
Skl is fully dependent on dmc for going to low power state (dc5/dc6).
This requires a trigger from rpm. To ensure the dmc firmware
is available for runtime pm support rpm-reference-count is used
by not releasing the rpm reference if firmware loading is
not completed.
So moved the intel_csr_ucode_i
From: Daniel Vetter
Grabbing a runtime pm reference with intel_runtime_pm_get will only
prevent device D3. But dmc firmware is required even earlier (namely
for the skl power well 2).
Hence we need to grab a rpm reference higher up in the hierarchy. For
simplicity just grab the _INIT display pow
This patch series has the changes done to redesign the dmc firmware
loading flow. This is continuation of the below patch series after
addressing review comments from Daniel.
v1: http://lists.freedesktop.org/archives/intel-gfx/2015-August/072921.html
v2:
- After rebasing based on below patch ser
From: Daniel Vetter
Standard is to align continuations of parameter lists and if
conditions to the opening ( in i915 and drm code.
Apply this across the entire file since it was sticking out a bit too
much.
Also align register definitions while at it.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sun
From: Daniel Vetter
Avoids non-static functions since all the callers are in intel_rpm.c.
Only thing we need for that is to move the register definitions into
i915_reg.h.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers
From: Daniel Vetter
This removes two anti-patterns:
- Locking shouldn't be used to synchronize with async work (of any
form, whether callbacks, workers or other threads). This is what the
mutex_lock/unlock seems to have been for in intel_csr_load_program.
Instead ordering should be ensured
From: Daniel Vetter
The loader function will get a bit more complicated soon, extract the
parsing code to make the control flow clearer. While doing that just
use dev_priv->csr.dmc_payload as the indicator for whether it all
suceeded or not.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
S
From: Daniel Vetter
Two benefits:
- We can use FW_LOADER_USERSPACE_FALLBACK.
- We can use flush_work to synchronize with the oustanding worker,
which is a notch more obvious what it does than having a special
completion.
The next patch will properly synchronize against the async loader in
th
Condition check for out of boundary for csr address space is corrected
(Thanks to David Binderman for suggestion).
Cc: Imre Deak
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c
Note that for bxt without dmc, display engine can go to lowest
possible state (dc9), so releasing the rpm reference.
Cc: Daniel Vetter
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Daniel Vetter
If we really want to we can be more verbose here, but we really don't
need an entire function for this.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c | 20
From: Daniel Vetter
We need to make sure we don't put garbage into the hw if dmc firmware
loading failed mid-thru.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 inse
From: Daniel Vetter
As all csr firmware related opertion are not using any
any data structures of drm framework level, so better to
use dev_priv instead of dev. it's a new style! :)
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
-
During driver unload to ensure we dont have any pending task,
flush_work added to complete firmware loading task.
v1: Initial version.
v2: As per review comments from Daniel,
Removed flush_work from skl_set_power_well. As we have taken
power well refernece and rpm count during firmware loading
by
As during disabling dc6 no need to check for csr firmware
loading status, so removed the assert call (Requested by Damien).
Cc: Damien Lespiau
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_r
There is no need to have a separate flag for tps3 as the information is
only used at one location. Move the logic there to make it easier to
follow.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 31 +--
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 fi
Cc: Thierry Reding
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 499e9f625aef..8c52d0ef1fc9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_he
No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f10a4724b841..60dca34d2f0f 100644
--- a/drivers/gpu/drm/i915/intel_d
On Wed, Aug 26, 2015 at 02:14:37PM +0530, Archit Taneja wrote:
>
>
> On 08/26/2015 10:42 AM, Archit Taneja wrote:
> >
> >
> >On 08/25/2015 07:15 PM, Daniel Vetter wrote:
> >>Faster than recompiling.
> >>
> >>Note that restore_fbdev_mode_unlocked is a bit special and the only
> >>one which returns
On Tue, Aug 25, 2015 at 03:20:02PM -0400, Rob Clark wrote:
> On Tue, Aug 25, 2015 at 11:20 AM, Daniel Vetter
> wrote:
> > Using bool and returning true upon error is very uncommon. Also an int
> > return value is actually what all the callers which did check it seem
> > to have expected.
> >
> >
On Wed, Aug 26, 2015 at 01:34:58PM +0200, Daniel Vetter wrote:
> On Wed, Aug 26, 2015 at 02:14:37PM +0530, Archit Taneja wrote:
> >
> >
> > On 08/26/2015 10:42 AM, Archit Taneja wrote:
> > >
> > >
> > >On 08/25/2015 07:15 PM, Daniel Vetter wrote:
> > >>Faster than recompiling.
> > >>
> > >>Note t
On Tue, Aug 25, 2015 at 05:20:36PM +0530, Sivakumar Thulasimani wrote:
> From: "Thulasimani,Sivakumar"
>
> This patch reads sink_count dpcd always and removes its
> read operation based on values in downstream port dpcd. Also
> we should read it irrespective of current status of sink.
>
> SINK_C
Hello Linux Graphic Team members,
REQUEST
May I please request support for driver of Intel GMA 3150 for Ubuntu 14.04.3
32 bit (Trusty Tahr)?
I installed "Intel Graphic Installer for Linux" from 01.org, but it stops at
the very first step saying "Distribution not supported".
BACKGROUND
Af
As we mark the preallocated objects as bound, we should also flag them
correctly as being map-and-fenceable (if appropriate!) so that latter
users do not get confused and try and rebind the pinned vma in order to
get a map-and-fenceable binding.
Signed-off-by: Chris Wilson
Cc: "Goel, Akash"
Cc:
On 8/26/2015 5:21 PM, Ville Syrjälä wrote:
On Tue, Aug 25, 2015 at 05:20:36PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
This patch reads sink_count dpcd always and removes its
read operation based on values in downstream port dpcd. Also
we should read it irrespective
On 8/18/2015 1:36 AM, Benjamin Tissoires wrote:
On Aug 14 2015 or thereabouts, Stéphane Marchesin wrote:
On Wed, Aug 5, 2015 at 12:34 PM, Benjamin Tissoires
wrote:
On Jul 30 2015 or thereabouts, Sivakumar Thulasimani wrote:
On 7/29/2015 8:52 PM, Benjamin Tissoires wrote:
On Jul 29 2015 or
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