On Tue, 30 Jun 2015, Ander Conselvan De Oliveira wrote:
> On Mon, 2015-06-29 at 14:31 +0300, Ander Conselvan De Oliveira wrote:
>> On Fri, 2015-06-26 at 18:28 +0300, Ander Conselvan De Oliveira wrote:
>> > Hi all,
>> >
>> > I've been looking into creating custom fields in Bugzilla to help sort
>>
On Tue, Aug 18, 2015 at 02:37:00PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot
On Tue, Aug 18, 2015 at 02:36:59PM +0300, Mika Kahola wrote:
> Store max dotclock into dev_priv structure so we are able
> to filter out the modes that are not supported by our
> platforms.
>
> V2:
> - limit the max dot clock frequency to max CD clock frequency
> for the gen9 and above
> - limit
On Tue, Aug 18, 2015 at 02:37:01PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot
On Tue, Aug 18, 2015 at 02:37:02PM +0300, Mika Kahola wrote:
> It is possible the we request to have a mode that has
> higher pixel clock than our HW can support. This patch
> checks if requested pixel clock is lower than the one
> supported by the HW. The requested mode is discarded
> if we cannot
On Fri, 2015-08-21 at 13:58 +0300, Ville Syrjälä wrote:
> On Tue, Aug 18, 2015 at 02:37:02PM +0300, Mika Kahola wrote:
> > It is possible the we request to have a mode that has
> > higher pixel clock than our HW can support. This patch
> > checks if requested pixel clock is lower than the one
> > s
Since RC6 enabling does not involve PCU communication overhead,
it can be enabled immediately during the resume time.
This will help save additional power & meet power requirements
for active Idle KPI where power is evaluated over
number of transitions of suspend/resume.
Signed-off-by: Namrta Salo
On Sat, Aug 22, 2015 at 02:19:48AM +0530, Namrta Salonie wrote:
> Since RC6 enabling does not involve PCU communication overhead,
> it can be enabled immediately during the resume time.
> This will help save additional power & meet power requirements
> for active Idle KPI where power is evaluated o
On Fri, 2015-08-07 at 15:53 +0300, David Weinehall wrote:
> On Thu, Aug 06, 2015 at 11:33:00PM +0200, Daniel Vetter wrote:
> > This reverts commit 0b45b0746f45deea11670a8b2c949776bbbef55c.
> >
> > The point of testing for LAST_FLAG + 1 is to catch abi extensions -
> > despite our best efforts we r
On Fri, Jul 24, 2015 at 11:51:01AM +0100, Chris Wilson wrote:
> On Fri, Jul 24, 2015 at 11:22:34AM +0200, Michał Winiarski wrote:
> > From: Rafał Sapała
> >
> > It is possible to hit a race condition in create_from_prime, when trying
> > to import a BO that's currently being freed. In case of pri
Since I had to revert David's commit from v4.2, we'll have to add it
back to drm-intel-next-fixes for v4.3. So it's a good occasion to
reflect on it.
I think it's problematic to be so strict with the VBT child device
size. We generally go for really verbose error and debug messages in the
dmesg an
The VEBOX ring is not available in generations before Haswell, so make
tests that use it skip instead of fail in previous gens.
Signed-off-by: Ander Conselvan de Oliveira
---
tests/gem_storedw_loop.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/tests/gem_storedw_l
From: David Weinehall
VBT version 196 increased the size of common_child_dev_config. The
parser code assumed that the size of this structure would not change.
The modified code now copies the amount needed based on the VBT version,
and emits a debug message if the VBT version is unknown (too new
Em Sex, 2015-08-21 às 01:04 +, Rodrigo Vivi escreveu:
> This patch series brings stability to PSR on VLV, CHV, HSW and BDW.
>
> It fixes issues Matthew Garrett without causing the blank and frozen
> screens Ivan Mitev was facing.
>
> It also move the VLV/CHV workaround of that big delay from
On Fri, Aug 21, 2015 at 04:52:01PM +0300, Jani Nikula wrote:
> From: David Weinehall
>
> VBT version 196 increased the size of common_child_dev_config. The
> parser code assumed that the size of this structure would not change.
>
> The modified code now copies the amount needed based on the VBT
In order to flush the results from in-batch pipecontrol writes (used for
example in glQuery) before declaring the batch complete (and so declaring
the query results coherent), we need to set the FlushEnable bit in our
flushing pipecontrol. The FlushEnable bit "waits until all previous
writes of imm
On Tue, Aug 18, 2015 at 02:51:52PM +0800, libin.y...@intel.com wrote:
> From: Libin Yang
>
> HDMI audio may not work at some frequencies
> with the HW provided N/CTS.
>
> This patch sets the proper N value for the
> given audio sample rate at the impacted frequencies.
> At other frequencies, it
On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> In order to flush the results from in-batch pipecontrol writes (used for
> example in glQuery) before declaring the batch complete (and so declaring
> the query results coherent), we need to set the FlushEnable bit in our
> flushing pi
On Tue, Aug 18, 2015 at 02:51:54PM +0800, libin.y...@intel.com wrote:
> From: Libin Yang
>
> When modeset occurs and the TMDS frequency is set to some
> speical values, the N/CTS need to be set manually if audio
> is playing.
>
> Signed-off-by: Libin Yang
> ---
> drivers/gpu/drm/i915/i915_reg.
On Fri, Aug 21, 2015 at 7:06 AM Zanoni, Paulo R
wrote:
>
> Em Sex, 2015-08-21 às 01:04 +, Rodrigo Vivi escreveu:
> > This patch series brings stability to PSR on VLV, CHV, HSW and BDW.
> >
> > It fixes issues Matthew Garrett without causing the blank and frozen
> > screens Ivan Mitev was faci
From: Ville Syrjälä
Simple one:
drivers/gpu/drm/i915/i915_debugfs.c:2449:57: warning: Using plain integer as
NULL pointer
And something a bit more peculiar:
drivers/gpu/drm/i915/i915_debugfs.c:4953:18: warning: Variable length array is
used.
drivers/gpu/drm/i915/i915_debugfs.c:4953:32: warning
From: Ville Syrjälä
A couple of hand rolled ARRAY_SIZE()s caught my eye. Get rid of them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 2 +-
drivers/gpu/drm/i915/intel_tv.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
3 files changed, 3 insertions(+), 4 de
From: Ville Syrjälä
Most of our char* arrays are markes as const already, but a few slipped
through the cracks. Fix it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
On Fri, Aug 21, 2015 at 08:45:29PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Most of our char* arrays are markes as const already, but a few slipped
> through the cracks. Fix it.
>
> Signed-off-by: Ville Syrjälä
All 3, Reviewed-by: Chris Wilson
-Chris
--
Chris Wi
Em Qua, 2015-08-05 às 14:59 -0700, Rodrigo Vivi escreveu:
> SKL-Y can now use the same programming for all VccIO values after an
> adjustment to I_boost.
> SKL-U DP table adjustments.
> 1. Remove SKL Y 0.95V from "SKL H and S" columns in all tables.
> The other SKL Y column removes the "0.
Using pandoc as the Markdown engine cause some minor side effects as
pandoc includes main tags for almost everything.
Original Markdown support approach removes those main tags, but it caused
some inconsistencies when that tag is not the main one, like:
..
...
As kernel-doc was already including
"/**" should be used for kernel-doc documentation only.
It causes a warning with the new "in struct body" format.
Signed-off-by: Danilo Cesar Lemes de Paula
Cc: Randy Dunlap
Cc: Daniel Vetter
Cc: Laurent Pinchart
Cc: Jonathan Corbet
Cc: Herbert Xu
Cc: Stephan Mueller
Cc: Michal Marek
Cc: l
2015-07-24 20:38 GMT-03:00 Rodrigo Vivi :
> We also need to call the frontbuffer flip to trigger proper
> invalidations when disabling planes. Otherwise we will miss
> screen updates when disabling sprites or cursor.
>
> It was caught with kms_psr_sink_crc sprite_plane_onoff
> and cursor_plane_onof
On Thu, Aug 06, 2015 at 10:08:12PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi
>
> This patch adds atomic get property interface for Intel CRTC. This
> interface will be used for get operation on any non-core DRM properties.
>
> Signed-off-by: Shashank Sharma
> Signed-off-by: Kausal Ma
On Thu, Aug 06, 2015 at 10:08:14PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi
>
> As per Color Manager design, each driver is responsible to load its
> palette color correction and enhancement capabilities in the form of
> a DRM blob property, so that user space can query and read.
>
>
On Thu, Aug 06, 2015 at 10:08:18PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi
>
> CHV/BSW platform supports two different pipe level gamma
> correction modes, which are:
> 1. Legacy 8-bit mode
> 2. 10-bit CGM (Color Gamut Mapping) mode
>
> This patch does the following:
> 1. Attaches G
On Thu, Aug 06, 2015 at 10:08:17PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi
>
> I915 driver registers gamma correction as palette correction
> property with DRM layer. This patch adds set_property() and get_property()
> handlers for pipe level gamma correction.
>
> The set function a
On Thu, Aug 06, 2015 at 10:08:24PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi
>
> This patch initializes gamma color correction proeprty
typo
> for Gen8 and higher platforms.
I'd sp
On Thu, Aug 06, 2015 at 10:08:15PM +0530, Shashank Sharma wrote:
> From: Kausal Malladi
>
> This patch adds new variables in CRTC state, to hold respective color
> correction blobs. These blobs will be required during the atomic commit
> for writing the color correction values in correction regis
Thanks for the review Matt.
Regards
Shashank
On 8/22/2015 4:10 AM, Matt Roper wrote:
On Thu, Aug 06, 2015 at 10:08:12PM +0530, Shashank Sharma wrote:
From: Kausal Malladi
This patch adds atomic get property interface for Intel CRTC. This
interface will be used for get operation on any non-cor
Regards
Shashank
On 8/22/2015 4:10 AM, Matt Roper wrote:
On Thu, Aug 06, 2015 at 10:08:14PM +0530, Shashank Sharma wrote:
From: Kausal Malladi
As per Color Manager design, each driver is responsible to load its
palette color correction and enhancement capabilities in the form of
a DRM blob pr
Regards
Shashank
On 8/22/2015 4:10 AM, Matt Roper wrote:
On Thu, Aug 06, 2015 at 10:08:15PM +0530, Shashank Sharma wrote:
From: Kausal Malladi
This patch adds new variables in CRTC state, to hold respective color
correction blobs. These blobs will be required during the atomic commit
for writ
Regards
Shashank
On 8/22/2015 4:10 AM, Matt Roper wrote:
On Thu, Aug 06, 2015 at 10:08:17PM +0530, Shashank Sharma wrote:
From: Kausal Malladi
I915 driver registers gamma correction as palette correction
property with DRM layer. This patch adds set_property() and get_property()
handlers for p
Regards
Shashank
On 8/22/2015 4:11 AM, Matt Roper wrote:
On Thu, Aug 06, 2015 at 10:08:18PM +0530, Shashank Sharma wrote:
From: Kausal Malladi
CHV/BSW platform supports two different pipe level gamma
correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
T
Regards
Shashank
On 8/22/2015 4:11 AM, Matt Roper wrote:
On Thu, Aug 06, 2015 at 10:08:24PM +0530, Shashank Sharma wrote:
From: Kausal Malladi
This patch initializes gamma color correction proeprty
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