Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7200
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Sun, Aug 16, 2015 at 04:02:28AM +0100, Michel Thierry wrote:
> The adj_start calculation for DRM_MM_CREATE_TOP should happen after
> mm->color_adjust. There was an inconsistency between
> drm_mm_insert_helper_range
> and drm_mm_insert_helper, as the later was already updating after
> color_adjus
I traced a stability issue on my Braswell nuc to a lack of visibility of
PTE writes into the GTT by the GPU. (The smoking gun was GPU hangs with
random fault addresses but correct command streams). Adding clflushes or
kicking the chipset flush harder had no effect, only disabling the WC
cache for t
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7201
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7202
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -2
Hi Daniel,
On Wed, Aug 12, 2015 at 11:10:59PM +0200, Daniel Vetter wrote:
> Yes just squash and mention that the patch is based on work from
> $list_of_other_authors, plus cc them. There's not much point in
> acknowledging when people write broken patches ;-)
As you requested I've squashed the fi
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7208
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7209
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Sorry, but I don't get how this enables power_well_2 as well. I just see it
enabling ddi A/E as the other.
Maybe Paulo or Imre are the best one to review this.
On Thu, Aug 13, 2015 at 2:54 AM Xiong Zhang
mailto:xiong.y.zh...@intel.com>> wrote:
From B spec, DDI_E port belong to PowerWell 2, but
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
When fractional m2 divider isn't used on CHV the fractional part
is ignore by the hardware. Despite that, program the fractional
value (0 in this case) to the hardware register just to keep
things a bit more cons
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
The docs give you the impression that the unique transition scale
value shouldn't matter when unique transition scale is enabled. But
as Imre found on BXT (and I verfied also on BSW) the value does
matter. So fro
Hi Dave,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/i915/intel_atomic.c
drivers/gpu/drm/i915/intel_display.c
between commits:
f0fdc55db0c6 ("drm/i915: calculate primary visibility changes instead of
calling from set_config")
d2944cf21305 ("drm/i915: Com
On Tue, 28 Jul 2015 16:45:15 -0300
Danilo Cesar Lemes de Paula wrote:
> Functions, Structs and Parameters definitions on kernel documentation
> are pure cosmetic, it only highlights the element.
>
> To ease the navigation in the documentation we should use inside
> those tags so readers can eas
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Move the CHV clock buffer disable from chv_disable_pll() to the new
encoder .post_pll_disable() hook. This is more symmetric since the
clock buffer enable happens from the .pre_pll_enable() hook.
We'll have more
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
To implement DPIO lane power gating on CHV we're going to need to access
DPIO registers from the cmn power well enable hook. That gets called
rather early, so we need to move the DPIO port IOSF sideband port
assi
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
dev_priv->chv_phy_control is protected by the power_domains->lock
elsewhere, so also grab it when initializing chv_phy_control.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
With DPIO powergating active on CHV, we can't even access the DPIO PLL
registers until the lane power state overrides have been enabled. That
will happen from the encoder .pre_pll_enable() hook, so move
chv_prepa
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
With DPIO powergating active on CHV, we can't even access the DPIO PLL
registers until the lane power state overrides have been enabled. That
will happen from the encoder .pre_pll_enable() hook, so move
chv_prepa
On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Add vlv_dport_to_phy() and fix up the return values of
vlv_dport_to_channel() and vlv_pipe_to_channel() to use
the appropriate enums.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_drv.h | 18 +++
On 8/10/2015 11:14 AM, Sivakumar Thulasimani wrote:
On 7/14/2015 5:21 PM, Sonika Jindal wrote:
Adding this for SKL onwards.
v2: Adding checks for VLV/CHV as well. Reusing old ibx and g4x functions
to check digital port status. Adding a separate function to get bxt live
status (Daniel)
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