Hi Jani,
> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Wednesday, August 12, 2015 2:20 PM
> To: Yang, Libin; alsa-de...@alsa-project.org; ti...@suse.de; intel-
> g...@lists.freedesktop.org; daniel.vet...@ffwll.ch
> Subject: RE: [Intel-gfx] [PATCH v4
On 8/11/2015 1:05 PM, Zhiyuan Lv wrote:
Hi Mika/Dave/Michel,
I saw the patch of using LRI for root pointer update has been merged to
drm-intel. When we consider i915 driver to run inside a virtual machine, e.g.
with XenGT, we may still need Mika's this patch like below:
"
if (intel_vgp
We don't want pageflips to be delayed by any arbitrary user process, so
move their task to the high priority workqueue.
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
From: vkorjani
s RFC is for feature Display Stream Compression (DSC) for BXT,
It is a VESA defined standard to compress and decompress image in display
streams in a link independent manner. Some of the basic requirements of
the standard are to support higher resolution on a given display link
wit
From: vkorjani
For compression enabled, the number of bytes in active
region cannot be calculated just by multiplying number
of pixels and bits per pixel, formula in HLD is
ceil((ceil(pixels/num_slice) * bpp) / 8) * num_slice
hence modifying txbyteclkhs() to accommodate calculation
for DSC Enab
From: vkorjani
This patch adds register definitions required to support
DSC feature.
Signed-off-by: vkorjani
Signed-off-by: Yogesh Mohan Marimuthu
---
drivers/gpu/drm/i915/i915_reg.h | 126 +
drivers/gpu/drm/i915/intel_bios.h |1 +
2 files changed, 1
From: vkorjani
Adding pps structure as per VESA DSC v1.1 spec.
Adding "vbt_dsc_param" vbt structure to store DSC info
vbt_dsc_param and pps structures are made part of intel_vbt_data.
Signed-off-by: vkorjani
Signed-off-by: Yogesh Mohan Marimuthu
---
drivers/gpu/drm/i915/i915_drv.h |2 +
From: vkorjani
Program the MIPI_DPI_RESOLUTION register horizontal
resolution using the byte_to_pixels() DSC specific
function in case of compression enabled.
For non-compressed video, the number of pixels
in active region are computed as usual.
Change-Id: Iacea79352fa67a40a1d305494539f7c99f2715
From: vkorjani
This patch adds code to send pps long packet and compression mode
command packet.
Signed-off-by: vkorjani
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/
From: vkorjani
Program the PPS data from intel_dsc->vesa_dsc_pps_data
into display controller register DSCx_PICTURE_PARAMETER_SET_x.
DSC should be enabled in MIPI Port control register, after
programming PPS register
Disable DSC in disable sequence after disabling port.
Signed-off-by: vkorjani
From: vkorjani
After enabling DSC we need to send compression mode command packet
and pps data packet, for which 2 new data types are added
07h Compression Mode Data Type Write , short write, 2 parameters
0Ah PPS Long Write (word count determines number of bytes)
This patch adds support to send
From: vkorjani
This patch adds code to initialize Picture Parameter set (PPS)
data structure for DSC.
DSC is enabled than the bitrate should be calculated using the
formula pixel_clock * bits_per_pixel / lane_count, where
bits_per_pixel can be 8bpp, 10bpp, 12bpp.
value of bits_per_pixel is avail
In
commit d328c9d78d64ca11e744fe227096990430a88477
Author: Daniel Vetter
Date: Fri Apr 10 16:22:37 2015 +0200
drm/i915: Select starting pipe bpp irrespective or the primary plane
we started to select the pipe bpp from sink capabilities and not from
the primary framebuffer - that one might
On 11/08/2015 13:25, Mika Kuoppala wrote:
Don't set the size of bindless surface state on rendercopy.
And as of doing so, take into account the workaround for setting
the command size.
This was tried during hunting for
https://bugs.freedesktop.org/show_bug.cgi?id=89959. But no
impact was found.
Some more fixup is needed; the bits from Antti's patch
that actually expanded the struct to fully fit the newer
versions of the child_device_config was part of the second
patch; since that patch hasn't been merged yet we need this bit:
This applies on top of the patch you already merged
(the Iboos
> On Tue, 2015-08-11 at 11:47 +0200, Daniel Vetter wrote:
> > On Thu, Aug 06, 2015 at 03:51:39PM +0800, Xiong Zhang wrote:
> > > From: Rodrigo Vivi
> > >
> > > On Skylake we have eDP-to-VGA using DDI-E and another aux.
> > > So let's identify it properly.
> >
> > eDP means panel (the only differen
DDI-E doesn't have the correspondent GMBUS pin.
We rely on VBT to tell us which one it being used instead.
The DVI/HDMI on shared port couldn't exist.
This patch isn't tested without hardware wchich has HDMI
on DDI-E.
v2: fix trailing whitespace
v3: WARN() take place of BUG()
Signed-off-by: Xi
From Gen9, by default push constant command is not committed to the shader unit
untill the corresponding shader's BTP_* command is parsed. This is the
behaviour when set shader is enabled. This patch updates the batch to follow
this requirement otherwise it results in gpu hang.
Bugzilla: https://b
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7079
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
Currently when allocating a framebuffer fails, the gem object gets
unrefed at the bottom of the call chain in __intel_framebuffer_create,
not where it gets refed, which is in intel_framebuffer_create_for_mode
(via i915_gem_alloc_object) and in intel_user_framebuffer_create
(via drm_gem_object_looku
On Fri, Jul 31, 2015 at 11:32:52AM +0530, Sivakumar Thulasimani wrote:
> From: "Thulasimani,Sivakumar"
>
> This reverts
> commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
> Author: Ville Syrjälä
> Date: Thu Mar 12 17:10:38 2015 +0200
>
> CHV does not support intermediate frequencies so revert
This is a follow-up to the v1 posted in April:
http://lists.freedesktop.org/archives/dri-devel/2015-April/081515.html
Patches 1 - 17 enable GPU switching on the pre-retina MacBook Pro.
These were tested successfully by multiple people and solve two
tickets in Bugzilla:
https://bugzilla.kernel.org
From: Tvrtko Ursulin
We had two failure modes here:
1.
Deadlock in intelfb_alloc failure path where it calls
drm_framebuffer_remove, which grabs the struct mutex and intelfb_create
(caller of intelfb_alloc) was already holding it.
2.
Deadlock in intelfb_create failure path where it calls
drm_fr
The i915 driver probes eDP and LVDS connectors once on startup by
invoking intel_setup_outputs(). If no DPCD or EDID can be obtained,
it will remove the connectors from the device's mode configuration,
presuming they're ghost connectors. As a result, subsequent calls to
drm_fb_helper_hotplug_event(
Commit 92122789b2d6 ("drm/i915: preserve SSC if previously set v3")
added code to intel_modeset_gem_init to override the SSC status read
from VBT with the SSC status set by BIOS.
However, intel_modeset_gem_init is invoked *after* intel_modeset_init,
which calls intel_setup_outputs, which *modifies
On Tue, Aug 11, 2015 at 11:41:42AM +0200, Daniel Vetter wrote:
> On Mon, Aug 10, 2015 at 02:05:47PM +0530, Jindal, Sonika wrote:
> >
> >
> > On 8/10/2015 1:38 PM, Daniel Vetter wrote:
> > >On Mon, Aug 10, 2015 at 04:50:37AM +, Jindal, Sonika wrote:
> > >>Hi Daniel,
> > >>
> > >>That patch was
On 8/12/2015 5:02 PM, Ville Syrjälä wrote:
On Fri, Jul 31, 2015 at 11:32:52AM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
This reverts
commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
Author: Ville Syrjälä
Date: Thu Mar 12 17:10:38 2015 +0200
CHV does not support in
On ke, 2015-08-12 at 12:26 +0100, Arun Siluvery wrote:
> From Gen9, by default push constant command is not committed to the
> shader unit
> untill the corresponding shader's BTP_* command is parsed. This is
> the
> behaviour when set shader is enabled. This patch updates the batch to
> follow
>
On Wed, 12 Aug 2015, David Weinehall wrote:
> Some more fixup is needed; the bits from Antti's patch
> that actually expanded the struct to fully fit the newer
> versions of the child_device_config was part of the second
> patch; since that patch hasn't been merged yet we need this bit:
>
> This a
When we queue the command or operation to change the scanout address, we
mark the flip as in progress. We can use this flag to prevent us from
checking for a stalled flip prior to its existence!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 inser
On 11/08/2015 21:58, Timo Aaltonen wrote:
On 11.08.2015 17:44, Arun Siluvery wrote:
Patch1 fixes a simple compile error in Patch2
Patch2 fixes gpu hang observed with a subtest of gem_concurrent_blit.
Arun Siluvery (1):
drm/i915/gen9: Disable gather at set shader bit
Mika Kuoppala (1):
dr
On Tue, Aug 11, 2015 at 11:03:54AM +, Sharma, Shashank wrote:
> HI Daniel,
>
> Looks like we are not getting an IVB machine here. I think instead of
> blocking the patch set for the whole series, we can just block it for the
> platforms we don’t get success for.
> We are shipping many VLV/C
On Wed, Aug 12, 2015 at 10:27:08AM +, Zhang, Xiong Y wrote:
> > On Tue, 2015-08-11 at 11:47 +0200, Daniel Vetter wrote:
> > > On Thu, Aug 06, 2015 at 03:51:39PM +0800, Xiong Zhang wrote:
> > > > From: Rodrigo Vivi
> > > >
> > > > On Skylake we have eDP-to-VGA using DDI-E and another aux.
> > >
On Wed, Aug 12, 2015 at 06:39:34PM +0800, Xiong Zhang wrote:
> DDI-E doesn't have the correspondent GMBUS pin.
>
> We rely on VBT to tell us which one it being used instead.
>
> The DVI/HDMI on shared port couldn't exist.
>
> This patch isn't tested without hardware wchich has HDMI
> on DDI-E.
>
Regards
Shashank
On 8/12/2015 5:55 PM, Daniel Vetter wrote:
On Tue, Aug 11, 2015 at 11:03:54AM +, Sharma, Shashank wrote:
HI Daniel,
Looks like we are not getting an IVB machine here. I think instead of blocking
the patch set for the whole series, we can just block it for the platforms we
On Fri, Aug 07, 2015 at 02:07:39PM +0100, Chris Wilson wrote:
> On Fri, Aug 07, 2015 at 01:55:01PM +0200, Daniel Vetter wrote:
> > On Fri, Aug 07, 2015 at 11:10:58AM +0100, Chris Wilson wrote:
> > > On Fri, Aug 07, 2015 at 10:07:28AM +0200, Daniel Vetter wrote:
> > > > On Thu, Aug 06, 2015 at 05:43
On Wed, Aug 12, 2015 at 06:04:50PM +0530, Sharma, Shashank wrote:
> Regards
> Shashank
>
> On 8/12/2015 5:55 PM, Daniel Vetter wrote:
> >On Tue, Aug 11, 2015 at 11:03:54AM +, Sharma, Shashank wrote:
> >>HI Daniel,
> >>
> >>Looks like we are not getting an IVB machine here. I think instead of
On Wed, Aug 12, 2015 at 11:36:07AM +0530, Sivakumar Thulasimani wrote:
> Hi Daniel,
> any comments for the patch below ?
Find me a reviewer to r-b stamp this patch and I'll merge.
-Daniel
>
> regards,
> Sivakumar
>
> On Friday 07 August 2015 03:14 PM, Sivakumar Thulasimani wrote:
> >From: "
Sure, I understood the point.
We will do another round of testing with gen8, and when we are good with that,
will submit the patches again.
Regards
Shashank
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Wednesday, August 12, 2015
On Wed, Aug 12, 2015 at 02:35:59PM +0200, Daniel Vetter wrote:
> On Fri, Aug 07, 2015 at 02:07:39PM +0100, Chris Wilson wrote:
> > On Fri, Aug 07, 2015 at 01:55:01PM +0200, Daniel Vetter wrote:
> > > On Fri, Aug 07, 2015 at 11:10:58AM +0100, Chris Wilson wrote:
> > > > On Fri, Aug 07, 2015 at 10:07
On Fri, Aug 07, 2015 at 11:10:22AM -0700, Jesse Barnes wrote:
> On 08/07/2015 10:29 AM, Daniel Vetter wrote:
> > "Timed out" isn't a terribly informative message, allow users to set
> > something more informative. Inspired by a request from Jesse.
> >
> > Cc: Jesse Barnes
> > Signed-off-by: Danie
On Fri, Aug 07, 2015 at 08:24:15PM +0100, Chris Wilson wrote:
> The IOMMU for Intel graphics has historically had many issues resulting
> in random GPU hangs. Lets include its status when capturing the GPU hang
> error state for post-mortem analysis.
>
> Signed-off-by: Chris Wilson
Queued for -n
On Mon, Aug 10, 2015 at 05:51:48PM +0530, Sivakumar Thulasimani wrote:
>
>
> On 8/10/2015 5:44 PM, Jani Nikula wrote:
> >On Mon, 10 Aug 2015, Sivakumar Thulasimani
> >wrote:
> >>On 8/10/2015 5:07 PM, Jani Nikula wrote:
> >>>On Mon, 10 Aug 2015, Sivakumar Thulasimani
> >>> wrote:
> Reviewed
On Mon, Aug 10, 2015 at 10:58:55AM +0530, Sivakumar Thulasimani wrote:
> Reviewed-by: Sivakumar Thulasimani
>
> On 8/10/2015 10:35 AM, Sonika Jindal wrote:
> >WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling
> >DDIA HPD pin in place of DDIB.
> >
> >v2: For DP, irq_port is us
On Mon, Aug 10, 2015 at 06:23:19PM +, Rodrigo Vivi wrote:
> I believe this function could be added along with the next patch that is
> the first to use it...
> Or it would be good to have a good commit message explaining why this
> function is needed and what is be used for...
Yes, please don'
On Wed, Aug 12, 2015 at 05:31:55PM +0530, Sivakumar Thulasimani wrote:
>
>
> On 8/12/2015 5:02 PM, Ville Syrjälä wrote:
> > On Fri, Jul 31, 2015 at 11:32:52AM +0530, Sivakumar Thulasimani wrote:
> >> From: "Thulasimani,Sivakumar"
> >>
> >> This reverts
> >> commit fe51bfb95c996733150c44d21e1c9f4
On Mon, Aug 10, 2015 at 03:00:13PM +0300, Jani Nikula wrote:
> On Mon, 10 Aug 2015, libin.y...@intel.com wrote:
> > + n_low = n & 0xfff;
> > + n_up = (n >> 12) & 0xff;
> > +
> > + /* 4. set the N/CTS */
> > + tmp = I915_READ(HSW_AUD_CFG(pipe));
> > + tmp |= AUD_CONFIG_N_PROG_ENABLE;
> > +
On Mon, Aug 10, 2015 at 03:16:46PM +0300, Jani Nikula wrote:
> On Mon, 10 Aug 2015, libin.y...@intel.com wrote:
> > From: Libin Yang
> >
> > Display audio may not work at some frequencies
> > with the HW provided N/CTS.
> >
> > This patch sets the proper N value for the
> > given audio sample rate
On Wed, Aug 12, 2015 at 09:20:17AM +0300, Jani Nikula wrote:
> On Wed, 12 Aug 2015, "Yang, Libin" wrote:
> > Hi Jani,
> >
> >> -Original Message-
> >> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> >> Sent: Tuesday, August 11, 2015 4:14 PM
> >> To: Yang, Libin; alsa-de...@alsa-pr
On Fri, Jul 31, 2015 at 11:32:53AM +0530, Sivakumar Thulasimani wrote:
> From: "Thulasimani,Sivakumar"
>
> This patch removes 5.4Gbps from supported link rate for CHV since
> it is not supported in it.
>
> Signed-off-by: Sivakumar Thulasimani
> ---
> drivers/gpu/drm/i915/intel_dp.c |5 +++-
On Tue, Aug 11, 2015 at 04:49:33PM +0300, Mika Kahola wrote:
> Depending on the VBT BDB version the maximum size
> can be up to 38 bytes.
>
> This fix increases the maximum of the VBT expected size
> from 33 bytes to 38 bytes and by doing so cures the kernel
> hang on BSW box.
>
> Signed-off-by:
On Wed, 12 Aug 2015, Daniel Vetter wrote:
> On Wed, Aug 12, 2015 at 09:20:17AM +0300, Jani Nikula wrote:
>> On Wed, 12 Aug 2015, "Yang, Libin" wrote:
>> > Hi Jani,
>> >
>> >> -Original Message-
>> >> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>> >> Sent: Tuesday, August 11, 20
On Tue, Aug 11, 2015 at 06:12:04PM +0100, Chris Wilson wrote:
> On Tue, Aug 11, 2015 at 07:47:10PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Currently we don't clflush on pin_to_display if the bo is already
> > UC/WT and is not in the CPU write domain. This cause
On Tue, Aug 11, 2015 at 11:59:16AM -0400, Micah Fedke wrote:
>
> Update the drm_read test to operate on any platform to demonstrate the use of
> drm_open_driver(OPEN_ANY_GPU).
>
> To work on exynos, the event generation code is converted to use the new CRTC
> selection API for vblank. The first
On Tue, Aug 11, 2015 at 11:20:46PM +0100, Chris Wilson wrote:
> On Tue, Aug 11, 2015 at 05:59:23PM -0300, Tiago Vignatti wrote:
> > Userspace is the one in charge of flush CPU by wrapping mmap with
> > begin{,end}_cpu_access.
> >
> > v2: Remove LLC check cause we have dma-buf sync providers now. A
This WA doesn't have a name. According to WA ID 0555 in spec, driver need to
reset disable gather at set shader bit in per ctx WA batch. It is to be noted
that the default value is already '0' for this bit but we still need to apply
this WA because userspace may set it. If userspace really need it
On Wed, Aug 12, 2015 at 03:23:48PM +0530, vikas.korj...@intel.com wrote:
> From: vkorjani
>
> This patch adds code to initialize Picture Parameter set (PPS)
> data structure for DSC.
> DSC is enabled than the bitrate should be calculated using the
> formula pixel_clock * bits_per_pixel / lane_co
jn Wed, Aug 12, 2015 at 03:23:45PM +0530, vikas.korj...@intel.com wrote:
> From: vkorjani
>
> s RFC is for feature Display Stream Compression (DSC) for BXT,
> It is a VESA defined standard to compress and decompress image in display
> streams in a link independent manner. Some of the basic requir
On Wed, 12 Aug 2015, Daniel Vetter wrote:
> On Tue, Aug 11, 2015 at 04:49:33PM +0300, Mika Kahola wrote:
>> Depending on the VBT BDB version the maximum size
>> can be up to 38 bytes.
>>
>> This fix increases the maximum of the VBT expected size
>> from 33 bytes to 38 bytes and by doing so cures
On Wed, Aug 12, 2015 at 04:23:12PM +0300, Jani Nikula wrote:
> On Wed, 12 Aug 2015, Daniel Vetter wrote:
> > On Wed, Aug 12, 2015 at 09:20:17AM +0300, Jani Nikula wrote:
> >> On Wed, 12 Aug 2015, "Yang, Libin" wrote:
> >> > Hi Jani,
> >> >
> >> >> -Original Message-
> >> >> From: Jani Nik
On Wed, Aug 12, 2015 at 04:42:53PM +0300, Jani Nikula wrote:
> On Wed, 12 Aug 2015, Daniel Vetter wrote:
> > On Tue, Aug 11, 2015 at 04:49:33PM +0300, Mika Kahola wrote:
> >> Depending on the VBT BDB version the maximum size
> >> can be up to 38 bytes.
> >>
> >> This fix increases the maximum of
On Sun, Aug 09, 2015 at 01:12:53PM +0100, Chris Wilson wrote:
> We follow the VBT as to whether a DDI port is used for eDP and if so, do
> not attach a HDMI encoder to it. However there are machines for which
> the VBT eDP flag is a lie (shocking!) and we fail to detect a eDP link.
> Furthermore, o
On Wed, Aug 12, 2015 at 04:02:17PM +0300, Ville Syrjälä wrote:
> On Wed, Aug 12, 2015 at 05:31:55PM +0530, Sivakumar Thulasimani wrote:
> >
> >
> > On 8/12/2015 5:02 PM, Ville Syrjälä wrote:
> > > On Fri, Jul 31, 2015 at 11:32:52AM +0530, Sivakumar Thulasimani wrote:
> > >> From: "Thulasimani,Siv
On Wed, Aug 12, 2015 at 01:08:22PM +0100, Chris Wilson wrote:
> When we queue the command or operation to change the scanout address, we
> mark the flip as in progress. We can use this flag to prevent us from
> checking for a stalled flip prior to its existence!
>
> Signed-off-by: Chris Wilson
>
On Wed, Aug 12, 2015 at 04:45:39PM +0300, Ville Syrjälä wrote:
> > - /*
> > -* For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
> > -* for DP the encoder type can be set by the caller to
> > -* INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
> > -*/
> > - if (t
On Wed, 12 Aug 2015, Daniel Vetter wrote:
> On Wed, Aug 12, 2015 at 04:23:12PM +0300, Jani Nikula wrote:
>> On Wed, 12 Aug 2015, Daniel Vetter wrote:
>> > It sounds like we actually need to ping the audio side _before_ we do the
>>
>> Do you mean "read _HSW_AUD_STR_DESC_*" by "ping the audio sid
On Tue, Aug 11, 2015 at 12:29:17PM +0200, Lukas Wunner wrote:
> This is a follow-up to the v1 posted in April:
> http://lists.freedesktop.org/archives/dri-devel/2015-April/081515.html
>
>
> Patches 1 - 17 enable GPU switching on the pre-retina MacBook Pro.
> These were tested successfully by mult
On Wed, 12 Aug 2015, David Weinehall wrote:
> Some more fixup is needed; the bits from Antti's patch
> that actually expanded the struct to fully fit the newer
> versions of the child_device_config was part of the second
> patch; since that patch hasn't been merged yet we need this bit:
>
> This a
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7093
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Hi Tiago,
Thanks for the patch!
On 12 August 2015 at 02:29, Tiago Vignatti wrote:
> From: Daniel Vetter
>
> FIXME: Update kerneldoc for begin/end to make it clear that those are
> for mmap too.
I think if we're going to add this patch upstream, atleast the FIXMEs
should be fixed.
>
> Open: Do
On Thu, 16 Jul 2015, Damien Lespiau wrote:
> On Thu, Jul 16, 2015 at 07:36:51PM +0300, Mika Kuoppala wrote:
>> Fix divide by zero if we end up updating the watermarks
>> with zero dotclock.
>>
>> This is a stop gap measure to allow module load in cases
>> where our state keeping fails.
>>
>> v2:
On Wed, Aug 12, 2015 at 03:14:53PM +0100, Chris Wilson wrote:
> On Wed, Aug 12, 2015 at 04:45:39PM +0300, Ville Syrjälä wrote:
> > > - /*
> > > - * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
> > > - * for DP the encoder type can be set by the caller to
> > > - * INTEL_OUTPUT
Hi Daniel,
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Wednesday, August 12, 2015 9:05 PM
> To: Jani Nikula
> Cc: Yang, Libin; alsa-de...@alsa-project.org; ti...@suse.de; intel-
> g...@lists.freedesktop.org; daniel.vet...@
Hi Daniel,
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Wednesday, August 12, 2015 9:06 PM
> To: Jani Nikula
> Cc: Yang, Libin; alsa-de...@alsa-project.org; ti...@suse.de; intel-
> g...@lists.freedesktop.org; daniel.vet...@
On Wed, Aug 12, 2015 at 04:54:09PM +0300, Ville Syrjälä wrote:
> On Wed, Aug 12, 2015 at 01:08:22PM +0100, Chris Wilson wrote:
> > When we queue the command or operation to change the scanout address, we
> > mark the flip as in progress. We can use this flag to prevent us from
> > checking for a st
On Wed, 12 Aug 2015, "Yang, Libin" wrote:
> Hi Daniel,
>
>> -Original Message-
>> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
>> Daniel Vetter
>> Sent: Wednesday, August 12, 2015 9:06 PM
>> To: Jani Nikula
>> Cc: Yang, Libin; alsa-de...@alsa-project.org; ti...@suse.de;
From: Alex Dai
Allocate a GEM object to hold GuC log data. A debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
v2:
Add struct members at point of use [Chris Wilson]
v6:
Rebased
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drive
This patch series enables command submission via the GuC. In this mode,
instead of the host CPU driving the execlist port directly, it hands
over work items to the GuC, using a doorbell mechanism to tell the GuC
that new items have been added to its work queue. The GuC then dispatches
contexts to t
GuC submission is basically execlist submission, but with the GuC
handling the actual writes to the ELSP and the resulting context
switch interrupts. So to describe a context for submission via
the GuC, we need one of the same functions used in execlist mode.
This commit exposes one such function,
From: Alex Dai
The new node provides access to the status of the GuC-specific loader;
also the scratch registers used for communication between the i915
driver and the GuC firmware.
v2:
Changes to output formats per Chris Wilson's suggestions
v6:
Rebased
Issue: VIZ-4884
Signed-off-by:
From: Alex Dai
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes
From: Alex Dai
This adds the first of the data structures used to communicate with the
GuC (the pool of guc_context structures).
We create a GuC-specific wrapper round the GEM object allocator as all
GEM objects shared with the GuC must be pinned into GGTT space at an
address that is NOT in the
This provides a means of reading status and counts relating
to GuC actions and submissions.
v2:
Remove surplus blank line in output [Chris Wilson]
v5:
Added GuC per-engine submission & seqno statistics
v6:
Add per-ring statistics to client, refactor client-dumper.
Signed-off-by: Dav
Turn on interrupt steering to route necessary interrupts to GuC.
v6:
Rebased
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_reg.h | 11 +--
drivers/gpu/drm/i915/intel_guc_loader.c | 51 +
2 files
A GuC client has its own doorbell and workqueue. It maintains the
doorbell cache line, process description object and work queue item.
A default guc_client is created for the i915 driver to use for
normal-priority in-order submission.
Note that the created client is not yet ready for use; doorbel
From: Alex Dai
This fetches the required firmware image from the filesystem,
then loads it into the GuC's memory via a dedicated DMA engine.
This patch is derived from GuC loading work originally done by
Vinit Azad and Ben Widawsky.
v2:
Various improvements per review comments by Chris Wils
For both patches,
Reviewed-by: Ander Conselvan de Oliveira
On Tue, 2015-08-11 at 12:31 +0200, Maarten Lankhorst wrote:
> This patch is based on the upstream commit 5ac1c4bcf073ad and amended
> for v4.2 to make sure it works as intended.
>
> Repeated calls to begin_crtc_commit can cause warnings
Hi Jani,
> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Wednesday, August 12, 2015 10:45 PM
> To: Yang, Libin; Daniel Vetter
> Cc: alsa-de...@alsa-project.org; ti...@suse.de; intel-
> g...@lists.freedesktop.org; daniel.vet...@ffwll.ch
> Subject: RE: [
On 12/08/15 15:43, Dave Gordon wrote:
This patch series enables command submission via the GuC. In this mode,
instead of the host CPU driving the execlist port directly, it hands
over work items to the GuC, using a doorbell mechanism to tell the GuC
that new items have been added to its work queu
On 12/08/15 08:56, Thierry, Michel wrote:
On 8/11/2015 1:05 PM, Zhiyuan Lv wrote:
Hi Mika/Dave/Michel,
I saw the patch of using LRI for root pointer update has been merged to
drm-intel. When we consider i915 driver to run inside a virtual machine, e.g.
with XenGT, we may still need Mika's this
Hi Daniel,
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Wednesday, August 12, 2015 9:43 PM
> To: Jani Nikula
> Cc: Daniel Vetter; Yang, Libin; alsa-de...@alsa-project.org;
> ti...@suse.de; intel-gfx@lists.freedesktop.org; d
On 11/08/15 15:44, Arun Siluvery wrote:
From: Mika Kuoppala
Prevent leaking the if scoping by containing the WA_REG
macro inside its own scope.
Reported-by: Arun Siluvery
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
1 file changed, 2 insertions(+), 2
On 11/08/15 15:44, Arun Siluvery wrote:
From Gen9, Push constant instruction parsing behaviour varies according to
whether set shader is enabled or not. If we want legacy behaviour then it
can be achieved by disabling set shader.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89959
Cc:
From: Ville Syrjälä
Indent the PORTx_HOTPLUG_... defines appropriately, and fix some space
vs. tab issues.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 72 +
1 file changed, 37 insertions(+), 35 deletions(-)
diff --git a/drivers/gp
From: Ville Syrjälä
The PORTA HPD defines are not BXT specific. They also exist on SPT,
and partially already on LPT:LP.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
From: Ville Syrjälä
I've had a bunch of this stuff sitting in a branch for quite a while, almost a
year by the looks of the git dates :P I also had port E HPD in there but
something similar has already landed in the meantime so I just rebased my
junk on top.
I've only quickly tested the port A H
From: Ville Syrjälä
ILK/SNB support port A HPD. While HPD is optional on eDP let's at least
try to wite it up so that we might notice if the link has issues.
The eDP spec suggests that if HPD is not wired up, one should poll the
link status instead. We don't even do that currently.
Signed-off-b
From: Ville Syrjälä
Supposedly we have to enable port A HPD also in the south on LPT:LP.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d994b80..de601
From: Ville Syrjälä
Wire up the port A HPD for BDW. Compared to earlier platforms the
interrupt setup is a bit different, but basically everything else
looks the same.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 72 +
1 file change
From: Ville Syrjälä
Make LPT:LP checks look neater by wrapping the details in a
new HAS_PCH_LPT_LP() macro.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 13 +
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
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