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> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Gore, Tim
> Sent: Wednesday, June 03, 2015 9:43 AM
> To: Chris Wilson
> Cc: intel-gfx@lists.freedesktop.org; Wood, Thomas
> Subject: Re: [Intel-gfx] [PATCH i-g-t] tests/gem_reset_stats :
For old-school component TV and CRT connectors, we require a heavyweight
load-detection mechanism. This involves setting up a CRTC and sending a
signal to the output, before reading back any response. As that is quite
slow and CPU heavy, the process is only performed when the output
detection is fo
On Fri, Jun 05, 2015 at 07:39:13AM +, Gore, Tim wrote:
> However it would still be good to get this fix in for now. I'll start looking
> At removing the use of stop_rings from IGT when I've finished my current
> Crop of HSD's, so if someone could push this patch it would be appreciated.
> One l
On Thu, 04 Jun 2015, Ville Syrjälä wrote:
> On Thu, Jun 04, 2015 at 04:24:43PM +0300, Jani Nikula wrote:
>> On Wed, 03 Jun 2015, Mika Kahola wrote:
>> > From: Ville Syrjälä
>> >
>> > ilk_get_aux_clock_divider() is now a subset of
>> > hsw_get_aux_clock_divider() so unify them.
>>
>> I do like t
On Fri, 05 Jun 2015, "m...@ellerman.id.au" wrote:
> Hi Dave,
>
> Today's linux-next merge of the drm tree got a conflict in
> drivers/gpu/drm/i915/intel_ringbuffer.c between commit 4f47c99a9be7
> ("drm/i915:
> Move WaBarrierPerformanceFixDisable:skl to skl code from chv code") from the
> drm-inte
In next, it was fixed by
http://cgit.freedesktop.org/drm-intel/commit/drivers/gpu/drm/i915/i915_gem_execbuffer.c?h=for-linux-next&id=c7c7372edc4ebc173ad359aeb5752e9ce09f2741
In 4.1, the problem only exists with the marked-as-unsafe parameter
i915.enable_ppgtt=2. (It could be fixed there with
On Thu, 04 Jun 2015, Rodrigo Vivi wrote:
> I just noticed that I had forgotten to reply-all...
>
> Jani, would you consider merge this fix with the explanation above
> related to Ville's question?
>
> or do you want/need any action here?
Ville's question, I'd like Ville's ack on it.
BR,
Jani.
Done.
I'll wait abit any other review responses then update the patch.
Peter.
-Original Message-
From: Matt Turner [mailto:matts...@gmail.com]
Sent: Thursday, June 4, 2015 10:33 PM
To: Antoine, Peter
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915 : Added P
On Thu, 04 Jun 2015, Rodrigo Vivi wrote:
> 04 is the minor version. API version is ver1.
> So let's follow same scheme used on published version at 01.org.
>
> If really needed the minor version a follow-up updated will be
> done. But for now we need to move fwd and unblock end users.
>
> Signed-o
On Fri, Jun 05, 2015 at 11:51:42AM +0300, Jani Nikula wrote:
> On Thu, 04 Jun 2015, Rodrigo Vivi wrote:
> > I just noticed that I had forgotten to reply-all...
> >
> > Jani, would you consider merge this fix with the explanation above
> > related to Ville's question?
> >
> > or do you want/need an
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On Thu, 04 Jun 2015, Ville Syrjälä wrote:
> On Thu, Jun 04, 2015 at 04:56:18PM +0100, Damien Lespiau wrote:
>> I noticed one of those and it turned out we have a few lingering around.
>
> Yuck. I'd prefer we got the other way. Consider the following diffs for
> example:
What's the, uh, diff betw
Hi Sonika,
Thanks for your suggestion. Will follow that from next time.
Regards
Kausal
On Friday 05 June 2015 09:31 AM, Jindal, Sonika wrote:
HI Kausal,
You don't need to send the entire series again .
Just send the updated patch --in-reply-to to the last message.
Otherwise the thread gets lo
On Fri, Jun 05, 2015 at 12:24:45PM +0300, Jani Nikula wrote:
> On Thu, 04 Jun 2015, Ville Syrjälä wrote:
> > On Thu, Jun 04, 2015 at 04:56:18PM +0100, Damien Lespiau wrote:
> >> I noticed one of those and it turned out we have a few lingering around.
> >
> > Yuck. I'd prefer we got the other way.
[ Please CC me I am not subscribed to this ML ]
Hi,
I have upgraded my llvm-toolchain to v3.6.1 and while at this updated
my Linux graphics driver stack on Ubuntu/precise AMD64.
This is the cool stuff...
libdrm-2-4-61
mesa-10-5-6 and mesa-10-5-6-24-g07aa6d78bbc9
GOOD: intelddx-2-99-917-312-ga6
On Fri, Jun 05, 2015 at 11:44:59AM +0200, Sedat Dilek wrote:
> [ Please CC me I am not subscribed to this ML ]
>
> Hi,
>
> I have upgraded my llvm-toolchain to v3.6.1 and while at this updated
> my Linux graphics driver stack on Ubuntu/precise AMD64.
>
> This is the cool stuff...
>
> libdrm-2-4
On Fri, Jun 05, 2015 at 12:27:21PM +0300, Ville Syrjälä wrote:
> On Fri, Jun 05, 2015 at 12:24:45PM +0300, Jani Nikula wrote:
> > On Thu, 04 Jun 2015, Ville Syrjälä wrote:
> > > On Thu, Jun 04, 2015 at 04:56:18PM +0100, Damien Lespiau wrote:
> > >> I noticed one of those and it turned out we have
Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid scratch obj
before we initialize WA.
Signed-off-by: Michel Thierry
Signed-off-by: Aru
In Indirect and Per context w/a batch buffer,
+WaDisableCtxRestoreArbitration
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_lrc.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/dr
In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 8
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are created for this purpose and these WA cannot
be applied using normal means. Each context has two registers to l
From Gen8+ we have some workarounds that are applied Per context and
they are applied using special batch buffers called as WA batch buffers.
HW executes them at specific stages during context save/restore.
The patches in this series adds this framework to i915.
I did some basic testing on BDW by
In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch
v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville)
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 24 +
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
MI_LOAD_REGISTER_REG; Add GEN8 specific defines for these instructions
so as to not break any future users of existing definitions (Michel)
Signed-off-by: Rafael Barbalho
S
On Fri, Jun 05, 2015 at 12:05:22PM +0200, Sedat Dilek wrote:
> Hi Chris,
>
> thanks for the quick reply.
>
> Attached are my kernel-config, dmesg and X logs plus my build-script.
>
> Hope this helps you.
Haven't gone through with finetooth comb yet, but I didn't spot the red
flag I was looking
On Fri, Jun 5, 2015 at 12:38 PM, Chris Wilson wrote:
> On Fri, Jun 05, 2015 at 12:05:22PM +0200, Sedat Dilek wrote:
>> Hi Chris,
>>
>> thanks for the quick reply.
>>
>> Attached are my kernel-config, dmesg and X logs plus my build-script.
>>
>> Hope this helps you.
>
> Haven't gone through with fi
On 04/06/2015 15:07, John Harrison wrote:
On 02/06/2015 19:16, Tomas Elf wrote:
On 29/05/2015 17:43, john.c.harri...@intel.com wrote:
From: John Harrison
The i915_add_request() function is called to keep track of work that
has been
written to the ring buffer. It adds epilogue commands to trac
On Fri, Jun 05, 2015 at 11:34:01AM +0100, Arun Siluvery wrote:
> Some of the WA are to be applied during context save but before restore and
> some at the end of context save/restore but before executing the instructions
> in the ring, WA batch buffers are created for this purpose and these WA cann
On Fri, Jun 05, 2015 at 11:34:01AM +0100, Arun Siluvery wrote:
> + /* FIXME: fill unused locations with NOOPs.
> + * Replace these instructions with WA
> + */
> +while (index < end)
> + reg_state[index++] = MI_NOOP;
I found calling it reg_state was very confusing.
On Fri, Jun 05, 2015 at 12:56:48PM +0200, Sedat Dilek wrote:
> Attached are dmesg and X logs.
> Last thing I did was to kill lightdm service.
>
> Have more fun.
Ok, no errors reported by the kernel and the cursor seems to be updating
fine.
There's a utility xf86-video-intel/tools/cursor which yo
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On 05/06/2015 11:56, Chris Wilson wrote:
On Fri, Jun 05, 2015 at 11:34:01AM +0100, Arun Siluvery wrote:
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are crea
On Fri, Jun 05, 2015 at 12:24:58PM +0100, Siluvery, Arun wrote:
> ok, it is possible to do the allocation and setup in
> logical_ring_init() itself. I wanted to group it with other wa which
> are setup in init_context().
Phew, I had worried I had missed something. The issue the current split
betwe
Culprit commit is "sna: Compilation fixes for stable distros" (see
attached files).
Reverting this commit fixes the issue for me.
$ git log --oneline -3
ee885de7ad39 Revert "sna: Compilation fixes for stable distros"
7d30ccea214b sna: Ensure compat_output is sane after sorting outputs
1525b017786
On Fri, Jun 05, 2015 at 01:41:25PM +0200, Sedat Dilek wrote:
> Culprit commit is "sna: Compilation fixes for stable distros" (see
> attached files).
>
> Reverting this commit fixes the issue for me.
>
> $ git log --oneline -3
> ee885de7ad39 Revert "sna: Compilation fixes for stable distros"
> 7d3
On 05/06/2015 12:36, Chris Wilson wrote:
On Fri, Jun 05, 2015 at 12:24:58PM +0100, Siluvery, Arun wrote:
ok, it is possible to do the allocation and setup in
logical_ring_init() itself. I wanted to group it with other wa which
are setup in init_context().
Phew, I had worried I had missed somet
On 6/4/2015 7:12 PM, Kausal Malladi wrote:
From: Kausal Malladi
This patch adds a new structure in DRM layer for Gamma color correction.
This structure will be used by all user space agents to configure
appropriate Gamma precision and Gamma level.
struct drm_intel_gamma {
__u32 gamma
Hi Sonika,
Please find my responses inline.
Thanks,
Kausal
On Friday 05 June 2015 05:30 PM, Jindal, Sonika wrote:
On 6/4/2015 7:12 PM, Kausal Malladi wrote:
From: Kausal Malladi
This patch adds a new structure in DRM layer for Gamma color correction.
This structure will be used by all use
On Thu, Jun 04, 2015 at 06:21:29PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
For patches 1-6
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> d
On Thu, Jun 04, 2015 at 06:21:35PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_display.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a232dc9
2015-06-04 14:23 GMT-03:00 Damien Lespiau :
> Signed-off-by: Damien Lespiau
For both patches: Reviewed-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debu
On Fri, Jun 05, 2015 at 03:24:45PM +0300, Ville Syrjälä wrote:
> On Thu, Jun 04, 2015 at 06:21:35PM +0100, Damien Lespiau wrote:
> > Signed-off-by: Damien Lespiau
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i
2015-06-04 14:32 GMT-03:00 Damien Lespiau :
> Signed-off-by: Damien Lespiau
> ---
> tests/pm_rpm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
> index a1f4013..2a83a75 100644
> --- a/tests/pm_rpm.c
> +++ b/tests/pm_rpm.c
> @@ -669,9
On Fri, Jun 05, 2015 at 01:40:29PM +0100, Damien Lespiau wrote:
> On Fri, Jun 05, 2015 at 03:24:45PM +0300, Ville Syrjälä wrote:
> > On Thu, Jun 04, 2015 at 06:21:35PM +0100, Damien Lespiau wrote:
> > > Signed-off-by: Damien Lespiau
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 4
>
Hi Dave, sorry I'm late with the fixes pull and I see you already sent
yours forward to Linus too. If you get the vibes there might be a
release this weekend, would be nice to get these in. Otherwise can wait
until next week, and I might have a few more on top then.
BR,
Jani.
The following chang
From: Minu
Display CRCs were not readable because the register defintions
for PORT_DFT_I9XX and PORT_DFT2_G4X were wrong.
MMIO offset needs to be added to these register offsets to fix them.
Issue: GMINL-6869
Signed-off-by: Minu Mathai
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed
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On Fri, Jun 05, 2015 at 02:00:24PM +0100, Minu Mathai wrote:
> From: Minu
>
> Display CRCs were not readable because the register defintions
> for PORT_DFT_I9XX and PORT_DFT2_G4X were wrong.
> MMIO offset needs to be added to these register offsets to fix them.
>
> Issue: GMINL-6869
> Signed-off
On Fri, Jun 5, 2015 at 2:09 PM, Sedat Dilek wrote:
> On Fri, Jun 5, 2015 at 1:57 PM, Sedat Dilek wrote:
>> On Fri, Jun 5, 2015 at 1:51 PM, Chris Wilson
>> wrote:
>>> On Fri, Jun 05, 2015 at 01:41:25PM +0200, Sedat Dilek wrote:
Culprit commit is "sna: Compilation fixes for stable distros" (
On Fri, Jun 5, 2015 at 3:17 PM, Sedat Dilek wrote:
> On Fri, Jun 5, 2015 at 2:09 PM, Sedat Dilek wrote:
>> On Fri, Jun 5, 2015 at 1:57 PM, Sedat Dilek wrote:
>>> On Fri, Jun 5, 2015 at 1:51 PM, Chris Wilson
>>> wrote:
On Fri, Jun 05, 2015 at 01:41:25PM +0200, Sedat Dilek wrote:
> Culp
On 05/06/15 11:04, Damien Lespiau wrote:
> On Fri, Jun 05, 2015 at 12:27:21PM +0300, Ville Syrjälä wrote:
>> On Fri, Jun 05, 2015 at 12:24:45PM +0300, Jani Nikula wrote:
>>> On Thu, 04 Jun 2015, Ville Syrjälä wrote:
On Thu, Jun 04, 2015 at 04:56:18PM +0100, Damien Lespiau wrote:
> I notic
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are created for this purpose and these WA cannot
be applied using normal means. Each context has two registers to l
Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid scratch obj
before we initialize WA.
Signed-off-by: Michel Thierry
Signed-off-by: Aru
In Indirect and Per context w/a batch buffer,
+WaDisableCtxRestoreArbitration
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_lrc.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/dr
In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 8
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm
In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch
v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville)
Signed-off-by: Rafael Barbalho
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 24 +
In Per context w/a batch buffer,
WaRsRestoreWithPerCtxtBb
v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
MI_LOAD_REGISTER_REG; Add GEN8 specific defines for these instructions
so as to not break any future users of existing definitions (Michel)
Signed-off-by: Rafael Barbalho
S
On 27/05/15 10:17, David Weinehall wrote:
> On Thu, May 21, 2015 at 10:50:37AM +0100, Chris Wilson wrote:
>> It also have just as much risk as reporting EBUSY due to the CL client
>> trying to use a pinned buffer.
>>
>> However, it is a security hole because the same process can arrange to
>> have
If I revert the first hunk of the culprit the issue is gone.
I will send a patch.
- sed@ -
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Fixes a problem having no mouse cursor in the LightDM login-screen
on Ubuntu/precise (see [1]).
[1] http://lists.freedesktop.org/archives/intel-gfx/2015-June/068096.html
Fixes: 7d30ccea214b ("sna: Compilation fixes for stable distros")
Signed-off-by: Sedat Dilek
---
src/sna/kgem.c | 3 +--
1 fi
On Fri, Jun 05, 2015 at 04:23:10PM +0200, Sedat Dilek wrote:
> If I revert the first hunk of the culprit the issue is gone.
Oh, boy. I was blind. I knew I should have just used the ring ids..
Thanks a lot for the investigation and patch.
-Chris
--
Chris Wilson, Intel Open Source Technology Cent
On Fri, Jun 05, 2015 at 04:23:36PM +0200, Sedat Dilek wrote:
> Fixes a problem having no mouse cursor in the LightDM login-screen
> on Ubuntu/precise (see [1]).
>
> [1] http://lists.freedesktop.org/archives/intel-gfx/2015-June/068096.html
>
> Fixes: 7d30ccea214b ("sna: Compilation fixes for stabl
On Fri, Jun 5, 2015 at 4:31 PM, Chris Wilson wrote:
> On Fri, Jun 05, 2015 at 04:23:36PM +0200, Sedat Dilek wrote:
>> Fixes a problem having no mouse cursor in the LightDM login-screen
>> on Ubuntu/precise (see [1]).
>>
>> [1] http://lists.freedesktop.org/archives/intel-gfx/2015-June/068096.html
>
This change adds the programming of the MOCS registers to the gen 9+
platforms. This change set programs the MOCS register values to a set
of values that are defined to be optimal.
It creates a fixed register set that is programmed across the different
engines so that all engines have the same tab
On Fri, Jun 05, 2015 at 02:56:48PM +0100, Arun Siluvery wrote:
> In Indirect context w/a batch buffer,
> +WaFlushCoherentL3CacheLinesAtContextSwitch
>
> Signed-off-by: Rafael Barbalho
> Signed-off-by: Arun Siluvery
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_lrc
On Fri, Jun 5, 2015 at 4:27 PM, Chris Wilson wrote:
> On Fri, Jun 05, 2015 at 04:23:10PM +0200, Sedat Dilek wrote:
>> If I revert the first hunk of the culprit the issue is gone.
>
> Oh, boy. I was blind. I knew I should have just used the ring ids..
>
> Thanks a lot for the investigation and patc
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On Fri, Jun 05, 2015 at 04:39:32PM +0200, Sedat Dilek wrote:
> On Fri, Jun 5, 2015 at 4:31 PM, Chris Wilson wrote:
> > On Fri, Jun 05, 2015 at 04:23:36PM +0200, Sedat Dilek wrote:
> >> Fixes a problem having no mouse cursor in the LightDM login-screen
> >> on Ubuntu/precise (see [1]).
> >>
> >> [1
automake 1.14 was complaining here:
overlay/Makefile.am:44: warning: source file 'x11/x11-window.c' is in a
subdirectory, but option 'subdir-objects' is disabled.
Signed-off-by: Damien Lespiau
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/co
On Fri, Jun 5, 2015 at 4:51 PM, Chris Wilson wrote:
> On Fri, Jun 05, 2015 at 04:39:32PM +0200, Sedat Dilek wrote:
>> On Fri, Jun 5, 2015 at 4:31 PM, Chris Wilson
>> wrote:
>> > On Fri, Jun 05, 2015 at 04:23:36PM +0200, Sedat Dilek wrote:
>> >> Fixes a problem having no mouse cursor in the Light
On Fri, Jun 05, 2015 at 03:43:36PM +0100, Peter Antoine wrote:
> This change adds the programming of the MOCS registers to the gen 9+
> platforms. This change set programs the MOCS register values to a set
> of values that are defined to be optimal.
>
> It creates a fixed register set that is prog
v2: Try first to open i915_pc8_status to make the transition (or just
running on older kernels) better. (Paulo)
Signed-off-by: Damien Lespiau
---
tests/pm_rpm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
index a1f4013..238a6e3 100644
-
The same entries have different requirement sources. I'll see if I can find
some communality.
Also, I might change some of the numbers to user named values and that may make
it easier to work out the usage.
Peter.
-Original Message-
From: Lespiau, Damien
Sent: Friday, June 5, 2015 3:5
A safer way to update the PDPx registers is sending lri commands, added in
the ring before the batchbuffer start. Otherwise, the ctx must be idle before
trying to change anything (but the ring-tail) in the ctx image. An
example where the ctx won't be idle is lite-restore.
This patch depends on [1]
Sorry. I know I asked some questions last time around, but I am having trouble
finding the response.
On Tue, May 05, 2015 at 09:53:55AM +0100, Chris Wilson wrote:
> Convert the bo-cache into 2 phases:
>
> 1. A two second cache of recently used buffers, keep untouched.
> 2. A two second cache of o
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On Fri, Jun 05, 2015 at 09:34:23AM -0700, Ben Widawsky wrote:
> Sorry. I know I asked some questions last time around, but I am having trouble
> finding the response.
You thought the existing code used a one second timeout and so wanted a
separated patch to convert from age <= 1 to age < 2.
Other
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Platform Delta drm-intel-nightly Series Applied
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> >> @@ -396,6 +377,24 @@ int intel_atomic_setup_scalers(struct
> drm_device
> > *dev,
> >>}
> >>}
> >>
> >> + /* plane not part of mask must leave hq mode? */
> >> + if (num_scalers_need > 1 && scaler_state->scalers[0].in_use &&
> >
On 05/29/2015 07:35 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 07:23:35PM +0200, Mario Kleiner wrote:
On 05/29/2015 07:19 PM, Daniel Vetter wrote:
On Fri, May 29, 2015 at 06:50:06PM +0200, Mario Kleiner wrote:
On 05/27/2015 11:04 AM, Daniel Vetter wrote:
In
commit 9cba5efab5a8145ae6c
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6544
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1
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The following changes since commit 3161bfa479d5e9ed4f46b57df9bcecbbc4f8eb3c:
linux-firmware: Update firmware patch for Intel Bluetooth 7260 (B3/B4)
(2015-05-13 11:12:48 -0400)
are available in the git repository at:
ssh://people.freedesktop.org/~vivijim/linux-firmware-i915 master
for you t
We need to call drm_atomic_set_mode_for_crtc() rather than copying the
mode in manually. As of commit
commit 99cf4a29fa24461bbfe22125967188a18383eb5c
Author: Daniel Stone
Date: Mon May 25 19:11:51 2015 +0100
drm/atomic: Add current-mode blob to CRTC state
Due to RTL Bug, GAM does not support enabling GTT cache when
big pages are also turned on. This leads to GAM reporting
incorrect data and address.
For A0 let the register GTT_CACHE_EN use the default value[0x].
For B0 onwards enable the GTT cache by setting the GTT_CACHE_EN[04024h]
to value
Override Cacheability to WB in LLC/eLLC - Aged 3 1000
for better performance.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d091fec..b0f
On Thu, Jun 04, 2015 at 07:12:32PM +0530, Kausal Malladi wrote:
> From: Kausal Malladi
>
> Color Manager is an extension in i915 driver to handle color correction
> and enhancements across various Intel platforms.
>
> This patch initializes color manager framework by :
> 1. Adding two new files,
On Thu, Jun 04, 2015 at 07:12:36PM +0530, Kausal Malladi wrote:
> From: Kausal Malladi
>
> This patch adds a new function to update color blob properties
> and exports it.
>
> v2: Addressing Sonika's comment,
> 1. Moved this function to a separate patch
> 2. Removed one input parameter to the fu
On Thu, Jun 04, 2015 at 07:12:35PM +0530, Kausal Malladi wrote:
> From: Kausal Malladi
>
> This patch adds a new structure in DRM layer for Gamma color correction.
> This structure will be used by all user space agents to configure
> appropriate Gamma precision and Gamma level.
>
> struct drm_in
On Thu, Jun 04, 2015 at 07:12:37PM +0530, Kausal Malladi wrote:
> From: Kausal Malladi
>
> The atomic CRTC set infrastructure is not available yet. So, the atomic
> check path throws error for any non-plane property.
>
> This patch adds a diversion to avoid commit path for DRM atomic set Gamma
>
On 6/4/2015 7:12 PM, Kausal Malladi wrote:
From: Kausal Malladi
This patch does the following:
1. Adds the core function to program Gamma correction values for CHV/BSW
platform
2. Adds Gamma correction macros/defines
3. Adds drm_mode_crtc_update_color_property function, which replaces the
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6546
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Op 05-06-15 om 21:05 schreef Konduru, Chandra:
@@ -396,6 +377,24 @@ int intel_atomic_setup_scalers(struct
>> drm_device
>>> *dev,
}
}
+ /* plane not part of mask must leave hq mode? */
+ if (num_scalers_need >
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