[Intel-gfx] [PATCH 00/13] Update of the HDMI DPLL dividers computation

As explained in the important patch of this series: The HW validation team came back from further testing with a slightly changed constraint on the deviation between the DCO frequency and the central frequency. Instead of +-4%, it's now +1%/-6%. Unfortunately, the previous alg

[Intel-gfx] [PATCH 02/13] drm/i915/skl: Make sure to break when not finding suitable PLL dividers

Right now, when finishing the cycle with odd dividers without finding a suitable candidate, we end up in an infinite loop. Make sure to break in that case. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i

[Intel-gfx] [PATCH 05/13] drm/i915/skl: Use a more idomatic early return

We can coalesce the WARN() condition with the WARN() itself and, as we are returning early, we can de-intent the rest of the function. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 121 +++ 1 file changed, 59 insertions(+), 62 deletions(

[Intel-gfx] [PATCH 06/13] drm/i915/skl: Factor out computing the DPLL paramaters from the dividers

This part doesn't depend on how we compute the DPLL dividers (p and p0/p1/p2) and can be reused even if we change the algorithm to do so. (something that is planned for a followup patch) Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 139 +---

[Intel-gfx] [PATCH 04/13] drm/i915/skl: Propagate the error if we fail to find a suitable DPLL divider

At the moment, even if we fail to find a suitable divider, we'll still try to set the mode with bogus parameters. Just fail the modeset if we can't generate the frequency. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletio

[Intel-gfx] [PATCH 08/13] drm/i915/skl: Remove unnecessary () used with abs_diff()

abs_diff() properly protects its parameters, so no need for the outer () here. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index fd90771.

[Intel-gfx] [PATCH 11/13] drm/i915/skl: Don't try to store the wrong central frequency

The orignal code started by storing the actual central frequency (in Hz, using a uint64_t) in a uint32_t which codes for the register value. That can't be right. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/dr

[Intel-gfx] [PATCH 13/13] drm/i915/skl: Prefer even dividers for SKL DPLLs

Currently, if an odd divider improves the deviation (minimizes it), we take that divider. The recommendation is to prefer even dividers. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c

[Intel-gfx] [PATCH 01/13] drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()

A part of this function was indented with 2 tabs and 1 space instead of just 2 tabs. We're going to touch that code, so start by re-indenting it. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 64 1 file changed, 32 insertions(+), 32

[Intel-gfx] [PATCH 07/13] drm/i915/skl: Remove unnecessary () used with div_u64()

div_u64() can be either a inline function or a define, but in either case it's safe to provide expressions as parameters without outer () around them. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/driv

[Intel-gfx] [PATCH 09/13] drm/i915/skl: Use MISSING_CASE() in skl_wrpll_params_populate()

We now have a special macro for those cases. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index b9d5d65..ab327a1 100644 --- a/drivers/

[Intel-gfx] [PATCH 12/13] drm/i915/skl: Replace the HDMI DPLL divider computation algorithm

The HW validation team came back from further testing with a slightly changed constraint on the deviation between the DCO frequency and the central frequency. Instead of +-4%, it's now +1%/-6%. Unfortunately, the previous algorithm didn't quite cope with these new constraints, the reason being tha

[Intel-gfx] [PATCH 03/13] drm/i915/skl: Display the WRPLL frequency we couldn't accomodate when failing

This helps debugging. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index da7aa0f..ff5eb05 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c

[Intel-gfx] [PATCH 10/13] drm/i915: Correctly prefix HSW/BDW HDMI clock functions

Those functions were the only one in existence when they were introduced. We now now they are only valid for HSW/BDW. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_ddi.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Update sprite watermarks outside vblank evasion

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6337 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

[Intel-gfx] [PATCH igt] lib/debugfs: wait_for_keypress("crc") when collecting CRC

From: Paulo Zanoni Let's just steal the "crc" namespace and add this by default to igt_pipe_crc_collect_crc() instead of adding more calls to other tests. If tests want special waits on just some of their collect_crc() calls, they can use another name instead of "crc". This is very useful when d

[Intel-gfx] [PATCH igt 1/8] tests/kms_fbc_crc: exec_nop() can also invalidate FBC

From: Paulo Zanoni So make sure that, at prepare_test(), we wait for FBC to be enabled again after we run the exec_nop() call. Since after this happens, we just assert fbc_enabled() at test_crc() instead of waiting for it to be enabled. This is now needed because we moved to software frontbuffer

[Intel-gfx] [PATCH igt 7/8] tests/kms_fbc_crc: extract fill_mmap_{cpu, gtt}()

From: Paulo Zanoni Just like we have fill_render() and fill_blt(). I'm also going to use fill_mmap_gtt() for the code that generates the reference CRCs. Signed-off-by: Paulo Zanoni --- tests/kms_fbc_crc.c | 35 +-- 1 file changed, 25 insertions(+), 10 deletions(

[Intel-gfx] [PATCH igt 0/8] Make kms_fbc_crc useful again

From: Paulo Zanoni After the recent IGT regressions and the FBC conversion to the frontbuffer tracking infrastructure, kms_fbc_crc was not being that useful anymore. So this series makes it useful again. The first 2 patches are alternate forms of patches that I already sent to the mailing list a

[Intel-gfx] [PATCH igt 4/8] tests/kms_fbc_crc: refactor context handling code

From: Paulo Zanoni Just a small modification to make the code a little easier to understand, IMHO. Signed-off-by: Paulo Zanoni --- tests/kms_fbc_crc.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/kms_fbc_crc.c b/tests/kms_fbc_crc.c index 20510ff..0f09a60

[Intel-gfx] [PATCH igt 6/8] tests/kms_fbc_crc: make the blt test draw the same pattern

From: Paulo Zanoni ... as the other drawing tests: single white pixel at top/left of the screen, instead of painting the whole screen blue. This will make it much easier to fix the CRC checking code. Signed-off-by: Paulo Zanoni --- tests/kms_fbc_crc.c | 5 +++-- 1 file changed, 3 insertions(+

[Intel-gfx] [PATCH igt 2/8] tests/kms_fbc_crc: increase the FBC wait timeout

From: Paulo Zanoni Now that we moved to the frontbuffer tracking scheme, it may take a long time for FBC to be updated after it is invalidated: 300ms is not enough anymore. The problem starts when i915_gem_execbuffer2() indirectly calls intel_fb_obj_invalidate(), which disables FBC. After this,

[Intel-gfx] [PATCH igt 5/8] tests/kms_fbc_crc: extract check_crc()

From: Paulo Zanoni To remove some duplicated code. When we finally fix that FIXME, the code will get a little bigger too. Signed-off-by: Paulo Zanoni --- tests/kms_fbc_crc.c | 26 ++ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/tests/kms_fbc_crc.c b/t

[Intel-gfx] [PATCH igt 3/8] tests/kms_fbc_crc: unify flip handling

From: Paulo Zanoni Just a small simplification to make the code a little easier to understand, and to help us when we further split drawing vs flipping later. Signed-off-by: Paulo Zanoni --- tests/kms_fbc_crc.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/km

[Intel-gfx] [PATCH igt 8/8] tests/kms_fb_crc: fix the reference CRC checking

From: Paulo Zanoni Now we get the reference CRCs on separate untiled FBs just to make sure FBC is not there to mess the CRC computation. We also get the reference CRCs for buffers that were drawn in the same way that we draw them during the tests, so we can finally get rid of that FIXME comment w

Re: [Intel-gfx] [PATCH 3/3] drm/i915/bxt: edp1.4 Intermediate Freq support

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6338 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

[Intel-gfx] [WARNING 4.1-rc2] i915: Unclaimed register detected before writing to register 0xc4040

[ cut here ] WARNING: CPU: 2 PID: 0 at /work/autotest/nobackup/linux-test.git/drivers/gpu/drm/i915/intel_uncore.c:566 hsw_unclaimed_reg_debug.isra.10+0x6c/0x84() Unclaimed register detected before writing to register 0xc4040 Modules linked in: microcode r8169 CPU: 2 P

Re: [Intel-gfx] [PATCH] Removing redundant is_edp_psr

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6339 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

[Intel-gfx] [PATCH] drm/i915: Set crtc_state->active to false when CRTC is disabled

With the recent modeset internal rework, we wind up setting crtc_state->enable to false, but leave crtc_state->active as true following a drmModeSetCrtc(fb=0), which is incorrect. This mismatch gets caught by drm_atomic_crtc_check() and causes subsequent atomic operations (such as plane updates wh

Re: [Intel-gfx] [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6340 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

Re: [Intel-gfx] [PATCH] drm/i915: Fix screen flickering on X

On Thu, 7 May 2015 15:18:27 +0100 Chris Wilson wrote: > On Thu, May 07, 2015 at 04:41:48PM +0300, Jani Nikula wrote: > > On Thu, 07 May 2015, Matt Roper wrote: > > > On Thu, May 07, 2015 at 12:12:18PM +0300, Jani Nikula wrote: > > >> On Thu, 23 Apr 2015, Chris Wilson > > >> wrote: > > >> > [cc'i

Re: [Intel-gfx] [PATCH] drm/i915: Set crtc_state->active to false when CRTC is disabled

On Thu, May 07, 2015 at 02:19:07PM -0700, Matt Roper wrote: > With the recent modeset internal rework, we wind up setting crtc_state->enable > to false, but leave crtc_state->active as true following a > drmModeSetCrtc(fb=0), which is incorrect. This mismatch gets caught by > drm_atomic_crtc_check

[Intel-gfx] [PATCH] drm/i915: Set crtc_state->active to false when CRTC is disabled (v2)

With the recent modeset internal rework, we wind up setting crtc_state->enable to false, but leave crtc_state->active as true, which is incorrect. This mismatch gets caught by drm_atomic_crtc_check() and causes subsequent atomic operations (such as plane updates while the CRTC is disabled) to fail

[Intel-gfx] VBIOS doesn't recognize the eDP port on Baytrail-I

Which VBIOS should be used with the Baytrail-I when trying to configure two local flat panels as eDP The EMGD VBIOS creates a device_type 0x1004 and the i915 drivers looks for a device_type=0x1806 so it seems that the EMGD VBIOS should not be used with the Open Source Graphic drivers. The O.S.

Re: [Intel-gfx] [PATCH v2 i-g-t 1/4] igt_kms: Avoid NULL ptr deref when commiting disabled planes

> >> diff --git a/lib/igt_kms.c b/lib/igt_kms.c index b7d1e90..33d437d > >> 100644 > >> --- a/lib/igt_kms.c > >> +++ b/lib/igt_kms.c > >> @@ -1331,7 +1331,7 @@ static int igt_drm_plane_commit(igt_plane_t > *plane, > >>fb_id = igt_plane_get_fb_id(plane); > >>crtc_id = output->config.crtc->cr

Re: [Intel-gfx] [PATCH i-g-t 3/4] igt_kms: Do not reset plane position on assigning a fb

> -Original Message- > From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] > Sent: Thursday, May 07, 2015 2:15 AM > To: Konduru, Chandra; Intel-gfx@lists.freedesktop.org > Cc: Ursulin, Tvrtko > Subject: Re: [PATCH i-g-t 3/4] igt_kms: Do not reset plane position on > assigning >

[Intel-gfx] [PATCH] drm/i915: perform scaler_id check for skl+

Scaler id is added for skylake to handle its shared scalers. This is not applicable for platforms before SKL. This patch limits the scaler_id check during intel_pipe_config_compare to platforms SKL and above. Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/intel_display.c |4 +++- 1

Re: [Intel-gfx] [i915]] *ERROR* mismatch in scaler_state.scaler_id

> -Original Message- > From: Sergey Senozhatsky [mailto:sergey.senozhat...@gmail.com] > Sent: Thursday, May 07, 2015 4:24 AM > To: Konduru, Chandra > Cc: Daniel Vetter; Sergey Senozhatsky; David Airlie; Vetter, Daniel; intel- > g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; li

Re: [Intel-gfx] [PATCH 06/11] drm/i915: Add NV12 as supported format for primary plane

> > +/* Primary plane formats for gen >= 9 */ > > +static const uint32_t intel_primary_formats_gen9[] = { > > + COMMON_PRIMARY_FORMATS, \ > > + DRM_FORMAT_XBGR, > > + DRM_FORMAT_ABGR, > > + DRM_FORMAT_XRGB2101010, > > + DRM_FORMAT_ARGB2101010, > > + DRM_FORMAT_XBGR2101010, > > +

Re: [Intel-gfx] [PATCH] drm/i915: Drop PIPE-A quirk for 945GSE HP Mini

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6342 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

Re: [Intel-gfx] [PATCH] igt/gem_create_stolen: Verifying extended gem_create ioctl

On Thu, 2015-05-07 at 08:52 +0200, Daniel Vetter wrote: > On Wed, May 06, 2015 at 03:51:52PM +0530, ankitprasad.r.sha...@intel.com > wrote: > > From: Ankitprasad Sharma > > > > This patch adds the testcases for verifying the new extended > > gem_create ioctl. By means of this extended ioctl, mem

[Intel-gfx] [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support

BXT supports following intermediate link rates for edp: 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz. Adding support for programming the intermediate rates. v2: Adding clock in bxt_clk_div struct and then look for the entry with required rate (Ville) v3: 'clock' has the selected value, no need to use link_b

Re: [Intel-gfx] [PATCH v3] drm/i915/bxt: eDP Panel Power sequencing

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6341 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

Re: [Intel-gfx] [PATCH] drm/i915: Remove locking for get-caching query

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6343 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1

Re: [Intel-gfx] [WARNING 4.1-rc2] i915: Unclaimed register detected before writing to register 0xc4040

On Thu, May 7, 2015 at 9:40 PM, Steven Rostedt wrote: > [ cut here ] > WARNING: CPU: 2 PID: 0 at > /work/autotest/nobackup/linux-test.git/drivers/gpu/drm/i915/intel_uncore.c:566 > hsw_unclaimed_reg_debug.isra.10+0x6c/0x84() > Unclaimed register detected before writing

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