Hi Takashi,
Our target is to apply the patches into intel-drm-nightly tree, It will be
great if you can help merge the patches into your tree. However I get a
negative test result on BYT platform auto test, I'll confirm if it's caused by
my patches, so please do not merge now and I'll give you
On 04/16/2015 03:03 PM, Daniel Vetter wrote:
On Thu, Apr 16, 2015 at 08:30:55AM -0400, Peter Hurley wrote:
On 04/15/2015 01:31 PM, Daniel Vetter wrote:
On Wed, Apr 15, 2015 at 09:00:04AM -0400, Peter Hurley wrote:
Hi Daniel,
On 04/15/2015 03:17 AM, Daniel Vetter wrote:
This was a bit too muc
On 04/15/2015 03:03 AM, Mario Kleiner wrote:
On 04/02/2015 01:34 PM, Chris Wilson wrote:
On vblank instant-off systems, we can get into a situation where the cost
of enabling and disabling the vblank IRQ around a drmWaitVblank query
dominates. However, we know that if the user wants the curren
On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
v3: Updated bias se
On 4/30/2015 4:53 PM, Jani Nikula wrote:
On Thu, 30 Apr 2015, Imre Deak wrote:
On to, 2015-04-30 at 13:07 +0530, Vandana Kannan wrote:
Second set of PPS registers have been defined but will be used when VBT
provides a selection between the 2 sets of registers.
Signed-off-by: Vandana Kannan
Changes based on future platform readiness patches related to
HAS_PCH_SPLIT(). Use HAS_GMCH_DISPLAY() instead of HAS_PCH_SPLIT.
BXT does not have PP_DIV register. Making changes to handle this.
Second set of PPS registers have been defined but will be used when VBT
provides a selection between the
