-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 04/10/2015 01:59 PM, Thierry Reding wrote:
> On Wed, Apr 01, 2015 at 11:58:50AM +0530, Shobhit Kumar wrote:
>> -BEGIN PGP SIGNED MESSAGE- Hash: SHA1
>>
>> On 03/24/2015 01:53 PM, Thierry Reding wrote:
>>> On Fri, Mar 13, 2015 at 07:28:02PM
Because they can be.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a0be6ab7ba7b..bc079d5016e1 100644
--- a/drivers/gpu/drm/
This was introduced in
commit 6db4063c5b72b46e9793b0f141a7a3984ac6facf
Author: Antonino A. Daplas
Date: Mon Jun 26 00:27:12 2006 -0700
[PATCH] VT binding: Add sysfs control to the VT layer
with the justification
"In addition, if any of the consoles are in KD_GRAPHICS mode, binding an
On Sun, Apr 12, 2015 at 03:49:34PM +0530, sagar.a.kam...@intel.com wrote:
> For updated patch that is coming up per
> http://lists.freedesktop.org/archives/intel-gfx/2015-March/062315.html
> Reviewed-by: Sagar Kamble
Please don't reply to mails by linking to their archive link because that
compl
On Sat, Apr 11, 2015 at 08:23:06AM +0200, Nicolas Kalkhof wrote:
> Hello,
>
> it seems I got kicked off Cc. Anyway I can confirm that the supplied
> patch works an I can hotplug to my docking station and switch between
> DP/eDP without Oops. :)
Thanks for the test feedback, patch applied.
-Daniel
On Sun, Apr 12, 2015 at 11:28:14AM +0530, sagar.a.kam...@intel.com wrote:
> From: Sagar Kamble
>
> When RC6 along with Render power gating is enabled, GPU hang
> happens due to lack of synchronization between GTI and Render
> power gating.
>
> v2: Updated commit message and WA name (Damien)
>
>
From: "A.Sunil Kamath"
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware
From: Suketu Shah
Add triggers as per expectations mentioned in gen9_enable_dc5
and gen9_disable_dc5 patch.
Also call POSTING_READ for every write to a register to ensure that
its written immediately.
v1: Remove POSTING_READ calls as they've already been added in previous patches.
v2: Rebase t
On Fri, 2015-04-10 at 16:10 +0200, Takashi Iwai wrote:
> At Fri, 10 Apr 2015 16:27:39 +0300,
> Mika Kahola wrote:
> >
> > On Thu, 2015-04-09 at 17:17 +0200, Takashi Iwai wrote:
> > > At Thu, 9 Apr 2015 15:51:27 +0200,
> > > Daniel Vetter wrote:
> > > >
> > > > On Thu, Apr 09, 2015 at 04:41:26PM +
On Thu, Apr 09, 2015 at 10:14:36PM +, Konduru, Chandra wrote:
>
>
> > -Original Message-
> > From: Roper, Matthew D
> > Sent: Thursday, April 09, 2015 2:52 PM
> > To: Konduru, Chandra
> > Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
> > Ander
> > Subjec
On su, 2015-04-12 at 16:02 +0530, sagar.a.kam...@intel.com wrote:
> These are review comments for
> 1)
> http://lists.freedesktop.org/archives/intel-gfx/2015-March/062167.html
> 2)
> http://lists.freedesktop.org/archives/intel-gfx/2015-March/062168.html
It'd be better to have inline
On Mon, Apr 13, 2015 at 09:36:02AM +0530, Jindal, Sonika wrote:
>
>
> On 4/10/2015 8:14 PM, Ville Syrjälä wrote:
> > On Fri, Apr 10, 2015 at 04:17:17PM +0200, Daniel Vetter wrote:
> >> On Fri, Apr 10, 2015 at 02:37:29PM +0530, Sonika Jindal wrote:
> >>> v2: Moving creation of property in a functi
On 4/13/2015 3:40 PM, Ville Syrjälä wrote:
On Mon, Apr 13, 2015 at 09:36:02AM +0530, Jindal, Sonika wrote:
On 4/10/2015 8:14 PM, Ville Syrjälä wrote:
On Fri, Apr 10, 2015 at 04:17:17PM +0200, Daniel Vetter wrote:
On Fri, Apr 10, 2015 at 02:37:29PM +0530, Sonika Jindal wrote:
v2: Moving cr
On Mon, 2015-04-13 at 13:09 +0300, Imre Deak wrote:
> On su, 2015-04-12 at 16:02 +0530, sagar.a.kam...@intel.com wrote:
> > These are review comments for
> > 1)
> > http://lists.freedesktop.org/archives/intel-gfx/2015-March/062167.html
> > 2)
> > http://lists.freedesktop.org/archives/int
On Mon, Apr 13, 2015 at 12:43:14PM +0300, Mika Kahola wrote:
> On Fri, 2015-04-10 at 16:10 +0200, Takashi Iwai wrote:
> > At Fri, 10 Apr 2015 16:27:39 +0300,
> > Mika Kahola wrote:
> > >
> > > On Thu, 2015-04-09 at 17:17 +0200, Takashi Iwai wrote:
> > > > At Thu, 9 Apr 2015 15:51:27 +0200,
> > > >
On Mon, Apr 13, 2015 at 03:53:22PM +0530, Jindal, Sonika wrote:
>
>
> On 4/13/2015 3:40 PM, Ville Syrjälä wrote:
> > On Mon, Apr 13, 2015 at 09:36:02AM +0530, Jindal, Sonika wrote:
> >>
> >>
> >> On 4/10/2015 8:14 PM, Ville Syrjälä wrote:
> >>> On Fri, Apr 10, 2015 at 04:17:17PM +0200, Daniel Vet
From: Tvrtko Ursulin
Purpose of this tracking is to know when to flush the cache between
the CPU and the non-coherent display engine. Prior to:
commit 121920faf2ccce9aa66a7e2588415c9647b66104
Author: Tvrtko Ursulin
Date: Mon Mar 23 11:10:37 2015 +
drm/i915/skl: Query disp
When synchronising to rendering, we only want to wait for it to complete
and avoid the cache-domain side-effects of SET_DOMAIN if possible. This
has the advantage of speeding up a few tests (and thereby making the
actual test more explicit in terms of kernel operations). Of course some
tests may be
On 04/02/2015 05:27 PM, Chris Wilson wrote:
On Thu, Apr 02, 2015 at 05:11:58PM +0100, Tvrtko Ursulin wrote:
+static struct drm_i915_gem_object *
+find_object_from_vma(struct drm_device *dev,
+struct drm_i915_gem_userptr *args)
+{
+ struct drm_i915_gem_object *obj = NUL
On Sat, 11 Apr 2015, shuang...@intel.com wrote:
> Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
> shuang...@intel.com)
> Task id: 6167
> -Summary-
> Platform Delta drm-intel-nightly
On ma, 2015-04-13 at 15:54 +0530, Animesh Manna wrote:
> From: "A.Sunil Kamath"
>
> Display Context Save and Restore support is needed for
> various SKL Display C states like DC5, DC6.
>
> This implementation is added based on first version of DMC CSR program
> that we received from h/w team.
>
On Fri, 10 Apr 2015, Ander Conselvan de Oliveira
wrote:
> Otherwise, once we start doing atomic updates, the values from a
> previous update might be used, leading to unnecessary changes.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 6 +-
>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6184
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Mon, Apr 13, 2015 at 03:53:22PM +0530, Jindal, Sonika wrote:
> >>I never really got the to understand the need of reversing 90 and 270 :)
> >>The last discussion was not concluded, AFAIR.
> >>Things look correct to me and work fine with the testcase also.
> >>Is there something completely differ
Hi,
On 04/07/2015 01:23 PM, Joonas Lahtinen wrote:
Add a straightforward test that allocates a BO that is bigger than
(by 1 page currently) the mappable aperture, tests mmap access to it
by CPU directly and through GTT in sequence.
Currently it is expected for the GTT access to gracefully fail
Hi,
On 04/07/2015 04:20 PM, Chris Wilson wrote:
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores disabled and so fre
On ma, 2015-04-13 at 15:56 +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Add triggers as per expectations mentioned in gen9_enable_dc5
> and gen9_disable_dc5 patch.
>
> Also call POSTING_READ for every write to a register to ensure that
> its written immediately.
>
> v1: Remove POSTING_RE
On 04/07/2015 05:28 PM, Chris Wilson wrote:
The obj->pin_mappable flag only exists for debug purposes and is a
hindrance that is mistreated with rotated GGTT views. For debug
purposes, it suffices to mark objects with pin_display as being of note.
Signed-off-by: Chris Wilson
---
drivers/gpu/
On Thu, 05 Mar 2015, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> When GPU is idle on VLV, Request freq to punit should be good enough to
> get the voltage back to VNN. Also, make sure gfx clock force applies
> before requesting the freq fot vlv.
>
> Bugzilla: https://bugs.freedesktop.org/
On Thu, 19 Mar 2015, Daniel Vetter wrote:
> On Thu, Mar 19, 2015 at 03:38:19PM +0200, David Weinehall wrote:
>> On Thu, Mar 19, 2015 at 06:17:00PM +0530, Deepak S wrote:
>> >
>> >
>> > On Thursday 19 March 2015 05:14 PM, David Weinehall wrote:
>> > >On Thu, Mar 19, 2015 at 04:09:44PM +0530, deep
On Thu, 26 Mar 2015, Tvrtko Ursulin wrote:
> On 03/26/2015 01:30 PM, Ville Syrjälä wrote:
>> On Thu, Mar 26, 2015 at 12:39:40PM +, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin
>>>
>>> intel_user_framebuffer_destroy() requires the struct_mutex for its
>>> object bookkeeping, so this means th
On Mon, Apr 13, 2015 at 02:55:12PM +0300, Jani Nikula wrote:
> On Thu, 05 Mar 2015, deepa...@linux.intel.com wrote:
> > From: Deepak S
> >
> > When GPU is idle on VLV, Request freq to punit should be good enough to
> > get the voltage back to VNN. Also, make sure gfx clock force applies
> > before
On 04/13/2015 04:33 PM, Imre Deak wrote:
On ma, 2015-04-13 at 15:54 +0530, Animesh Manna wrote:
From: "A.Sunil Kamath"
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
th
https://bugzilla.kernel.org/show_bug.cgi?id=94921
As mentioned in the above bug report, switching output color range
"Automatically" according to current mode does not make sense in computer use
case.
---
drivers/gpu/drm/i915/i915_drv.h| 5 ++---
drivers/gpu/drm/i915/intel_dp.c| 23 ++-
A bisect showed that commit 32b7eeec4d1e861230b09d437e95d76c86ff4a68
introduced the issue.
The issue starts as soon as X takes control of the screen, even if just
a plain X doing nothing, so based on the code touched by the commit I
thought it had to be related to the so called "hardware cursor".
All 17" models with i915 graphics had a resolution of 1920x1200,
necessitating dual channel LVDS. The 15" pre-retina models had
up to 1680x1050, hence used dual channel LVDS as well.
Reference for MacBookPro9,1 (also tested by myself):
http://ubuntuforums.org/showthread.php?t=2224567
Reference fo
On Mon, Apr 13, 2015 at 12:34:19PM +0100, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 04/07/2015 04:20 PM, Chris Wilson wrote:
> >This provides a nice boost to mesa in swap bound scenarios (as mesa
> >throttles itself to the previous frame and given the scenario that will
> >complete shortly). It will a
On Mon, Apr 13, 2015 at 12:35:53PM +0100, Tvrtko Ursulin wrote:
>
> On 04/07/2015 05:28 PM, Chris Wilson wrote:
> >The obj->pin_mappable flag only exists for debug purposes and is a
> >hindrance that is mistreated with rotated GGTT views. For debug
> >purposes, it suffices to mark objects with pin
On Mon, Apr 13, 2015 at 02:04:27PM +0300, Jani Nikula wrote:
> On Sat, 11 Apr 2015, shuang...@intel.com wrote:
> > Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
> > shuang...@intel.com)
> > Task id: 6167
> > -Summary---
On Sat, 2015-04-11 at 19:17 -0300, Ismael Luceno wrote:
> A bisect showed that commit 32b7eeec4d1e861230b09d437e95d76c86ff4a68
> introduced the issue.
>
> The issue starts as soon as X takes control of the screen, even if just
> a plain X doing nothing, so based on the code touched by the commit I
On ma, 2015-04-13 at 18:37 +0530, Animesh Manna wrote:
>
> On 04/13/2015 04:33 PM, Imre Deak wrote:
> > On ma, 2015-04-13 at 15:54 +0530, Animesh Manna wrote:
> >> From: "A.Sunil Kamath"
> >>
> >> Display Context Save and Restore support is needed for
> >> various SKL Display C states like DC5, D
On Mon, Apr 13, 2015 at 12:01:34PM +0100, Chris Wilson wrote:
> When synchronising to rendering, we only want to wait for it to complete
> and avoid the cache-domain side-effects of SET_DOMAIN if possible. This
> has the advantage of speeding up a few tests (and thereby making the
> actual test mor
On pe, 2015-04-10 at 20:41 +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Warn if the conditions to enter or exit DC5 are not satisfied such
> as support for runtime PM, state of power well, CSR loading etc.
>
> v2: Removed camelcase in functions and variables.
>
> v3: Do some minimal chec
On pe, 2015-04-10 at 20:41 +0530, Animesh Manna wrote:
> From: Suketu Shah
>
> Add triggers for DC6 as per details provided in skl_enable_dc6
> and skl_disable_dc6 implementations.
>
> Also Call POSTING_READ for every write to a register to ensure
> it is written to immediately
>
> v1: Remove P
On Thu, Apr 02, 2015 at 06:58:22PM +0300, Imre Deak wrote:
> On ke, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> > From: "A.Sunil Kamath"
> >
> > This patch just implements the basic enable and disable
> > functions of DC5 state which is needed for both SKL and BXT.
>
> Reviewed-by: Imre De
On Sun, Apr 12, 2015 at 03:52:12PM +0530, sagar.a.kam...@intel.com wrote:
> For patch at
> http://lists.freedesktop.org/archives/intel-gfx/2015-March/062169.html
> Reviewed-by: Sagar Kamble
Usually reviews are done as a reply to the patch, but maybe you didn't
receive the earlier mail?
-
On ma, 2015-04-13 at 14:21 +0100, Damien Lespiau wrote:
> On Sun, Apr 12, 2015 at 03:52:12PM +0530, sagar.a.kam...@intel.com wrote:
> > For patch at
> > http://lists.freedesktop.org/archives/intel-gfx/2015-March/062169.html
> > Reviewed-by: Sagar Kamble
>
> Usually reviews are done as a reply to
[dunno what the distribution was originally; adding intel-gfx]
On Sun, 12 Apr 2015, Lukas Wunner wrote:
> All 17" models with i915 graphics had a resolution of 1920x1200,
> necessitating dual channel LVDS. The 15" pre-retina models had
> up to 1680x1050, hence used dual channel LVDS as well.
I
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6185
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -4
On 04/13/2015 01:09 PM, Jani Nikula wrote:
On Thu, 26 Mar 2015, Tvrtko Ursulin wrote:
On 03/26/2015 01:30 PM, Ville Syrjälä wrote:
On Thu, Mar 26, 2015 at 12:39:40PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
intel_user_framebuffer_destroy() requires the struct_mutex for its
object
On Fri, 10 Apr 2015, Imre Deak wrote:
> From: Shashank Sharma
>
> In BXT, DDI hotplug control has been moved to CPU from PCH.
> This patch adds a new IRQ setup function for BXT which:
> 1. Checks which HPD ports are requested to be enabled by encoders.
> 2. Enables those ports in the hot plug con
On Fri, 10 Apr 2015, Imre Deak wrote:
> From: Shashank Sharma
>
> This patch adds a hot plug interrupt handler function for BXT.
> What this function typically does is:
> 1. Check if hot plug is enabled from hot plug control register.
> 2. Call hpd_irq_handler with appropriate trigger to detect a
On Fri, 10 Apr 2015, Imre Deak wrote:
> From: Shashank Sharma
>
> This patch adds conditional checks in gen8_irq functions
> to support BXT. Most of the checks just look for PCH split
> availability, and block the call to PCH interrupt functions if
> not available.
>
> v2: (jani)
> - drop redunda
On Fri, 10 Apr 2015, Imre Deak wrote:
> From: Shashank Sharma
>
> GMBUS interrupt has been moved to CPU side in BXT.
> What this patch does is:
> 1. Enable GMBUS IRQ in de_post_install function
> 2. Handle this interrupt as a port interrupt in display irq
>handler
>
> v2: Rebase on top of the
On ma, 2015-04-13 at 14:17 +0100, Damien Lespiau wrote:
> On Thu, Apr 02, 2015 at 06:58:22PM +0300, Imre Deak wrote:
> > On ke, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> > > From: "A.Sunil Kamath"
> > >
> > > This patch just implements the basic enable and disable
> > > functions of DC5 s
On Mon, Apr 13, 2015 at 02:37:41PM +0100, Tvrtko Ursulin wrote:
>
> On 04/13/2015 01:09 PM, Jani Nikula wrote:
> > On Thu, 26 Mar 2015, Tvrtko Ursulin wrote:
> >> On 03/26/2015 01:30 PM, Ville Syrjälä wrote:
> >>> On Thu, Mar 26, 2015 at 12:39:40PM +, Tvrtko Ursulin wrote:
> From: Tvrtko
On ma, 2015-04-13 at 16:51 +0300, Jani Nikula wrote:
> On Fri, 10 Apr 2015, Imre Deak wrote:
> > From: Shashank Sharma
> >
> > This patch adds conditional checks in gen8_irq functions
> > to support BXT. Most of the checks just look for PCH split
> > availability, and block the call to PCH interr
2015-04-10 13:12 GMT-03:00 Todd Previte :
> Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
> Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
> all HPD plug events. To reduce the amount of code, this EDID read is also
> used for Link CTS tests 4
On Wed, Apr 08, 2015 at 07:18:06PM +0800, Tom Yan wrote:
> https://bugzilla.kernel.org/show_bug.cgi?id=94921
>
> As mentioned in the above bug report, switching output color range
> "Automatically" according to current mode does not make sense in
> computer use case.
Current code seems correct to
On ma, 2015-04-13 at 12:32 +0100, Tvrtko Ursulin wrote:
> Hi,
>
> On 04/07/2015 01:23 PM, Joonas Lahtinen wrote:
> > Add a straightforward test that allocates a BO that is bigger than
> > (by 1 page currently) the mappable aperture, tests mmap access to it
> > by CPU directly and through GTT in se
Add a straightforward test that allocates a BO that is bigger than
(by 1 page currently) the mappable aperture, tests mmap access to it
by CPU directly and through GTT in sequence.
Currently it is expected for the GTT access to gracefully fail as
all objects are attempted to get pinned to GTT comp
On Mon, Apr 13, 2015 at 03:13:12PM +0100, Damien Lespiau wrote:
> On Wed, Apr 08, 2015 at 07:18:06PM +0800, Tom Yan wrote:
> > https://bugzilla.kernel.org/show_bug.cgi?id=94921
> >
> > As mentioned in the above bug report, switching output color range
> > "Automatically" according to current mode
From: Shashank Sharma
This patch adds conditional checks in gen8_irq functions
to support BXT. Most of the checks just look for PCH split
availability, and block the call to PCH interrupt functions if
not available.
v2: (jani)
- drop redundant TODO comment about PCH IRQ flags on BXT
- check HAS_
On 04/13/2015 03:22 PM, Joonas Lahtinen wrote:
On ma, 2015-04-13 at 12:32 +0100, Tvrtko Ursulin wrote:
Hi,
On 04/07/2015 01:23 PM, Joonas Lahtinen wrote:
Add a straightforward test that allocates a BO that is bigger than
(by 1 page currently) the mappable aperture, tests mmap access to it
by
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID read is also
used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual
suppo
Displayport compliance test 4.2.2.6 requires that a source device be capable of
detecting a corrupt EDID. The test specification states that the sink device
sets up the EDID with an invalid checksum. To do this, the sink sets up an
invalid EDID header, expecting the source device to generate the ch
On 4/13/15 7:10 AM, Paulo Zanoni wrote:
2015-04-10 13:12 GMT-03:00 Todd Previte :
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID r
From: Tvrtko Ursulin
intel_user_framebuffer_destroy() requires the struct_mutex for its
object bookkeeping, so this means that all calls to
drm_framebuffer_unreference must be held without that lock.
This is a simplified version of the identically named patch by Chris Wilson.
Regression fro
On Mon, Apr 13, 2015 at 03:56:23PM +0530, Animesh Manna wrote:
> @@ -71,6 +90,8 @@ void intel_csr_load_program(struct drm_device *dev)
> I915_WRITE(dev_priv->csr.mmioaddr[i],
> dev_priv->csr.mmiodata[i]);
> }
> +
> + intel_csr_load_status_set(dev_priv,
On 04/11/2015 01:41 AM, Chris Wilson wrote:
> Bug reports are still coming in for late 4.0-rcX that indicate that
> execlists causes GPU hangs following resume.
>
> Fixes regression from
> commit d7f621e50704306c348ccb192f17047f1499f9bc
> Author: Oscar Mateo
> Date: Thu Jul 24 17:04:49 2014 +01
On Mon, Apr 13, 2015 at 03:54:02PM +0530, Animesh Manna wrote:
> diff --git a/drivers/gpu/drm/i915/intel_csr.h
> b/drivers/gpu/drm/i915/intel_csr.h
> new file mode 100644
> index 000..c2a5a53
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_csr.h
> +
[...]
> +#define I915_CSR_SKL "i915/dmc
Update igt_paint_image so that it can read images from the package data
directory.
Signed-off-by: Thomas Wood
---
lib/Android.mk | 2 +-
lib/Makefile.am | 3 ++-
lib/igt_fb.c| 23 +--
tests/testdisplay.c | 35 ++-
4 files cha
Signed-off-by: Thomas Wood
---
lib/igt_core.c | 5 +
tests/testdisplay.c | 5 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index daef8c6..700604f 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -1751,5 +1751,10 @@ FILE *__igt_fo
On Mon, 2015-04-13 at 17:34 +0100, Damien Lespiau wrote:
> On Mon, Apr 13, 2015 at 03:54:02PM +0530, Animesh Manna wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_csr.h
> > b/drivers/gpu/drm/i915/intel_csr.h
> > new file mode 100644
> > index 000..c2a5a53
> > --- /dev/null
> > +++ b/drivers
On Mon, Apr 13, 2015 at 07:52:54PM +0300, Imre Deak wrote:
> On Mon, 2015-04-13 at 17:34 +0100, Damien Lespiau wrote:
> > On Mon, Apr 13, 2015 at 03:54:02PM +0530, Animesh Manna wrote:
> > > diff --git a/drivers/gpu/drm/i915/intel_csr.h
> > > b/drivers/gpu/drm/i915/intel_csr.h
> > > new file mode
On Mon, 2015-04-13 at 18:02 +0100, Damien Lespiau wrote:
> On Mon, Apr 13, 2015 at 07:52:54PM +0300, Imre Deak wrote:
> > On Mon, 2015-04-13 at 17:34 +0100, Damien Lespiau wrote:
> > > On Mon, Apr 13, 2015 at 03:54:02PM +0530, Animesh Manna wrote:
> > > > diff --git a/drivers/gpu/drm/i915/intel_csr
On Mon, Apr 13, 2015 at 08:15:29PM +0300, Imre Deak wrote:
> Ok, I haven't seen that. One question is if we need to support multiple
> interface versions or just the latest one. I would say only the latest
> one (for each platform) and so I915_CSR_SKL should be this latest
> firmware image filename
2015-04-10 13:12 GMT-03:00 Todd Previte :
> Add the skeleton framework for supporting automation for Displayport
> compliance
> testing. This patch adds the necessary framework for the source device to
> appropriately respond to test automation requests from a sink device.
>
> V2:
> - Addressed pr
On Mon, Apr 13, 2015 at 02:33:50PM +0300, Imre Deak wrote:
> > @@ -424,6 +434,25 @@ static void skl_set_power_well(struct drm_i915_private
> > *dev_priv,
> > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> > POSTING_READ(HSW_PWR_WELL_DRIVER);
> >
On Mon, Apr 13, 2015 at 03:56:23PM +0530, Animesh Manna wrote:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 90e47a9..8d6deaa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -667,6 +667,12 @@ struct intel_uncore
Our legacy SetPlane updates perform integer overflow checking on a
plane's destination rectangle in drm_mode_setplane(), and atomic updates
handled as part of a drm_atomic_state transaction do the same checking
in drm_atomic_plane_check(). However legacy cursor updates that get
routed through univ
On Tue, Apr 07, 2015 at 03:28:46PM -0700, Chandra Konduru wrote:
> This patch enables skylake primary plane scaling using shared
> scalers atomic desgin.
>
> v2:
> -use single copy of scaler limits (Matt)
>
> v3:
> -move detach_scalers to crtc commit path (Matt)
> -use values in plane_state->src
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Monday, April 13, 2015 11:13 AM
> To: Konduru, Chandra
> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander; Vetter,
> Daniel
> Subject: Re: [Intel-gfx] [PATCH 13/
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6186
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -4
On 2 April 2015 at 12:02, Jani Nikula wrote:
> On Tue, 31 Mar 2015, Steven Honeyman wrote:
>> On 31 March 2015 at 17:50, Matt Roper wrote:
>>> On Tue, Mar 31, 2015 at 08:54:19AM +0200, Daniel Vetter wrote:
Adding mailing lists (and hooray for me mixing up addresses, so now
there's a di
Hi Daniel, hi Ville,
some success at last. I couldn't stop myself playing with the NatSemi
2501 DVO in my Fujitsu S6010 and I believe I finally got a hang on this
chip. I believe I understand now most of the undocumented registers.
There are also a couple of additional features that are, appa
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6187
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -8
If the sink does not provide a maximum link rate, then check the
connector configuration before defaulting to the lowest allowed
link rate.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_dp.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/g
Allow the init-time configuration to specify the bits per color value
that gets used if bits per color is not present in EDID data (or if EDID
is not present).
v2: Use connector->base.name for connector name (Jani)
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_display.c | 14
This adds an init-time configuration framework that parses configuration
data from an ACPI property table. The table is assumed to have well
defined sub-device property tables that correspond to the various
driver components. Initially the following sub-device tables are
defined:
CRTC (CRTC)
T
Allow the configuration file to overide the various panel power
sequence delay values.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_dp.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b05ff6d
This is an example of what an ACPI property table looks like.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915-properties.asl | 167 +++
1 file changed, 167 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915-properties.asl
diff --git a/drivers/gpu/drm
Set the initial value of the force audio and broadcast rgb properties
using property values found in the init-time configuration.
v2: Use drm connector name (Jani)
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_modes.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --
To allow us to verify the current backlight max and level values.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a9b96fd..2bac3bc 100644
--
Use the init-time configuration setting for scaling_mode to set the
initial value of the scaling_mode connector property.
v2: Use drm connector name (Jani)
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_dp.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/dr
So that we verify which values are currently in use.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2394924..a9b96
Allow the configuration file to overide the backlight max and level
settings.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_panel.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index d8686ce..54c8c
Background:
This capability is targeted at deeply embedded appliance like devices
that make use of Intel integrated graphics. There are a few use cases
that are not currently supported by the i915 driver. For example,
they may not be running user space code that is capable of querying and
settin
2015-04-10 13:12 GMT-03:00 Todd Previte :
> The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1
> specifies that repeated AUX transactions after a failure (no response /
> invalid response) must have a minimum delay of 400us before the resend can
> occur. Tests 4.2.1.1 and 4.2.1
2015-04-13 11:53 GMT-03:00 Todd Previte :
> Displayport compliance test 4.2.2.6 requires that a source device be capable
> of
> detecting a corrupt EDID. The test specification states that the sink device
> sets up the EDID with an invalid checksum. To do this, the sink sets up an
> invalid EDID h
1 - 100 of 114 matches
Mail list logo
