Re: [Intel-gfx] [PATCH] drm/i915: Fix big cursors on snb

Hi Art, Indeed my patch looks fishy and it's because this isn't the code I've tested the entire night :( The one that works simply disables lp1+ wm levels. Which is a bit an oversized hammer really. Do you have any ideas for w/a or smaller tricks I could try? I did try just blantantly multiplying

Re: [Intel-gfx] [PATCH 2/3] drm/i915/skl: Restore pipe interrupt registers after power well enabling

On Mon, Mar 02, 2015 at 03:37:47PM -0300, Paulo Zanoni wrote: > 2015-02-13 17:37 GMT-02:00 Damien Lespiau : > > The pipe interrupt registers are in the actual pipe power well, so we > > need to restore them when re-enable the corresponding power well. > > > > I've also copied what we do on HSW/BDW

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.

On Mon, Mar 02, 2015 at 06:35:26PM +, Vivi, Rodrigo wrote: > On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote: > > On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote: > > > There are some cases like suspend/resume or dpms off/on sequences > > > that can flush frontbuffer bits. I

Re: [Intel-gfx] [PATCH] drm/i915: Export total subslice and EU counts

On Mon, Mar 02, 2015 at 03:37:32PM -0800, jeff.mc...@intel.com wrote: > From: Jeff McGee > > Setup new I915_GETPARAM ioctl entries for subslice total and > EU total. Userspace drivers need these values when constructing > GPGPU commands. This kernel query method is intended to replace > the PCI I

Re: [Intel-gfx] [PATCH] drm/i915: Export total subslice and EU counts

On Tue, Mar 03, 2015 at 09:54:39AM +0100, Daniel Vetter wrote: > On Mon, Mar 02, 2015 at 03:37:32PM -0800, jeff.mc...@intel.com wrote: > > From: Jeff McGee > > > > Setup new I915_GETPARAM ioctl entries for subslice total and > > EU total. Userspace drivers need these values when constructing > >

[Intel-gfx] [PATCH] demos/intel_sprite_on : Sprite Stress Testing

From: meghanelogal Adding the Sprite Stress Test Feature Signed-off-by: meghanelogal --- demos/intel_sprite_on.c | 653 +-- 1 file changed, 347 insertions(+), 306 deletions(-) diff --git a/demos/intel_sprite_on.c b/demos/intel_sprite_on.c index 23f

Re: [Intel-gfx] [PATCH 3/5] drm/i915/skl: Support secondary (rotated) frame buffer mapping

On 03/02/2015 06:21 PM, Daniel Vetter wrote: On Mon, Mar 02, 2015 at 02:43:50PM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin 90/270 rotated scanout needs a rotated GTT view of the framebuffer. This is put in a separate VMA with a dedicated ggtt_view and wired suchs that it is created wh

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Enable PSR by default.

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5865 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -5 278/278

[Intel-gfx] [PATCH i-g-t v4] tests/gem_render_linear_blits: split into two subtests

From: Tim Gore The gem_render_linear_blits test tends to get oom killed on low memory (< 4GB) Android systems. This is because the test tries to allocate (sysinfo.totalram * 9 / 10) in buffer objects and the remaining 10% of memory is not always enough for the Android system. After a discussion w

[Intel-gfx] [PATCH i-g-t v2] tests/gem_render_tiled_blits: split into subtests

From: Tim Gore The gem_render_tiled_blits test tends to get oom killed on low memory (< 4GB) Android systems. This is because the test tries to allocate (sysinfo.totalram * 9 / 10) in buffer objects and the remaining 10% of memory is not always enough for the Android system. A similar issue with

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use plane->state->fb in watermark code (v2)

Hi 2015-02-27 15:12 GMT-03:00 Matt Roper : > plane->fb is a legacy pointer that not always be up-to-date (or updated > early enough). Make sure the watermark code uses plane->state->fb so > that we're always doing our calculations based on the correct > framebuffers. QA reported a regression cau

Re: [Intel-gfx] [PATCH 01/12] drm/i915/bdw: Make pdp allocation more dynamic

On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry wrote: > From: Ben Widawsky > > This transitional patch doesn't do much for the existing code. However, > it should make upcoming patches to use the full 48b address space a bit > easier to swallow. The patch also introduces the PML4, ie. the new t

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Make for_each_sprite() take dev_priv as argument

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5866 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -9 278/278

Re: [Intel-gfx] [PATCH 02/12] drm/i915/bdw: Abstract PDP usage

On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry wrote: > From: Ben Widawsky > > Up until now, ppgtt->pdp has always been the root of our page tables. > Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs. > > In preparation for 4 level page tables, we need to stop use ppgtt->pdp > directly

Re: [Intel-gfx] [PATCH 04/12] drm/i915/bdw: Add ppgtt info for dynamic pages

On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry wrote: > From: Ben Widawsky > > Note that there is no gen8 ppgtt debug_dump function yet. > > Signed-off-by: Ben Widawsky > Signed-off-by: Michel Thierry > --- > drivers/gpu/drm/i915/i915_debugfs.c | 19 ++- > drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH] drm/i915: Add debugfs entry for DRRS

On Monday 23 February 2015 11:49 PM, Rodrigo Vivi wrote: On Mon, Feb 23, 2015 at 4:05 AM, Ramalingam C wrote: From: Vandana Kannan Adding a debugfs entry to determine if DRRS is supported or not V2: [By Ram]: Following details about the active crtc will be filled in seq-file of the

[Intel-gfx] [PATCH] drm/i915: Fix trivial typos in comments and warning message

Change 'mutliple' to 'multiple' Change 'mutlipler' to 'multiplier' Change 'Haswel' to 'Haswell' Signed-off-by: Yannick Guerrini --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_reg.h| 2 +- drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 3 files cha

[Intel-gfx] Intel Driver graphics - Failure

Hello, I installed the Ubuntu 14.04 based derivate Mint L. 17.1. I tried your installer on the web page. The installer denied the installing stating the false Os is installed. Could do me favour and add The Mint derivate to the installer. Would be great. In the moment my resolution is not correct

Re: [Intel-gfx] [PATCH 05/12] drm/i915/bdw: implement alloc/free for 4lvl

On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry wrote: > From: Ben Widawsky > > The code for 4lvl works just as one would expect, and nicely it is able > to call into the existing 3lvl page table code to handle all of the > lower levels. > > PML4 has no special attributes, and there will always

[Intel-gfx] [PATCH] drm/i915: Changes for calculating dsi clk for CHT

Depending on the correct refclk, n ,p for CHT, calculate the dsi clk during readout DSI HW state. Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/dri

Re: [Intel-gfx] [PATCH 06/12] drm/i915/bdw: Add 4 level switching infrastructure

On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry wrote: > From: Ben Widawsky > > Map is easy, it's the same register as the PDP descriptor 0, but it only > has one entry. > > v2: PML4 update in legacy context switch is left for historic reasons, > the preferred mode of operation is with lrc conte

Re: [Intel-gfx] i915 driver doesn't find all Modelines that nouveau driver finds

On Mon, Mar 02, 2015 at 03:16:16PM -0500, Brian J. Murrell wrote: > On Mon, 2015-03-02 at 20:44 +0200, Ville Syrjälä wrote: > > On Mon, Mar 02, 2015 at 07:07:47PM +0100, Daniel Vetter wrote: > > > On Mon, Mar 02, 2015 at 11:33:39AM -0500, Brian J. Murrell wrote: > > > > > > > > [ 50.508381] [drm

[Intel-gfx] [PATCH 1/3] drm/i915: DP link training optimization

This is a first of series patches that optimize DP link training. The first patch is for eDP only where we reuse the previously trained link training values from cache i.e. voltage swing and pre-emphasis levels. In case we are not able to train the link by reusing the known values, the link traini

Re: [Intel-gfx] [PATCH 07/12] drm/i915/bdw: Support 64 bit PPGTT in lrc mode

On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry wrote: > In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains > the base address to PML4, while the other PDP registers are ignored. > > Also, the addressing mode must be specified in every context descriptor. > > Signed-off-by: Mic

Re: [Intel-gfx] i915 driver doesn't find all Modelines that nouveau driver finds

On Tue, 2015-03-03 at 15:03 +0200, Ville Syrjälä wrote: > > Oh that's an a CRT monitor you have there. Been a while since I've > come across one of those :) Heh. Yeah. I have been in the market to replace it but no good enough deals yet. :-) > 65Hz on a CRT sounds like a good way to > get a h

[Intel-gfx] [PATCH 03/23] drm/i915: Improve staged config logging

When logging that full mode switch is necessary, log which connector, encoder or crtc has caused it, so it is easier to figure out what is goind on by just looking at the log. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 11 --- 1 file changed, 8

[Intel-gfx] [PATCH 12/23] drm/i915: Don't use encoder->new_crtc in intel_modeset_pipe_config()

Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/driver

[Intel-gfx] [PATCH 02/23] drm/i915: Add a for_each_intel_connector macro

We have similar macros for crtcs and encoders, and the pattern happens often enough to justify the macro. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/i915_debugfs.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 6 drivers/gpu/drm/i915/intel_display.c | 55 ++

[Intel-gfx] [PATCH 13/23] drm/i915: Don't use encoder->new_crtc in compute_baseline_pipe_bpp()

Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/dr

[Intel-gfx] [PATCH 05/23] drm/i915: Allocate a drm_atomic_state for the legacy modeset code

For the atomic conversion, the mode set paths need to be changed to rely on an atomic state instead of using the staged config. By using an atomic state for the legacy code, we will be able to convert the code base in small chunks. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/

[Intel-gfx] [PATCH 08/23] drm/i915: Allocate a crtc_state also when the crtc is being disabled

For consistency, allocate a new crtc_state for a crtc that is being disabled. Previously only the enabled value of the current state would change. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 36 +--- 1 file changed, 25 in

[Intel-gfx] [PATCH 09/23] drm/i915: Update dummy connector atomic state with current config

Keep that state updated so that we can write code that depends on it on the follow up patches. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 41 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/drivers/gp

[Intel-gfx] [PATCH 20/23] drm/i915: Use atomic state in pipe_has_enabled_pch()

This function is called indirectly by intel_crtc_compute_config(), which needs to be converted to work only with an atomic state. --- I'm not sure what are the implications of ignoring intel_crtc->active in pipe_has_enabled_pch(). If we allow a config because the third pipe is enabled but not act

[Intel-gfx] [PATCH 18/23] drm/i915: Don't use encoder->new_crtc in intel_lvds_compute_config()

Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_lvds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c

[Intel-gfx] [PATCH 04/23] drm/i915: Add intel_atomic_get_crtc_state() helper function

The pattern of getting the crtc state with drm_atomic_get_crtc_state() and then converting it to intel_crtc_state will repeat quite often in the following patches, so add a helper function to save some typing. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_drv.h | 10

[Intel-gfx] [PATCH 01/23] drm/i915: Set crtc backpointer when duplicating crtc state

In the path were there is no state to duplicate, the allocated crtc state wouldn't have the crtc backpointer initialized. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_atomic.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/g

[Intel-gfx] [PATCH 00/23] Remove depencies on staged config for atomic transition

This patch series starts to remove dependencies from the modeset code to enable the transition to atomic. That is achieved by using an atomic state struct for the legacy modeset, and changing related functiond to depend on it. I wasn't able to test all of the changes, so I'm very interested on PRT

[Intel-gfx] [PATCH 06/23] drm/i915: Add an optional atomic state argument to intel_set_mode()

In the set config modeset path, the atomic state is updated when changing the staged config in intel_modeset_stage_output_config(). The load detect code also causes a modeset, but it changes the staged config before calling intel_set_mode(). A follow up patch will change that function to also updat

[Intel-gfx] [PATCH 11/23] drm/i915: Copy the staged connector config to the legacy atomic state

With this in place, we can start converting pieces of the modeset code to look at the connector atomic state instead of the staged config. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 23 --- 1 file changed, 20 insertions(+), 3 deleti

[Intel-gfx] [PATCH 07/23] drm/i915: Use an atomic state for the load detect modeset

Create an atomic state and initialize it for the load detect pipe modesets, so it doesn't break once the rest of the mode set code starts using atomic states instead of the staged config. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/dr

[Intel-gfx] [PATCH 17/23] drm/i915: Don't use staged config in intel_dp_mst_compute_config()

Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dp_mst.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gp

[Intel-gfx] [PATCH 10/23] drm/i915: Implement connector state duplication

So that we can add connector states to the drm_atomic_state used in the legacy modeset. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_crt.c| 1 + drivers/gpu/drm/i915/intel_dp.c | 1 + drivers/gpu/drm/i915/intel_dp_mst.c | 1 + drivers/gpu/drm/i915/intel_dsi.

[Intel-gfx] [PATCH 16/23] drm/i915: Use atomic state in intel_ddi_crtc_get_new_encoder()

Instead of using connector->new_encoder, get the same information from the pipe_config, thus making the function ready for the atomic conversion. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_ddi.c | 24 +++- 1 file changed, 15 insertions(+), 9 de

[Intel-gfx] [PATCH 15/23] drm/i915: Don't depend on encoder->new_crtc in intel_hdmi_compute_config

Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_hdmi.c | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gp

[Intel-gfx] [PATCH 22/23] drm/i915: Don't look at staged config crtc when changing DRRS state

The function intel_dp_set_drrs_state() would decide which pipe to downclock based on the staged config for the given connector. However, the result of that function is immediate, and it uses input values from crtc->config, so it should be looking at the current crtc instead. Signed-off-by: Ander C

Re: [Intel-gfx] i915 when using vaapi, screen only refreshes on mouse movement

On Mon, 2015-03-02 at 14:27 +, Chris Wilson wrote: > > Mixing ZaphodHeads and DRI, Oh wait! You said "mixing" not "missing". But yeah, I'm an old-timer trying to maintain his 20+ year old preference for truly separate screens -- like from way back when even Xinerama didn't even exist. :-)

[Intel-gfx] [PATCH 19/23] drm/i915: Pass an atomic state to modeset_global_resources() functions

Follow up patches will convert some functions called from there to use the atomic state, instead of directly accessing the new or current config. This patch just changes the parameters, but shouldn't have any functional changes. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 21/23] drm/i915: Convert intel_pipe_will_have_type() to using atomic state

Pass a crtc_state to it and find whether the pipe has an encoder of a given type by looking at the drm_atomic_state the crtc_state points to. Note that is possible to reach i9xx_get_refclk() without a proper atomic state, since in the function vlv_force_pll_on() a minimally initialized crtc_state

[Intel-gfx] [PATCH 14/23] drm/i915: Don't depend on encoder->new_crtc in intel_dp_compute_config()

Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index

[Intel-gfx] [PATCH 23/23] drm/i915: Remove usage of encoder->new_crtc from clock computations

Some of the crtc_compute_clock() still depended on encoder->new_crtc since they didn't use intel_pipe_will_have_type() and used an open coded version of that function instead. This patch replaces those with the appropriate code that checks the atomic state intead. Signed-off-by: Ander Conselvan de

Re: [Intel-gfx] i915 driver doesn't find all Modelines that nouveau driver finds

On Tue, Mar 03, 2015 at 08:16:56AM -0500, Brian J. Murrell wrote: > On Tue, 2015-03-03 at 15:03 +0200, Ville Syrjälä wrote: > > > > Oh that's an a CRT monitor you have there. Been a while since I've > > come across one of those :) > > Heh. Yeah. I have been in the market to replace it but no go

Re: [Intel-gfx] eDP display control registers in Linux kernel

On Sat, 28 Feb 2015, Michael Leuchtenburg wrote: > No changes, even while the brightness is in the process of changing. Is it > possible there's some other bit used on this hardware? The Broadwell chips > are pretty new. I haven't had a chance to look for specs yet. The DPCD info is specific to y

Re: [Intel-gfx] [PATCH 2/2] acpi/video: Propagate the error code for acpi_video_register

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5867 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -4 278/278

Re: [Intel-gfx] i915 when using vaapi, screen only refreshes on mouse movement

On Tue, Mar 03, 2015 at 08:23:04AM -0500, Brian J. Murrell wrote: > On Mon, 2015-03-02 at 14:27 +, Chris Wilson wrote: > > > > Mixing ZaphodHeads and DRI, > > Oh wait! You said "mixing" not "missing". But yeah, I'm an old-timer > trying to maintain his 20+ year old preference for truly sep

Re: [Intel-gfx] [PATCH 00/12] PPGTT with 48b addressing

On Fri, Feb 20, 2015 at 05:45:54PM +, Michel Thierry wrote: > These patches rely on "PPGTT dynamic page allocations", currently under > review, > to provide GEN8 dynamic page table support with 64b addresses. As the review > progresses, these patches may be combined. > > In order expand the G

[Intel-gfx] [PATCH i-g-t 02/13] lib: Extract igt_buf_write_to_png() from gem_render_copy

From: Damien Lespiau Now that the Android build has cairo, we can put cairo-dependant code back into lib/ v2: Document image format. (Daniel Vetter) Signed-off-by: Damien Lespiau --- lib/intel_batchbuffer.c | 26 ++ lib/intel_batchbuffer.h | 2 ++ tests/gem_render_cop

[Intel-gfx] [PATCH i-g-t v3 00/13] Testing the Y tiled display

From: Tvrtko Ursulin Starting with Skylake the display engine can scan out Y tiled objects. (Both legacy Y tiled, and the new Yf format.) This series takes the original work by Damien Lespiau and converts it to use the new frame buffer modifiers instead of object set/get tiling. Some patches nee

[Intel-gfx] [PATCH i-g-t 01/13] tests/kms_addfb: Add support for fb modifiers

From: Tvrtko Ursulin Just a few basic tests to make sure fb modifiers can be used and behave sanely when mixed with the old set_tiling API. v2: * Review feedback from Daniel Vetter: 1. Move cap detection into the subtest so skipping works. 2. Added some gtkdoc comments. 3. T

[Intel-gfx] [PATCH i-g-t 10/13] lib/igt_fb: Use new ADDFB2 extension for new tiling modes

From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- lib/igt_fb.c | 36 +++- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 853b2f9..c54907e 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -404,16 +404,10 @@ ig

[Intel-gfx] [PATCH i-g-t 06/13] lib: Split two helpers to build fast copy's dword0 and dword1

From: Damien Lespiau Again, these helpers will be useful for a raw version of the gen9 fast copy. Signed-off-by: Damien Lespiau --- lib/intel_batchbuffer.c | 96 + 1 file changed, 57 insertions(+), 39 deletions(-) diff --git a/lib/intel_batchbuf

[Intel-gfx] [PATCH i-g-t 12/13] testdisplay/skl: Add command line options for Yb/Yf tiled fbs

From: Damien Lespiau Signed-off-by: Damien Lespiau --- tests/testdisplay.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/tests/testdisplay.c b/tests/testdisplay.c index 64ce4d7..dab9e12 100644 --- a/tests/testdisplay.c +++ b/tests/testdisplay.c @@ -51,6 +

[Intel-gfx] [PATCH i-g-t 05/13] lib: Don't give a struct igt_buf * to fast_copy_pitch()

From: Damien Lespiau So we can use this function in a "raw" (ie without igt_buf) version. Signed-off-by: Damien Lespiau --- lib/intel_batchbuffer.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index 9b8ae0d..

[Intel-gfx] [PATCH i-g-t 13/13] tests/kms_flip_tiling: Exercise Y tiling modes on Gen9+

From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- tests/kms_flip_tiling.c | 28 +--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/tests/kms_flip_tiling.c b/tests/kms_flip_tiling.c index 9adf143..9ca12f7 100644 --- a/tests/kms_flip_tiling.c +++ b/te

[Intel-gfx] [PATCH i-g-t 09/13] lib: Add support for new extension to the ADDFB2 ioctl.

From: Tvrtko Ursulin New functionality accessesed via the __kms_addfb wrapper. Signed-off-by: Tvrtko Ursulin --- lib/ioctl_wrappers.c | 26 ++ lib/ioctl_wrappers.h | 9 + 2 files changed, 35 insertions(+) diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.

[Intel-gfx] [PATCH i-g-t 11/13] lib: Allow the creation of Ys/Yf tiled FBs

From: Damien Lespiau There's no fencing for those tiling layouts, so we create a linear bo for cairo to play with, and when cairo is finished with it, we do a fast copy blit to the fb BO with its final tiling. v2: Move to correct domain after CPU is done with the object (-EINVAL). (Tvrtko Ursul

[Intel-gfx] [PATCH i-g-t 08/13] tiling: Convert framebuffer helpers to use fb modifiers

From: Tvrtko Ursulin This converts the IGT API only, underneath legacy set_tiling is still used. v2: One got away in kms_flip. Signed-off-by: Tvrtko Ursulin --- lib/igt_fb.c| 20 ++-- lib/igt_fb.h| 10 +- lib/igt_kms.h | 1

[Intel-gfx] [PATCH i-g-t 03/13] tests/kms_addfb: Y tiled testcases

From: Tvrtko Ursulin v2: Moved all init into fixtures. Signed-off-by: Tvrtko Ursulin --- lib/ioctl_wrappers.h | 2 ++ tests/kms_addfb.c| 70 +++- 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/lib/ioctl_wrappers.h b/lib/ioctl

[Intel-gfx] [PATCH i-g-t 04/13] lib/skl: Add gen9 specific igt_blitter_fast_copy()

From: Damien Lespiau v2: Adjust for BB handling changes. (Tvrtko Ursulin) Correct XY_FAST_COPY_DST_TILING_Yf. (Tvrtko Ursulin) v3: New tiling modes are not defined in the kernel any more. (Tvrtko Ursulin) Signed-off-by: Damien Lespiau Signed-off-by: Tvrtko Ursulin --- lib/intel_batchbuff

[Intel-gfx] [PATCH i-g-t 07/13] lib: Provide a raw version of the gen9 fast copy blits

From: Damien Lespiau So we can use it with bare kernel types, without going through libdrm bos. v2: Don't forget the object handle. (Tvrtko) Correct surface pitch calculation. (Tvrtko) Signed-off-by: Damien Lespiau Signed-off-by: Tvrtko Ursulin --- lib/intel_batchbuffer.c | 134 +

Re: [Intel-gfx] [PATCH v3] intel: New libdrm interface to create unbound wc user mappings for objects

On Tue, Dec 09, 2014 at 04:53:01PM +, Damien Lespiau wrote: > Right that leaves the last point in my answer to v3. With that addressed > this is: > > Reviewed-by: Damien Lespiau Hum it seems that we've upstreamed the kernel part without the libdrm API. Is it time to fix this? Akash, Chris, a

[Intel-gfx] [PATCH 7/8] drm/i915/skl: Query display address through a wrapper

From: Tvrtko Ursulin Need to do this in order to support 90/270 rotated display. v2: Pass in drm_plane instead of plane index to intel_obj_display_address. v3: * Renamed intel_obj_display_address to intel_plane_obj_offset. (Chris Wilson) * Simplified rotation check to bitwise AND.

[Intel-gfx] [PATCH 6/8] drm/i915/skl: Support secondary (rotated) frame buffer mapping

From: Tvrtko Ursulin 90/270 rotated scanout needs a rotated GTT view of the framebuffer. This is put in a separate VMA with a dedicated ggtt view and wired such that it is created when a framebuffer is pinned to a 90/270 rotated plane. Rotation is only possible with Yb/Yf buffers and error is p

[Intel-gfx] [PATCH 1/8] drm: Pass in new and old plane state to prepare_fb and cleanup_fb

From: Tvrtko Ursulin Use cases like rotation require these hooks to have some context so they know how to prepare and cleanup the frame buffer correctly. For i915 specifically, object backing pages need to be mapped differently for different rotation modes and the driver needs to know which mapp

[Intel-gfx] [PATCH 4/8] drm/i915: Pass in plane state when (un)pinning frame buffers

From: Tvrtko Ursulin Plane state carries the rotation information which is needed for determining the appropriate GGTT view type. This just adds the parameter with the actual usage coming in future patches. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_display.c | 18 ++

[Intel-gfx] [PATCH 8/8] drm/i915/skl: Take 90/270 rotation into account in watermark calculations

From: Tvrtko Ursulin v2: Pass in rotation info to sprite plane updates as well. v3: Use helper to determine 90/270 rotation. (Michel Thierry) v4: Rebased for fb modifiers and atomic changes. For: VIZ-4546 Signed-off-by: Tvrtko Ursulin Reviewed-by: Michel Thierry (v3) --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 2/8] drm/i915/skl: Extract tile height code into a helper function

From: Tvrtko Ursulin It will be used in a later patch. v2: Rebased for fb modifiers. v3: Fixed v2 rebase. Signed-off-by: Tvrtko Ursulin Reviewed-by: Michel Thierry (v1) --- drivers/gpu/drm/i915/intel_display.c | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff

[Intel-gfx] [PATCH v2 0/8] Skylake 90/270 display rotation

From: Tvrtko Ursulin Display engine on Skylake can scan out specially prepared frame buffers rotated by 90 or 270 degrees. This adds partial support for that - display programming patches are missing from this initial posting because for now the only purpose is to see if people now like the appr

[Intel-gfx] [PATCH 5/8] drm/i915: Helper function to determine GGTT view from plane state

From: Tvrtko Ursulin For now only default implementation defaulting to normal view. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_display.c | 26 +++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/dri

[Intel-gfx] [PATCH 3/8] drm/i915: Use GGTT view when (un)pinning objects to planes

From: Tvrtko Ursulin To support frame buffer rotation we need to be able to pass on the information on what kind of GGTT view is required for display. This patch just adds the parameter and makes all the callers default to the normal view. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i91

Re: [Intel-gfx] [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV

On 2/16/2015 5:02 PM, Ville Syrjälä wrote: On Mon, Feb 16, 2015 at 03:08:02PM +0530, Vijay Purushothaman wrote: This patch implements latest PHY changes in Gain, prop and int co-efficients based on the vco freq. Signed-off-by: Vijay Purushothaman --- drivers/gpu/drm/i915/i915_reg.h |

Re: [Intel-gfx] [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz

On 2/23/2015 9:43 PM, Daniel Vetter wrote: On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote: On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote: As per the recommendation from PHY team, limit the max vco supported in CHV to 6.48 GHz Signed-off-by: Vijay Purushoth

[Intel-gfx] [PATCH 1/3] drm/i915: Disable M2 frac division for integer case

v2 : Handle M2 frac division for both M2 frac and int cases v3 : Addressed Ville's review comments. Cleared the old bits for RMW Signed-off-by: Vijay Purushothaman --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_display.c | 24 ++-- 2 files ch

[Intel-gfx] [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV

This patch implements latest PHY changes in Gain, prop and int co-efficients based on the vco freq. v2: Split the original changes into multiple smaller patches based on review by Ville v3: Addressed Ville's review comments. Fixed the error introduced in v2. Clear the old bits before we modify th

[Intel-gfx] [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold

Initialize lock detect threshold and select coarse threshold for the case where M2 fraction division is disabled. v2: Split the changes into multiple smaller patches based on review by Ville v3: Addressed rest of the review comments. Clear out the old bits before we modify those bits as part of R

[Intel-gfx] [PATCH] drm/i915: Setup all page directories for gen8

If the mappable size is less than what the full range of pdps can address, we end up setting pdps for only the mappable area. The logical context however needs valid pdp entries. Prior to commit 06fda602dbca ("drm/i915: Create page table allocators") we just have been writing pdp entries with dma

Re: [Intel-gfx] [PATCH v2] drm/i915: gen4: work around hang during hibernation

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5868 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -5 278/278

[Intel-gfx] [PATCH] drm/i915: Add debugfs entry for DRRS

From: Vandana Kannan Adding a debugfs entry to determine if DRRS is supported or not V2: [By Ram]: Following details about the active crtc will be filled in seq-file of the debugfs 1. Encoder output type 2. DRRS Support on this CRTC 3. DRRS current state 4

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Disable M2 frac division for integer case

On Tue, Mar 03, 2015 at 08:41:54PM +0530, Vijay Purushothaman wrote: > v2 : Handle M2 frac division for both M2 frac and int cases > > v3 : Addressed Ville's review comments. Cleared the old bits for RMW > > Signed-off-by: Vijay Purushothaman > --- > drivers/gpu/drm/i915/i915_reg.h |1

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use plane->state->fb in watermark code (v2)

On Tue, Mar 03, 2015 at 08:21:44AM -0300, Paulo Zanoni wrote: > Hi > > 2015-02-27 15:12 GMT-03:00 Matt Roper : > > plane->fb is a legacy pointer that not always be up-to-date (or updated > > early enough). Make sure the watermark code uses plane->state->fb so > > that we're always doing our calcu

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold

On Tue, Mar 03, 2015 at 08:43:12PM +0530, Vijay Purushothaman wrote: > Initialize lock detect threshold and select coarse threshold for the > case where M2 fraction division is disabled. > > v2: Split the changes into multiple smaller patches based on review by > Ville > > v3: Addressed rest of t

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV

On Tue, Mar 03, 2015 at 08:44:04PM +0530, Vijay Purushothaman wrote: > This patch implements latest PHY changes in Gain, prop and int co-efficients > based on the vco freq. > > v2: Split the original changes into multiple smaller patches based on > review by Ville > > v3: Addressed Ville's review

Re: [Intel-gfx] [PATCH i-g-t 02/13] lib: Extract igt_buf_write_to_png() from gem_render_copy

On 03/03/2015 02:10 PM, Tvrtko Ursulin wrote: From: Damien Lespiau Now that the Android build has cairo, we can put cairo-dependant code back into lib/ Looks like we'll have to drop this one - Cairo is not available in Android after all. I looked at the following patches and couldn't see

Re: [Intel-gfx] [PATCH i-g-t 02/13] lib: Extract igt_buf_write_to_png() from gem_render_copy

> -Original Message- > From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] > Sent: Tuesday, March 03, 2015 4:04 PM > To: Intel-gfx@lists.freedesktop.org; Lespiau, Damien > Cc: Ceraolo Spurio, Daniele; Gore, Tim > Subject: Re: [Intel-gfx] [PATCH i-g-t 02/13] lib: Extract > igt_buf

Re: [Intel-gfx] [PATCH] drm/i915: Setup all page directories for gen8

On Tue, Mar 03, 2015 at 05:03:29PM +0200, Mika Kuoppala wrote: > If the mappable size is less than what the full range > of pdps can address, we end up setting pdps for only the > mappable area. mappable is not a factor here. The global gtt is 2GiB and we just used the same size for the ppgtt, whi

[Intel-gfx] [PATCH] drm/i915: Fix modeset state confusion in the load detect code

This is a tricky story of the new atomic state handling and the legacy code fighting over each another. The bug at hand is an underrun of the framebuffer reference with subsequent hilarity caused by the load detect code. Which is peculiar since the the exact same code works fine as the implementati

Re: [Intel-gfx] [PATCH 10/12] drm/i915/bdw: Add 4 level support in insert_entries and clear_range

On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry wrote: > When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map > Level 4 (PML4), before it selects which Page Directory Pointer (PDP) > it will write to. > > Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range

Re: [Intel-gfx] [PATCH 11/12] drm/i915: Expand error state's address width to 64b

On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry wrote: > From: Ben Widawsky > > v2: 0 pad the new 8B fields or else intel_error_decode has a hard time. > Note, regardless we need an igt update. > > v3: Make reloc_offset 64b also. > > Signed-off-by: Ben Widawsky > Signed-off-by: Michel Thierry

Re: [Intel-gfx] [PATCH] Revert "drm/i915: Switch planes from transitional helpers to full atomic helpers"

On Mon, Mar 02, 2015 at 04:35:20PM +0100, Daniel Vetter wrote: > This reverts commit 3f678c96abb43a977d2ea41aefccdc49e8a3e896. > > We've been a bit too optimistic with this one here :( > > The trouble is that internally we're still using these plane > update/disable hooks. Which was totally ok pr

Re: [Intel-gfx] i915 driver doesn't find all Modelines that nouveau driver finds

On Tue, 2015-03-03 at 15:31 +0200, Ville Syrjälä wrote: > > I suppose any increase is good. But personally I just couldn't stand > anything below 75Hz when I was still using a CRT. Yeah. 75Hz is what I was using with the nVidia card I replaced with this new motherboard and Celeron G1840. Slight

[Intel-gfx] [PATCH] drm/i915: Add module param to test the load detect code

This is useful for writing igts to make sure we don't break this, without being forced to own a one of these dinosaurs. Suggested-by: Jesse Barnes Cc: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h| 1 + drivers/gpu/drm/i915/i915_params.c | 8 +++- drivers/

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