On Fri, Feb 27, 2015 at 10:22:32AM -0800, jeff.mc...@intel.com wrote:
> From: Jeff McGee
>
> Collect the currently enabled counts of slice, subslice, and
> execution units using the power gate control ack message
> registers specific to Cherryview.
>
> Slice/subslice/EU info and hardware status
On Fri, Feb 27, 2015 at 06:22:43PM +, John Harrison wrote:
> On 27/02/2015 13:35, Daniel Vetter wrote:
> >On Fri, Feb 27, 2015 at 12:22:42PM +, John Harrison wrote:
> >>On 25/02/2015 21:52, Daniel Vetter wrote:
> >>>On Fri, Feb 13, 2015 at 11:48:13AM +, john.c.harri...@intel.com wrote:
On Fri, Feb 27, 2015 at 08:21:07PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 27, 2015 at 08:54:19AM -0800, Matt Roper wrote:
> > Move watermark handling from intel_pm.c to intel_wm.c and add a little
> > bit of kerneldoc to exported functions. We also add a new
> > intel_init_wm() function to setu
On Fri, Feb 27, 2015 at 07:47:46PM +0100, Daniel Vetter wrote:
> On Fri, Feb 27, 2015 at 08:21:07PM +0200, Ville Syrjälä wrote:
> > On Fri, Feb 27, 2015 at 08:54:19AM -0800, Matt Roper wrote:
> > > Move watermark handling from intel_pm.c to intel_wm.c and add a little
> > > bit of kerneldoc to expo
On Fri, Feb 27, 2015 at 10:11:58AM -0800, Matt Roper wrote:
> I'm in the process of reworking watermarks to play more nicely with atomic
> driver design. It sounds like a few people are already running into
> watermark-related problems caused by the atomic changes, so I've extracted a
> few early
igt_kms extensively uses line continuation when dumping state updates
at the debug level. They got badly mangled with the recent changes to
for the log handling functions. Two separate fixes:
- Don't prepend domain and other metainformation when it's just a
continuation line.
- Dont add newlines
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5825
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 282/282
From: Jeff McGee
Total EU was already being detected on CHV, so we just add the
additional info parameters. The detection method is changed to
be more robust in the case of subslice fusing - we don't want
to trust the EU fuse bits corresponding to subslices which are
fused-off.
v2: Fixed subslic
On Fri, Feb 27, 2015 at 12:12:28PM -0800, jeff.mc...@intel.com wrote:
> From: Jeff McGee
>
> Total EU was already being detected on CHV, so we just add the
> additional info parameters. The detection method is changed to
> be more robust in the case of subslice fusing - we don't want
> to trust t
On 02/10/2015 05:28 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Poke at the CBR1_VLV register during init_clock_gating to make sure the
> PND deadline scheme is used.
>
> The hardware has two modes of operation wrt. watermarks:
>
> 1) PND deadline mode:
> - memory reques
On 02/27/2015 10:09 AM, Ville Syrjälä wrote:
> On Fri, Feb 27, 2015 at 09:57:20AM -0800, Jesse Barnes wrote:
>> On 02/10/2015 05:28 AM, ville.syrj...@linux.intel.com wrote:
>>> From: Ville Syrjälä
>>>
>>> Now that we have drm_planes for the cursor and primary we can move the
>>> pixel_size handlin
On Fri, Feb 27, 2015 at 12:38:44PM -0800, Jesse Barnes wrote:
> On 02/10/2015 05:28 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Poke at the CBR1_VLV register during init_clock_gating to make sure the
> > PND deadline scheme is used.
> >
> > The hardware has two modes
cool, thanks for the detailed explanation.
Reviewed-by: Rodrigo Vivi
On Fri, Feb 27, 2015 at 6:04 AM, Daniel Vetter wrote:
> On Thu, Feb 26, 2015 at 05:11:16PM -0800, Rodrigo Vivi wrote:
>> I believe this patch is on the wrong series, right?
>
> It's in here since I've spotted the FIXME while re
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5834
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 282/282
According to spec: "In PSR HW or SW mode, SW set this bit before writing
registers for a flip. It will be self-clear when it gets to the PSR
active state."
Some versions of spec mention that this is needed when in
"Persistent mode" but define it as same as "SW mode". Since this
fix the page flip c
Since the begining there is a missunderstanding on the meaning of this
dpcd bit.
This bit should'n indicate wheter to use link standby or not, but just
be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
since HW is the responsible one.
Even with help of frontbuffer tracki
On Haswell and Broadwell with link in standby when exit event happens
between vblank and VSC packet, PSR exit on panel but DPA transmitter
still sends black pixel. hen this condition hits, panel will intermittently
display black frame.
The known W/A for this case involve the of single_frame update
Since active function on VLV immediately activate PSR let's give more
time for idleness.
v2: Rebase over intel_psr.c and fix typo.
v3: Revival: Manual tests indicated that this is needed. With a short delay
there is a huge risk of getting blank screens when planes are being enabled.
v4: Reviva
With a reliable frontbuffer tracking and all instability corner cases solved
let's re-enabled PSR by default on all supported platforms.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: chandra konduru
Adding i-g-t test case to test display crtc background color.
v2:
- Added IGT_TEST_DESCRIPTION() (Thomas Wood)
- Added to .gitignore (Thomas Wood)
- Added additional details to function header (Thomas Wood)
- Simplified igt_main (Thomas Wood)
Signed-off-by: chandra konduru
This wrong logic and useless define came from first versions and
came along with all rework. Just now I notice how ugly, wrong and
useless this is.
val is already defined as 0 anyway and logic is completelly wrong
and useless. So let's starting the link_standby fix with this
cleaning.
Signed-off-
There are some cases like suspend/resume or dpms off/on sequences
that can flush frontbuffer bits. In these cases features that relies
on frontbuffer tracking can start working and user can stop getting
screen updates on fbcon having impression the system is frozen.
So, let's make sure on fbcon wr
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5835
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 282/282
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5835
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 282/282
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