On Thu, Feb 26, 2015 at 01:29:09PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
> are stored, initially by the Driver, inside the dev_priv->rps structure.
> Since these values are expected to remain same throughout
On Thu, 2015-02-26 at 08:04 +, Chris Wilson wrote:
> On Thu, Feb 26, 2015 at 01:29:09PM +0530, akash.g...@intel.com wrote:
> > From: Akash Goel
> >
> > The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
> > are stored, initially by the Driver, inside the dev_priv->rps struc
On Thu, 26 Feb 2015, Michael Leuchtenburg wrote:
> Okay, here's the results:
> : 12 0a 02 41 00 00 00 00 00 00 00 00 00 0b 00
> 0070: 01 00
> 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 0100: 0a 02 00 09 09 00 00 00 01 00 00
> 0200: 01 00 77 00 01 01 55 00
> 0600: 01
> 0700: 02
> 0
Hi Dave -
First batch of fixes for v4.0-rc, plenty of cc: stable material.
BR,
Jani.
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539:
Linux 4.0-rc1 (2015-02-22 18:21:14 -0800)
are available in the git repository at:
git://anongit.freedesktop.org/drm-intel tags
On Wed, Feb 25, 2015 at 12:46:31PM -0800, Jesse Barnes wrote:
> On 01/28/2015 02:07 AM, Chris Wilson wrote:
> > On Wed, Jan 28, 2015 at 10:50:18AM +0100, Daniel Vetter wrote:
> >> On Wed, Jan 28, 2015 at 09:23:46AM +, Chris Wilson wrote:
> >>> On Wed, Jan 28, 2015 at 10:22:15AM +0100, Daniel Ve
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5820
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 281/281
In a case when DP link has been once trained we can reuse
the existing link training parameters i.e. voltage swing
and pre-emphasis levels from cache when there is a need to
restart link training. In a case of eDP we initially try
to train the link by using the parameter set that we can find
from V
Imre Deak writes:
>> That patch fixes the problem, with only pci_set_power_state commented
>> out. Do you still want me to try with pci_disable_device() commented
>> out as well?
>
> No, but it would help if you could still try the two attached patch
> separately, without any of the previous wor
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
Mostly display control related DPCD addresses.
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 32
1 file changed, 32 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/dr
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 95 ++---
1 file changed, 90 insertions(+), 5 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
i
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
Keep the DPCD macros ordered by address, and make indentation conform to
the rest of the file.
commit e045d20bef41707dbba676e58624b54f9f39e172
Author: Sonika Jindal
Date: Thu Feb 19 13:16:44 2015 +0530
drm: Adding edp1.4 specif
Since we use obj->active as a hint in many places throughout the code,
knowing its state in debugfs is extremely useful.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
At runtime, this helps ensure that the batch pools are kept trim and
fast. Then at suspend, this releases memory that we do not need to
restore. It also ties into the oom-notifier to ensure that we recover as
much kernel memory as possible during OOM.
Signed-off-by: Chris Wilson
---
drivers/gpu/
Combining list_del() with the list_for_each() is actually safe.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_batch_pool.c | 41 +-
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
b/drivers/gp
Now with the trimmed memcpy before the command parser, we try to
allocate many different sizes of batches, predominantly one or two
pages. We can therefore speed up searching for a good sized batch by
keeping the objects of buckets of roughly the same size.
Signed-off-by: Chris Wilson
---
driver
In the next patch, I want to use the structure elsewhere and so require
it defined earlier. Rather than move the definition to an earlier location
where it feels very odd, place it in its own header file.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h| 13 +
I woke up one morning and found 50k objects sitting in the batch pool
and every search seemed to iterate the entire list... Painting the
screen in oils would provide a more fluid display.
One issue with the current design is that we only check for retirements
on the current ring when preparing to
From: Akash Goel
The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
are stored, initially by the Driver, inside the dev_priv->rps structure.
Since these values are expected to remain same throughout, there is no real
need to read this register, on dynamic basis, from certain de
On Thu, Feb 26, 2015 at 04:09:47PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
> are stored, initially by the Driver, inside the dev_priv->rps structure.
> Since these values are expected to remain same throughout
On Thu, Feb 26, 2015 at 11:26:10AM +0200, Mika Kahola wrote:
> In a case when DP link has been once trained we can reuse
> the existing link training parameters i.e. voltage swing
> and pre-emphasis levels from cache when there is a need to
> restart link training. In a case of eDP we initially try
From: Tvrtko Ursulin
So no need to have code which never gets called in the driver.
Signed-off-by: Tvrtko Ursulin
Cc: Matt Roper
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 24
1 file changed, 4 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/int
From: Tvrtko Ursulin
Commit 1da30627fc511a57c9bd23a02c97f0576379f761 "drm: Add rotation value to
plane state" moved the rotation property to DRM core but only did the set
property part. This does the get property part as well.
Signed-off-by: Tvrtko Ursulin
Cc: Matt Roper
---
drivers/gpu/drm/d
The patch "drm/i915: Plumb drm_device through page tables operations"
added an extra parameter, but it didn't update the function description.
Also remove unnecessary blank line added by the same patch.
Found by kbuild test robot.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_
On Thu, Feb 26, 2015 at 10:05:14AM +, Chris Wilson wrote:
> I woke up one morning and found 50k objects sitting in the batch pool
> and every search seemed to iterate the entire list... Painting the
> screen in oils would provide a more fluid display.
Fwiw, I've figured out the culprit here. m
On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 37 +
1 file changed, 37 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index cc96024e8776..07d94
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5821
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3 281/281
On Thu, 26 Feb 2015, sonika wrote:
> On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
>> Signed-off-by: Jani Nikula
>> ---
>> include/drm/drm_dp_helper.h | 37 +
>> 1 file changed, 37 insertions(+)
>>
>> diff --git a/include/drm/drm_dp_helper.h b/i
From: Akash Goel
For SKL, register definition for RPNSWREQ (A008), RPSTAT1(A01C)
have changed slightly. Also on SKL, frequency is specified in
units of 16.66 MHZ, compared to 50 MHZ for most of the earlier
platforms and the time values are expressed in units of 1.33 us,
compared to 1.28 us for ea
From: Akash Goel
On SKL the frequency is specified in units of 16.66 MHZ, barring the
RP_STATE_CAP(0x5998) register, which still reports frequency in units
of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
function for SKL, to store the frequency values as per the actual
From: Akash Goel
On SKL, frequency is specified in units of 16.66 MHZ.
Updated the intel_gpu_freq() and intel_freq_opecode() functions
to do the conversion appropriately.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_pm.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
From: Akash Goel
Added support for SKL in the i915_frequency_info debugfs function
v2:
- corrected the handling of reqf (Damien)
- Reorderd the platform check for cagf (Ville)
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 +
1 file changed, 17
From: Akash Goel
Prior to SKL, the time period programmed in Up/Down EI & Up/Down
threshold registers was in units of 1.28 micro seconds. But for
SKL, the units have changed (1.333 micro seconds).
Have generalized the implementation of gen6_set_rps_thresholds function,
by removing the hard coding
From: Akash Goel
This patch series adds the missing changes, required for proper functioning
of the Turbo feature on SKL.
Most of the changes are mainly due to the fact that on SKL, the frequency has
to be programmed in units of 16.66 MHZ and the time period value programmed
in Up/Down EI & thr
From: Akash Goel
RP Interrupt Up/Down Frequency Limits register (A014) definition
has changed for SKL. Updated the gen6_rps_limits function as per that
v2: Renamed the function to intel_rps_limits (Chris)
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_pm.c | 16 +++-
1 f
From: Akash Goel
On SKL, the frequency is programmed differently in RPNSWREQ (A008)
register (from bits 23 to 31, compared to bits 24 to 31). So updated
the gen6_set_rps function, as per this change.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_pm.c | 5 -
1 file changed, 4 ins
From: Akash Goel
Added support for SKL in the act_freq_mhz_show sysfs function
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/i915_sysfs.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 186
From: Akash Goel
Earlier Turbo interrupts were not being processed for SKL,
as something was amiss in turbo programming for SKL.
Now missing changes have been added, so enabling the Turbo
interrupt processing for SKL.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 f
From: Akash Goel
On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
us for older platforms. So updated the gen9_enable_rps func
On Thu, Feb 26, 2015 at 06:19:41PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> Prior to SKL, the time period programmed in Up/Down EI & Up/Down
> threshold registers was in units of 1.28 micro seconds. But for
> SKL, the units have changed (1.333 micro seconds).
> Have generalized t
On Thu, Feb 26, 2015 at 06:19:37PM +0530, akash.g...@intel.com wrote:
> +#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv->dev) ? \
> + INTERVAL_1_33_US(us) : \
> + INTERVAL_1_28_US(us))
Just use IS_GEN9(dev_priv)
-Chris
--
Chris Wilson, I
On Thu, Feb 26, 2015 at 12:50:16PM +, Chris Wilson wrote:
> On Thu, Feb 26, 2015 at 06:19:37PM +0530, akash.g...@intel.com wrote:
> > +#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv->dev) ? \
> > + INTERVAL_1_33_US(us) : \
> > + INTERVAL_1_
Copypaste-fail from cleanup_planes. Reported by Tvrtko.
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_atomic_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu
On Thu, Feb 26, 2015 at 03:21:13PM +0530, sonika wrote:
>
> On Wednesday 25 February 2015 06:16 PM, Jani Nikula wrote:
> >Mostly display control related DPCD addresses.
> >
> >Signed-off-by: Jani Nikula
> >---
> > include/drm/drm_dp_helper.h | 32
> > 1 file chan
On Thu, Feb 26, 2015 at 09:44:45AM +0200, Ander Conselvan de Oliveira wrote:
> The code in function intel_crtc_compute_config() that evens pipe_src_w
> if necessary would look at the current config instead of the staged one
> when deciding if there is an LVDS encoder in use. This could potentially
On Thu, Feb 26, 2015 at 10:38:28AM +, Chris Wilson wrote:
> On Thu, Feb 26, 2015 at 04:09:47PM +0530, akash.g...@intel.com wrote:
> > From: Akash Goel
> >
> > The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
> > are stored, initially by the Driver, inside the dev_priv->rp
On Thu, Feb 26, 2015 at 11:28:13AM +, Michel Thierry wrote:
> The patch "drm/i915: Plumb drm_device through page tables operations"
> added an extra parameter, but it didn't update the function description.
> Also remove unnecessary blank line added by the same patch.
>
> Found by kbuild test
On Thu, Feb 26, 2015 at 10:05:17AM +, Chris Wilson wrote:
> Combining list_del() with the list_for_each() is actually safe.
Sigh. It's not, the iterator disappears and so iter = iter->next is
unsafe (I was just thinking that the value of iter->next is left
untouched by list_del()). Time to go
From: Tvrtko Ursulin
Commit 1da30627fc511a57c9bd23a02c97f0576379f761 "drm: Add rotation value to
plane state" moved the rotation property to DRM core but only did the set
property part. This does the get property part as well.
Signed-off-by: Tvrtko Ursulin
Cc: Matt Roper
Reviewed-by: Daniel Ve
From: Tvrtko Ursulin
So no need to have code which never gets called in the driver.
Signed-off-by: Tvrtko Ursulin
Cc: Matt Roper
Reviewed-by: Daniel Vetter
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 24
1 file changed, 4 inser
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Thursday, February 26, 2015 12:51 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: DP link training optimization
>
> On Thu, Feb 26, 2015 at 11:26:10A
For MIPI panels requiring higher DSI clk, values needs to be added
in lfsr_converts table for getting the correct values of pll ctrl
and dividor values which gets programmed in cck regs, otherwise DSI
PLL does not get locked leading to no display on the MIPI panel.
Signed-off-by: Gaurav K Singh
-
On Thu, Feb 26, 2015 at 02:19:51PM +, Kahola, Mika wrote:
> > -Original Message-
> > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> > Sent: Thursday, February 26, 2015 12:51 PM
> > To: Kahola, Mika
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5826
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 281/281
From: Deepak S
After feedback from the hardware team we are changing the RC6
promotional timer to increase the power saving without
changing performance.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_r
From: Deepak S
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force off during suspend and allow the force clk as part S0ix
Sequence
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_drv.c | 6 -
From: Deepak S
In normal cases, RC6 promotion timer is 1700us/500us. This will
result in more time spent in C1 state. For more residency in C6
in case of media workloads, this is changed to 250us.
Not doing this for 3D workloads as too many C6-C0 transition
delays can result in performance impact
For both patches:
Reviewed-by: Matt Roper
On Thu, Feb 26, 2015 at 01:49:17PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Commit 1da30627fc511a57c9bd23a02c97f0576379f761 "drm: Add rotation value to
> plane state" moved the rotation property to DRM core but only did the set
> propert
From: Deepak S
Adding few of PM fixes and Improvements for CHV/VLV.
Deepak S (5):
drm/i915/chv: Remove Wait for a previous gfx force-off
drm/i915: Re-adjusting rc6 promotional timer for chv
drm/i915/chv: Set min freq to efficient frequency on chv
drm/i915: Modifying RC6 Promotion timer f
From: Deepak S
After feedback from the hardware team, now we set the GPU min freq to RPe.
If we drop the freq to RPn, we found that the punit was not setting the
voltage to Vnn, So recommendation is to set min freq to RPe.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 f
From: Deepak S
The restriction of pinningFramebuffer to first 256MB is removed from gen8+.
Removing the restriction so that FB can be pinned in any space within
GTT/PPGTT. Also, for gen8+ no need to use pin_mappable for Framebuffer &
also we do not take fence as Framebuffer compression is not ena
Renaming tests massively confuses QA's test result tracking and
blacklisting. So except when really good reasons are around we
shouldn't do it.
Here I think just adding the -hibernat suffix and leaving test names
unchanged is enough.
Cc: David Weinehall
Cc: Imre Deak
Signed-off-by: Daniel Vette
On Thu, Feb 26, 2015 at 08:46:54PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
> sticky bit and it will always be set. So ignore Check for previous
> Gfx force off during suspend and allow the force clk as part S0
From: Ville Syrjälä
On VLV/CHV the media well rc6 residency gets reported separately
from the render well, so add another file to sysfs so that we can
report the residency to the user.
Testcase: igt/pm_rc6_residency --run-subtest media-rc6-accuracy
Reviewed-by: Chris Wilson
Signed-off-by: Ville
From: Deepak S
Added new media_rc6_residency_subtest for chv & vlv.
Signed-off-by: Deepak S
---
tests/pm_rc6_residency.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/pm_rc6_residency.c b/tests/pm_rc6_residency.c
index 1600ac3..f6152da 100644
--- a/tests/pm_
From: Deepak S
With current code we are not considering the RC6 residency during sysfs
read. This is causing test to fail due to incorrect residency_accuracy check
This patch consider code time spent for accuracy check
Signed-off-by: Deepak S
---
tests/pm_rc6_residency.c | 3 ++-
1 file change
On Thursday 26 February 2015 09:13 PM, Ville Syrjälä wrote:
On Thu, Feb 26, 2015 at 08:46:54PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a
sticky bit and it will always be set. So ignore Check for previous
Gfx force
On Wed, Feb 25, 2015 at 04:47:21PM +, Tvrtko Ursulin wrote:
> From: Damien Lespiau
>
> v2: Rebased for addfb2 interface and consolidated a bit. (Tvrtko Ursulin)
> v3: Rebased for fb modifier changes. (Tvrtko Ursulin)
> v4: Use intel_fb_stride_alignment instead of open coding. (Damien Lespiau)
When we takeover from the BIOS and install our interrupt handler, the
BIOS may have left us a few surprises in the form of spontaneous
interrupts. (This is especially likely on hardware like 965gm where
display fifo underruns are continuous and the GMCH cannot filter that
interrupt souce.) As we en
Michel Thierry writes:
> From: Ben Widawsky
>
> Instead of implementing the full tracking + dynamic allocation, this
> patch does a bit less than half of the work, by tracking and warning on
> unexpected conditions. The tracking itself follows which PTEs within a
> page table are currently being
On Thu, Feb 26, 2015 at 09:01:52PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> The restriction of pinningFramebuffer to first 256MB is removed from gen8+.
> Removing the restriction so that FB can be pinned in any space within
> GTT/PPGTT. Also, for gen8+ no need to use pin_mappab
On Thu, Feb 26, 2015 at 08:46:57PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> In normal cases, RC6 promotion timer is 1700us/500us. This will
> result in more time spent in C1 state. For more residency in C6
> in case of media workloads, this is changed to 250us.
> Not doing this
On Thu, Feb 26, 2015 at 08:46:56PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> After feedback from the hardware team, now we set the GPU min freq to RPe.
> If we drop the freq to RPn, we found that the punit was not setting the
> voltage to Vnn, So recommendation is to set min fre
On Thu, Feb 26, 2015 at 04:01:32PM +, Chris Wilson wrote:
> On Thu, Feb 26, 2015 at 09:01:52PM +0530, deepa...@linux.intel.com wrote:
> > From: Deepak S
> >
> > The restriction of pinningFramebuffer to first 256MB is removed from gen8+.
> > Removing the restriction so that FB can be pinned in
On Thu, Feb 26, 2015 at 07:24:24AM -0800, Matt Roper wrote:
> For both patches:
>
> Reviewed-by: Matt Roper
Both merged to drm-misc, thanks.
-Daniel
>
> On Thu, Feb 26, 2015 at 01:49:17PM +, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Commit 1da30627fc511a57c9bd23a02c97f057637
On Wed, Feb 25, 2015 at 04:47:24PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> By this patch all underlying bits have been implemented and this
> patch actually enables the feature.
>
> v2: Validate passed in fb modifiers to reject garbage. (Daniel Vetter)
>
> Signed-off-by: Tvrtko
On Wed, Feb 25, 2015 at 04:47:22PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Recent BSpect updates have changed the watermark calculation to avoid
> display flickering in some cases.
>
> Signed-off-by: Tvrtko Ursulin
> ---
There are really several changes in this patch, it would
On Thu, Feb 26, 2015 at 09:10:27PM +0530, deepa...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> On VLV/CHV the media well rc6 residency gets reported separately
> from the render well, so add another file to sysfs so that we can
> report the residency to the user.
>
> Testcase: igt/pm_rc6_re
Okay, here's the results:
: 12 0a 02 41 00 00 00 00 00 00 00 00 00 0b 00
0070: 01 00
0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0100: 0a 02 00 09 09 00 00 00 01 00 00
0200: 01 00 77 00 01 01 55 00
0600: 01
0700: 02
0701: 88 40 00 00
0720: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note to anyone else who might try this (I sent someone this way from IRC
who was also wondering the same thing about the XPS 13), these patches
don't apply to 4.0-rc1 since they're missing DP_EDP_DPCD_REV (and maybe
some other things, haven't dug in thoroughly yet). Also that patch doesn't
quite ap
On Wed, Feb 18, 2015 at 9:18 PM, Shobhit Kumar wrote:
> The CRC (Crystal Cove) PMIC, controls the panel enable and disable
> signals for BYT for dsi panels. This is indicated in the VBT fields. Use
> that to initialize and use GPIO based control for these signals.
>
> Cc: Linus Walleij
> Cc: Alex
On Thu, Feb 26, 2015 at 09:10:29PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Added new media_rc6_residency_subtest for chv & vlv.
>
> Signed-off-by: Deepak S
Both igt patches merged, thanks.
-Daniel
> ---
> tests/pm_rc6_residency.c | 8 +++-
> 1 file changed, 7 inserti
This printk leads to the following Smatch warning:
drivers/gpu/drm/i915/i915_gem_gtt.c:336 alloc_pt_range()
error: '%pa' expects argument of type 'phys_addr_t*',
argument 5 has type 'struct i915_page_table_entry*'
It looks like a simple typo to me where "%p
On Wed, Feb 25, 2015 at 04:47:23PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Display watermarks need different programming for different tiling
> modes.
>
> Set the relevant flag so this happens during the plane commit and
> add relevant data into a structure made available to the
Not all of the DVO functions were checking the return value from their
i2c routines when reading registers. This could lead to us feeding
garbage values back into the hardware, possible causing further
failures. In some cases the uninitialised stack values were being
written into the kernel log.
Q
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5827
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 281/281
Updates the EDID compliance test function to perform the EDID read as
required by the tests. This read needs to take place in the kernel for
reasons of speed and efficiency. The results of the EDID read operations
are handed off to userspace so that the userspace app can set the display
mode approp
While reviewing the initial 18 patches series Nick noticed one stepping check
didn't look correct, so here a couple of patches to fix that.
--
Damien
Damien Lespiau (2):
drm/i915/skl: Fix stepping check for a couple of W/As
drm/i915/skl: Implement WaDisableVFUnitClockGating
drivers/gpu/drm
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..6849b74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+
Both WaDisableSDEUnitClockGating and WaSetGAPSunitClckGateDisable are
needed on B0 as well.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
inde
On to, 2015-02-26 at 10:34 +0100, Bjørn Mork wrote:
> Imre Deak writes:
>
> >> That patch fixes the problem, with only pci_set_power_state commented
> >> out. Do you still want me to try with pci_disable_device() commented
> >> out as well?
> >
> > No, but it would help if you could still try the
From: Ville Syrjälä
The current minimum vco frequency leaves us with a gap in our supported
frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a
pixel clock of 241.5 MHz, which is just withing that gap. Reduce the
allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 M
From: Ville Syrjälä
DDR DVFS introduces massive memory latencies which can't be handled by
the PND deadline stuff. Instead the watermarks will need to be
programmed to compensate for the latency and the deadlines will need to
be programmed to tight fixed values. That means DDR DVFS can only be
en
From: Ville Syrjälä
CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.
v2: Put the thing into a separate function to avoid churn later
Signed-off
From: Ville Syrjälä
To get 4k resolutions to work reliably with the current watermark
setup we need to further reduce the drain latency.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/int
Imre Deak writes:
> Attached is the proposed fix for this issue.
>
> --Imre
>
> From 5c23657bc168db12a1ba100ab65fabd305c89c8a Mon Sep 17 00:00:00 2001
> From: Imre Deak
> Date: Thu, 26 Feb 2015 18:38:53 +0200
> Subject: [PATCH] drm/i915: gm45: work around hang during hibernation
I can confirm t
On Thu, Feb 26, 2015 at 07:53:54PM +0300, Dan Carpenter wrote:
> This printk leads to the following Smatch warning:
>
> drivers/gpu/drm/i915/i915_gem_gtt.c:336 alloc_pt_range()
> error: '%pa' expects argument of type 'phys_addr_t*',
> argument 5 has type 'struct i
On Thu, Feb 26, 2015 at 08:50:48PM +0200, Imre Deak wrote:
> On to, 2015-02-26 at 10:34 +0100, Bjørn Mork wrote:
> > Imre Deak writes:
> >
> > >> That patch fixes the problem, with only pci_set_power_state commented
> > >> out. Do you still want me to try with pci_disable_device() commented
> > >
On Thu, Feb 26, 2015 at 08:50:48PM +0200, Imre Deak wrote:
> On to, 2015-02-26 at 10:34 +0100, Bjørn Mork wrote:
> > Imre Deak writes:
> >
> > >> That patch fixes the problem, with only pci_set_power_state commented
> > >> out. Do you still want me to try with pci_disable_device() commented
> > >
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5828
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 281/281
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